Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26587

1

T1

200

T2

2

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23002

1

T1

200

T2

2

T3

40

auto[ADC_CTRL_FILTER_COND_OUT]

3585

1

T3

14

T5

2

T8

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20341

1

T1

194

T3

41

T5

3

auto[1]

6246

1

T1

6

T2

2

T3

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22672

1

T1

200

T2

2

T3

42

auto[1]

3915

1

T3

12

T8

17

T11

16

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	679	1			T1	6		T3	13		T35	7
values[0]	44	1			T218	7		T190	1		T285	3
values[1]	602	1			T11	20		T12	12		T13	18
values[2]	2806	1			T2	2		T4	1		T5	1
values[3]	659	1			T13	2		T36	8		T27	18
values[4]	612	1			T5	1		T8	27		T26	15
values[5]	887	1			T5	1		T47	40		T36	11
values[6]	643	1			T26	2		T134	3		T135	1
values[7]	763	1			T12	20		T37	22		T48	4
values[8]	829	1			T6	1		T8	9		T134	1
values[9]	909	1			T3	1		T11	16		T37	1
minimum	17154	1			T1	194		T3	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	629	1			T6	1		T11	20		T12	12
values[1]	2773	1			T2	2		T4	1		T5	1
values[2]	692	1			T36	8		T27	18		T221	1
values[3]	716	1			T5	2		T8	27		T26	15
values[4]	787	1			T47	40		T36	11		T26	2
values[5]	627	1			T48	4		T134	3		T229	3
values[6]	824	1			T12	20		T37	22		T15	3
values[7]	774	1			T6	1		T8	9		T11	16
values[8]	858	1			T3	14		T37	1		T44	4
values[9]	138	1			T48	3		T199	23		T184	1
minimum	17769	1			T1	200		T3	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

4136

1

T8

17

T11

18

T12

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T6	1		T12	7		T13	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	11		T13	1		T39	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1509	1			T2	2		T4	1		T5	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T47	10		T32	8		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T36	6		T221	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T27	1		T138	9		T200	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T26	1		T218	1		T171	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	2		T8	16		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T47	13		T26	1		T29	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T47	9		T36	6		T32	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T229	1		T141	9		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T48	4		T134	1		T137	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T31	7		T232	11		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T12	9		T37	7		T15	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T6	1		T8	3		T11	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T134	1		T217	11		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T36	1		T27	1		T90	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T3	2		T37	1		T44	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T48	3		T184	1		T239	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T199	12		T264	11		T245	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17497	1			T1	200		T3	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T27	1		T285	1		T248	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T12	5		T13	9		T33	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T11	9		T13	1		T40	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	883	1			T13	1		T110	11		T35	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T47	10		T134	5		T223	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T36	2		T153	1		T17	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T27	17		T138	11		T153	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T26	14		T218	1		T190	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T8	11		T136	11		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T47	11		T26	1		T29	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T47	7		T36	5		T246	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T229	2		T224	18		T149	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T134	2		T198	2		T39	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T31	4		T232	9		T198	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	11		T37	15		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	6		T11	7		T137	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T147	4		T149	9		T210	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T36	1		T27	4		T90	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	12		T29	1		T33	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T302	2		T303	8		T304	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T199	11		T264	11		T245	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T15	3		T29	5		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T27	4		T285	4		T248	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	504	1			T1	6		T35	7		T36	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T3	1		T96	1		T19	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T218	7		T190	1		T285	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	7		T13	9		T15	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	11		T27	1		T39	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1572	1			T2	2		T4	1		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	1		T47	10		T32	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	1		T36	6		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T27	1		T138	9		T200	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T26	1		T218	1		T141	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	1		T8	16		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T47	13		T29	3		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T5	1		T47	9		T36	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T26	1		T229	1		T141	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T134	1		T135	1		T137	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T31	7		T232	11		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T12	9		T37	7		T48	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T6	1		T8	3		T137	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T134	1		T217	11		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T11	9		T48	3		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T3	1		T37	1		T44	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17007	1			T1	194		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T40	5		T215	15		T34	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T3	12		T19	3		T264	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T285	2		T302	2		T258	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T12	5		T13	9		T15	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	9		T27	4		T188	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	904	1			T110	11		T35	1		T42	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	1		T47	10		T134	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T13	1		T36	2		T153	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T27	17		T138	11		T153	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T26	14		T218	1		T93	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	11		T136	11		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T47	11		T29	1		T145	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T47	7		T36	5		T246	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T26	1		T229	2		T215	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T134	2		T198	2		T153	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T31	4		T232	9		T198	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	11		T37	15		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T8	6		T137	11		T138	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T139	15		T243	7		T149	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	7		T36	1		T27	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T29	1		T33	7		T38	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T29	5		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	1		T12	6		T13	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	10		T13	2		T39	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1216	1			T2	2		T4	1		T5	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T47	11		T32	1		T134	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T36	6		T221	1		T153	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T27	18		T138	12		T200	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T26	15		T218	2		T171	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T5	2		T8	12		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T47	12		T26	2		T29	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T47	8		T36	8		T32	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T229	3		T141	1		T224	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T48	1		T134	3		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T31	5		T232	10		T198	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	12		T37	16		T15	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T6	1		T8	7		T11	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T134	1		T217	1		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T36	2		T27	5		T90	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T3	14		T37	1		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T48	1		T184	1		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T199	12		T264	12		T245	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17644	1			T1	200		T3	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T27	5		T285	5		T248	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	6		T13	8		T33	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	10		T39	1		T188	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1176	1			T236	30		T237	32		T173	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T47	9		T32	7		T238	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T36	2		T17	5		T230	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T138	8		T200	2		T239	28
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T230	2		T141	10		T148	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T8	15		T136	13		T142	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T47	12		T234	9		T140	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T47	8		T36	3		T32	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T141	8		T215	10		T227	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T48	3		T137	9		T39	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T31	6		T232	10		T212	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T12	8		T37	6		T174	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T8	2		T11	8		T137	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T217	10		T146	2		T147	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T90	9		T232	9		T40	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T44	3		T29	1		T33	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T48	2		T239	2		T97	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T199	11		T264	10		T305	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T15	2		T32	15		T306	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T248	11		T307	7		T271	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	505	1			T1	6		T35	7		T36	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T3	13		T96	1		T19	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T218	1		T190	1		T285	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T12	6		T13	10		T15	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	10		T27	5		T39	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T2	2		T4	1		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	2		T47	11		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	2		T36	6		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T27	18		T138	12		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T26	15		T218	2		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	1		T8	12		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T47	12		T29	4		T145	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	1		T47	8		T36	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T26	2		T229	3		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T134	3		T135	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T31	5		T232	10		T198	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T12	12		T37	16		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T6	1		T8	7		T137	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T134	1		T217	1		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T11	8		T48	1		T36	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T3	1		T37	1		T44	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17154	1			T1	194		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T40	2		T239	2		T215	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T19	3		T264	10		T80	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T218	6		T258	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	6		T13	8		T15	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	10		T39	1		T188	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T33	9		T236	30		T237	32
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T47	9		T32	7		T238	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T36	2		T17	5		T230	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T138	8		T200	2		T239	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T141	10		T252	16		T81	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T8	15		T136	13		T239	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T47	12		T234	9		T140	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T47	8		T36	3		T32	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T141	8		T215	10		T227	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T137	9		T153	8		T139	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T31	6		T232	10		T212	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	8		T37	6		T48	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T8	2		T137	10		T138	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T217	10		T146	2		T139	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	8		T48	2		T90	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T44	3		T29	1		T33	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

auto[0]

4136

1

T8

17

T11

18

T12

14