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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 99.07 96.67 100.00 100.00 98.83 98.33 91.32


Total test records in report: 918
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T305 /workspace/coverage/default/40.adc_ctrl_filters_wakeup.2904318534 May 26 02:35:29 PM PDT 24 May 26 02:36:20 PM PDT 24 187874490994 ps
T321 /workspace/coverage/default/0.adc_ctrl_stress_all.3295659512 May 26 02:31:28 PM PDT 24 May 26 02:40:59 PM PDT 24 531918170488 ps
T290 /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2026993545 May 26 02:33:00 PM PDT 24 May 26 02:46:24 PM PDT 24 344969219951 ps
T62 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.471062831 May 26 02:29:53 PM PDT 24 May 26 02:29:56 PM PDT 24 500777752 ps
T112 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.752630875 May 26 02:30:02 PM PDT 24 May 26 02:30:05 PM PDT 24 1095114337 ps
T63 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3922286099 May 26 02:30:34 PM PDT 24 May 26 02:30:36 PM PDT 24 518498050 ps
T133 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.443827530 May 26 02:29:55 PM PDT 24 May 26 02:29:57 PM PDT 24 1343532285 ps
T799 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3665471745 May 26 02:30:48 PM PDT 24 May 26 02:30:49 PM PDT 24 304276687 ps
T55 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4155115556 May 26 02:29:53 PM PDT 24 May 26 02:31:37 PM PDT 24 46536287849 ps
T800 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1700641654 May 26 02:30:49 PM PDT 24 May 26 02:30:51 PM PDT 24 439096556 ps
T64 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3391064133 May 26 02:30:27 PM PDT 24 May 26 02:30:31 PM PDT 24 466809349 ps
T58 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.524862346 May 26 02:30:11 PM PDT 24 May 26 02:30:22 PM PDT 24 2807657430 ps
T56 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.592200177 May 26 02:30:36 PM PDT 24 May 26 02:30:55 PM PDT 24 4419048414 ps
T57 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2402694629 May 26 02:30:26 PM PDT 24 May 26 02:30:32 PM PDT 24 5240202926 ps
T59 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1487760310 May 26 02:30:41 PM PDT 24 May 26 02:30:54 PM PDT 24 4330819165 ps
T127 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3578202248 May 26 02:30:10 PM PDT 24 May 26 02:30:13 PM PDT 24 481841450 ps
T801 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.716463855 May 26 02:29:44 PM PDT 24 May 26 02:29:47 PM PDT 24 442584564 ps
T60 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2910570973 May 26 02:30:18 PM PDT 24 May 26 02:30:42 PM PDT 24 8603355231 ps
T113 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1147585471 May 26 02:29:45 PM PDT 24 May 26 02:29:50 PM PDT 24 729048936 ps
T128 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2777046658 May 26 02:29:52 PM PDT 24 May 26 02:29:56 PM PDT 24 2428301337 ps
T61 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1580973200 May 26 02:30:17 PM PDT 24 May 26 02:30:32 PM PDT 24 8755964779 ps
T129 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.748877515 May 26 02:30:10 PM PDT 24 May 26 02:30:12 PM PDT 24 569305318 ps
T88 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3370509576 May 26 02:30:33 PM PDT 24 May 26 02:30:37 PM PDT 24 582765448 ps
T65 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2451162256 May 26 02:30:12 PM PDT 24 May 26 02:30:35 PM PDT 24 8335421970 ps
T802 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.389920553 May 26 02:30:36 PM PDT 24 May 26 02:30:38 PM PDT 24 537185664 ps
T73 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1554968836 May 26 02:30:01 PM PDT 24 May 26 02:30:06 PM PDT 24 4148026685 ps
T130 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2633098058 May 26 02:30:01 PM PDT 24 May 26 02:30:09 PM PDT 24 2747950842 ps
T803 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1119788167 May 26 02:30:41 PM PDT 24 May 26 02:30:43 PM PDT 24 289954149 ps
T70 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2703532304 May 26 02:30:21 PM PDT 24 May 26 02:30:24 PM PDT 24 2111899595 ps
T69 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3810281970 May 26 02:30:19 PM PDT 24 May 26 02:30:22 PM PDT 24 757003281 ps
T114 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3838843642 May 26 02:29:52 PM PDT 24 May 26 02:29:53 PM PDT 24 460450544 ps
T804 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.30760740 May 26 02:29:53 PM PDT 24 May 26 02:29:55 PM PDT 24 386745884 ps
T131 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3811160047 May 26 02:30:32 PM PDT 24 May 26 02:30:34 PM PDT 24 2047086607 ps
T132 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2419931353 May 26 02:30:17 PM PDT 24 May 26 02:30:19 PM PDT 24 353812894 ps
T74 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3708666536 May 26 02:30:01 PM PDT 24 May 26 02:30:04 PM PDT 24 427332587 ps
T805 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3500639904 May 26 02:30:33 PM PDT 24 May 26 02:30:36 PM PDT 24 488570932 ps
T115 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2418619253 May 26 02:30:12 PM PDT 24 May 26 02:30:16 PM PDT 24 1094553441 ps
T337 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4213644937 May 26 02:30:32 PM PDT 24 May 26 02:30:37 PM PDT 24 4595897130 ps
T116 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2554924606 May 26 02:30:03 PM PDT 24 May 26 02:30:21 PM PDT 24 21123429514 ps
T806 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.835425246 May 26 02:30:33 PM PDT 24 May 26 02:30:34 PM PDT 24 488286348 ps
T807 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2881414675 May 26 02:30:19 PM PDT 24 May 26 02:30:21 PM PDT 24 535481920 ps
T808 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3509112628 May 26 02:30:09 PM PDT 24 May 26 02:30:12 PM PDT 24 1349129441 ps
T809 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2419361938 May 26 02:30:42 PM PDT 24 May 26 02:30:45 PM PDT 24 409835660 ps
T810 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2918550464 May 26 02:30:41 PM PDT 24 May 26 02:30:45 PM PDT 24 4478341394 ps
T811 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.387414421 May 26 02:30:28 PM PDT 24 May 26 02:30:48 PM PDT 24 5030822656 ps
T812 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3799390825 May 26 02:30:50 PM PDT 24 May 26 02:30:52 PM PDT 24 443992334 ps
T813 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1106140222 May 26 02:29:44 PM PDT 24 May 26 02:29:50 PM PDT 24 10007615515 ps
T814 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.169104970 May 26 02:30:42 PM PDT 24 May 26 02:30:44 PM PDT 24 346996116 ps
T117 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.4197474968 May 26 02:30:09 PM PDT 24 May 26 02:30:12 PM PDT 24 526131941 ps
T118 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2237949554 May 26 02:29:53 PM PDT 24 May 26 02:30:00 PM PDT 24 1164648202 ps
T815 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.4103633112 May 26 02:30:49 PM PDT 24 May 26 02:30:51 PM PDT 24 327773948 ps
T816 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2896412019 May 26 02:30:02 PM PDT 24 May 26 02:30:05 PM PDT 24 429103967 ps
T817 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1539137183 May 26 02:30:19 PM PDT 24 May 26 02:30:24 PM PDT 24 675174985 ps
T818 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2829245911 May 26 02:29:53 PM PDT 24 May 26 02:29:57 PM PDT 24 915700469 ps
T819 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.51823579 May 26 02:30:25 PM PDT 24 May 26 02:30:28 PM PDT 24 444834376 ps
T820 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3207968751 May 26 02:30:17 PM PDT 24 May 26 02:30:19 PM PDT 24 474426003 ps
T821 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1982332264 May 26 02:29:44 PM PDT 24 May 26 02:29:47 PM PDT 24 532550212 ps
T822 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3940736044 May 26 02:30:42 PM PDT 24 May 26 02:30:45 PM PDT 24 353262191 ps
T823 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2841192431 May 26 02:30:11 PM PDT 24 May 26 02:30:13 PM PDT 24 594650625 ps
T824 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2189484335 May 26 02:30:32 PM PDT 24 May 26 02:30:33 PM PDT 24 591951791 ps
T119 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3261708122 May 26 02:29:44 PM PDT 24 May 26 02:29:46 PM PDT 24 789570073 ps
T120 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3354942883 May 26 02:30:00 PM PDT 24 May 26 02:30:04 PM PDT 24 1112602085 ps
T825 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.140261824 May 26 02:30:33 PM PDT 24 May 26 02:30:43 PM PDT 24 4978999026 ps
T826 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2860147594 May 26 02:30:49 PM PDT 24 May 26 02:30:52 PM PDT 24 431394443 ps
T827 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.814874710 May 26 02:30:10 PM PDT 24 May 26 02:30:12 PM PDT 24 427905005 ps
T828 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3081423748 May 26 02:30:49 PM PDT 24 May 26 02:30:52 PM PDT 24 423113609 ps
T829 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2963695493 May 26 02:30:43 PM PDT 24 May 26 02:30:46 PM PDT 24 576191272 ps
T830 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.133939271 May 26 02:30:49 PM PDT 24 May 26 02:30:51 PM PDT 24 414785675 ps
T121 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2498191300 May 26 02:29:53 PM PDT 24 May 26 02:29:59 PM PDT 24 8624756542 ps
T831 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3156917896 May 26 02:29:45 PM PDT 24 May 26 02:29:47 PM PDT 24 1815834243 ps
T125 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2999546582 May 26 02:30:44 PM PDT 24 May 26 02:30:48 PM PDT 24 531425234 ps
T832 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.25228467 May 26 02:30:32 PM PDT 24 May 26 02:30:33 PM PDT 24 360712977 ps
T833 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1366819270 May 26 02:30:48 PM PDT 24 May 26 02:30:49 PM PDT 24 441829550 ps
T834 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.759576790 May 26 02:30:33 PM PDT 24 May 26 02:30:40 PM PDT 24 8395988404 ps
T835 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.607272725 May 26 02:30:10 PM PDT 24 May 26 02:30:13 PM PDT 24 548605028 ps
T836 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.141388446 May 26 02:30:49 PM PDT 24 May 26 02:30:50 PM PDT 24 458025837 ps
T837 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1776407494 May 26 02:30:43 PM PDT 24 May 26 02:30:46 PM PDT 24 440936807 ps
T838 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3247926854 May 26 02:30:41 PM PDT 24 May 26 02:30:44 PM PDT 24 775729313 ps
T122 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1097620548 May 26 02:30:09 PM PDT 24 May 26 02:30:42 PM PDT 24 7690820981 ps
T839 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2841043146 May 26 02:30:25 PM PDT 24 May 26 02:30:32 PM PDT 24 4672848962 ps
T840 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.389672713 May 26 02:30:21 PM PDT 24 May 26 02:30:23 PM PDT 24 537718405 ps
T841 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.44732070 May 26 02:30:02 PM PDT 24 May 26 02:30:04 PM PDT 24 601022922 ps
T842 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1503690302 May 26 02:30:11 PM PDT 24 May 26 02:30:13 PM PDT 24 303927089 ps
T843 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2338507404 May 26 02:30:20 PM PDT 24 May 26 02:30:22 PM PDT 24 456642006 ps
T844 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3020859622 May 26 02:30:50 PM PDT 24 May 26 02:30:53 PM PDT 24 454378043 ps
T845 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2979215421 May 26 02:30:11 PM PDT 24 May 26 02:30:14 PM PDT 24 2073170447 ps
T846 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1879521807 May 26 02:30:35 PM PDT 24 May 26 02:30:42 PM PDT 24 5297923230 ps
T126 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2373149335 May 26 02:30:24 PM PDT 24 May 26 02:30:27 PM PDT 24 372220630 ps
T847 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1171778960 May 26 02:30:43 PM PDT 24 May 26 02:30:46 PM PDT 24 310150574 ps
T848 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1298187530 May 26 02:30:20 PM PDT 24 May 26 02:30:23 PM PDT 24 2434363891 ps
T849 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1786395207 May 26 02:30:12 PM PDT 24 May 26 02:30:15 PM PDT 24 451885607 ps
T850 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3347217231 May 26 02:30:25 PM PDT 24 May 26 02:30:28 PM PDT 24 524651226 ps
T851 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3104559033 May 26 02:29:46 PM PDT 24 May 26 02:29:51 PM PDT 24 824693928 ps
T852 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2313141654 May 26 02:30:09 PM PDT 24 May 26 02:30:11 PM PDT 24 476816908 ps
T853 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.153455750 May 26 02:30:18 PM PDT 24 May 26 02:30:20 PM PDT 24 451871970 ps
T854 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3199197815 May 26 02:29:53 PM PDT 24 May 26 02:30:10 PM PDT 24 8314940954 ps
T855 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2781503489 May 26 02:30:17 PM PDT 24 May 26 02:30:19 PM PDT 24 296682471 ps
T856 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3553368518 May 26 02:30:48 PM PDT 24 May 26 02:30:49 PM PDT 24 475132622 ps
T341 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3039304447 May 26 02:30:25 PM PDT 24 May 26 02:30:29 PM PDT 24 4424146458 ps
T857 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3598973660 May 26 02:30:35 PM PDT 24 May 26 02:30:37 PM PDT 24 298005118 ps
T858 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3994211540 May 26 02:30:42 PM PDT 24 May 26 02:30:47 PM PDT 24 513160536 ps
T859 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1862630044 May 26 02:30:17 PM PDT 24 May 26 02:30:19 PM PDT 24 454451853 ps
T860 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.861766600 May 26 02:30:18 PM PDT 24 May 26 02:30:22 PM PDT 24 2552038496 ps
T861 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.908647642 May 26 02:29:47 PM PDT 24 May 26 02:29:55 PM PDT 24 5033306559 ps
T862 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3382973833 May 26 02:30:10 PM PDT 24 May 26 02:30:13 PM PDT 24 480434233 ps
T863 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3678822255 May 26 02:30:41 PM PDT 24 May 26 02:30:45 PM PDT 24 2545031179 ps
T864 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2126457139 May 26 02:30:50 PM PDT 24 May 26 02:30:52 PM PDT 24 436473468 ps
T865 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1364758713 May 26 02:30:26 PM PDT 24 May 26 02:30:27 PM PDT 24 451117963 ps
T866 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4048348358 May 26 02:30:32 PM PDT 24 May 26 02:30:36 PM PDT 24 776544964 ps
T867 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.836418782 May 26 02:30:33 PM PDT 24 May 26 02:30:35 PM PDT 24 686838689 ps
T868 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3768197279 May 26 02:30:49 PM PDT 24 May 26 02:30:52 PM PDT 24 315817298 ps
T869 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2969263795 May 26 02:29:52 PM PDT 24 May 26 02:29:55 PM PDT 24 575703279 ps
T870 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4271732328 May 26 02:30:48 PM PDT 24 May 26 02:30:49 PM PDT 24 483590210 ps
T871 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2162080483 May 26 02:30:49 PM PDT 24 May 26 02:30:52 PM PDT 24 429894428 ps
T75 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.171118579 May 26 02:30:09 PM PDT 24 May 26 02:30:31 PM PDT 24 8473413921 ps
T872 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3234405847 May 26 02:30:50 PM PDT 24 May 26 02:30:53 PM PDT 24 282350081 ps
T873 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1180111504 May 26 02:30:41 PM PDT 24 May 26 02:30:43 PM PDT 24 510108697 ps
T874 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.198638608 May 26 02:29:53 PM PDT 24 May 26 02:29:55 PM PDT 24 491456079 ps
T875 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1889537837 May 26 02:30:42 PM PDT 24 May 26 02:31:04 PM PDT 24 7942833288 ps
T876 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.832561974 May 26 02:30:42 PM PDT 24 May 26 02:30:44 PM PDT 24 394028647 ps
T123 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1158764558 May 26 02:30:35 PM PDT 24 May 26 02:30:36 PM PDT 24 558838409 ps
T877 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.161064901 May 26 02:29:55 PM PDT 24 May 26 02:29:58 PM PDT 24 476590320 ps
T878 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.536372286 May 26 02:30:33 PM PDT 24 May 26 02:30:35 PM PDT 24 649051210 ps
T879 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.24874330 May 26 02:29:53 PM PDT 24 May 26 02:29:57 PM PDT 24 581006490 ps
T880 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.4170554131 May 26 02:30:50 PM PDT 24 May 26 02:30:52 PM PDT 24 350973206 ps
T881 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2182548033 May 26 02:30:48 PM PDT 24 May 26 02:30:50 PM PDT 24 421333072 ps
T76 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2532127479 May 26 02:30:43 PM PDT 24 May 26 02:30:50 PM PDT 24 4338705356 ps
T882 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3096337627 May 26 02:30:09 PM PDT 24 May 26 02:30:11 PM PDT 24 393841518 ps
T883 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1964522835 May 26 02:30:40 PM PDT 24 May 26 02:30:42 PM PDT 24 561039119 ps
T884 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1217440368 May 26 02:30:49 PM PDT 24 May 26 02:30:51 PM PDT 24 496867791 ps
T885 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3580879053 May 26 02:30:43 PM PDT 24 May 26 02:30:46 PM PDT 24 691793667 ps
T886 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2855210733 May 26 02:30:43 PM PDT 24 May 26 02:30:46 PM PDT 24 374292580 ps
T887 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3186944304 May 26 02:29:53 PM PDT 24 May 26 02:30:06 PM PDT 24 4350395076 ps
T888 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1307137720 May 26 02:30:09 PM PDT 24 May 26 02:30:14 PM PDT 24 4324846091 ps
T889 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3481055749 May 26 02:30:49 PM PDT 24 May 26 02:30:51 PM PDT 24 511191347 ps
T890 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2872177774 May 26 02:30:01 PM PDT 24 May 26 02:30:03 PM PDT 24 532918239 ps
T891 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1365962888 May 26 02:30:43 PM PDT 24 May 26 02:30:45 PM PDT 24 486673717 ps
T892 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3178637377 May 26 02:30:42 PM PDT 24 May 26 02:30:45 PM PDT 24 324347246 ps
T893 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4064361171 May 26 02:30:20 PM PDT 24 May 26 02:30:22 PM PDT 24 420491568 ps
T894 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2796868214 May 26 02:30:35 PM PDT 24 May 26 02:30:38 PM PDT 24 589025304 ps
T895 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.778596423 May 26 02:30:26 PM PDT 24 May 26 02:30:29 PM PDT 24 421089578 ps
T896 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.651154019 May 26 02:30:25 PM PDT 24 May 26 02:30:28 PM PDT 24 424982696 ps
T124 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.17085456 May 26 02:30:25 PM PDT 24 May 26 02:30:27 PM PDT 24 416901114 ps
T338 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1344680071 May 26 02:30:17 PM PDT 24 May 26 02:30:38 PM PDT 24 8007052042 ps
T897 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.629224657 May 26 02:29:46 PM PDT 24 May 26 02:29:50 PM PDT 24 493483915 ps
T898 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3757057514 May 26 02:30:50 PM PDT 24 May 26 02:30:53 PM PDT 24 343614340 ps
T899 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1401701963 May 26 02:29:53 PM PDT 24 May 26 02:29:57 PM PDT 24 467482152 ps
T900 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.623493718 May 26 02:29:53 PM PDT 24 May 26 02:29:56 PM PDT 24 1169478027 ps
T901 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1668882793 May 26 02:30:03 PM PDT 24 May 26 02:30:04 PM PDT 24 510930153 ps
T902 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1654274104 May 26 02:30:26 PM PDT 24 May 26 02:30:27 PM PDT 24 515187341 ps
T903 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.532948089 May 26 02:30:18 PM PDT 24 May 26 02:30:22 PM PDT 24 2480774589 ps
T904 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3269613356 May 26 02:29:44 PM PDT 24 May 26 02:29:46 PM PDT 24 485035038 ps
T905 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.39480560 May 26 02:30:40 PM PDT 24 May 26 02:30:45 PM PDT 24 4516977720 ps
T906 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1539128883 May 26 02:30:41 PM PDT 24 May 26 02:30:46 PM PDT 24 688988115 ps
T907 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1204411636 May 26 02:30:10 PM PDT 24 May 26 02:30:16 PM PDT 24 4484408131 ps
T339 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1214447590 May 26 02:30:35 PM PDT 24 May 26 02:30:40 PM PDT 24 4285867412 ps
T908 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1218399383 May 26 02:30:34 PM PDT 24 May 26 02:30:37 PM PDT 24 597412212 ps
T909 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4017592216 May 26 02:30:25 PM PDT 24 May 26 02:30:27 PM PDT 24 408353462 ps
T910 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1802927336 May 26 02:30:33 PM PDT 24 May 26 02:30:35 PM PDT 24 459202750 ps
T911 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3304305619 May 26 02:30:28 PM PDT 24 May 26 02:30:45 PM PDT 24 4777585057 ps
T340 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3059741048 May 26 02:30:34 PM PDT 24 May 26 02:30:38 PM PDT 24 5601032123 ps
T912 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3177957713 May 26 02:30:49 PM PDT 24 May 26 02:30:52 PM PDT 24 371768877 ps
T913 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.908504175 May 26 02:30:27 PM PDT 24 May 26 02:30:50 PM PDT 24 8372368495 ps
T914 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3607063499 May 26 02:30:49 PM PDT 24 May 26 02:30:52 PM PDT 24 542227087 ps
T915 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3441503644 May 26 02:30:34 PM PDT 24 May 26 02:30:38 PM PDT 24 492342035 ps
T916 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1613581580 May 26 02:30:43 PM PDT 24 May 26 02:30:46 PM PDT 24 508432704 ps
T917 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.4120581391 May 26 02:30:26 PM PDT 24 May 26 02:30:28 PM PDT 24 442294416 ps
T918 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1658048254 May 26 02:30:51 PM PDT 24 May 26 02:30:53 PM PDT 24 512556984 ps

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3400294520
Short name T3
Test name
Test status
Simulation time 334779970602 ps
CPU time 190.98 seconds
Started May 26 02:34:05 PM PDT 24
Finished May 26 02:37:17 PM PDT 24
Peak memory 201904 kb
Host smart-0de7ec9a-5073-4237-bff7-2dc66082118d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400294520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3400294520
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3686593839
Short name T1
Test name
Test status
Simulation time 120436673800 ps
CPU time 665.73 seconds
Started May 26 02:36:52 PM PDT 24
Finished May 26 02:47:58 PM PDT 24
Peak memory 202236 kb
Host smart-4ebdc882-0c7a-4c64-9d12-17ddb1944ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686593839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3686593839
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.303435707
Short name T15
Test name
Test status
Simulation time 41525379017 ps
CPU time 101.85 seconds
Started May 26 02:34:16 PM PDT 24
Finished May 26 02:35:58 PM PDT 24
Peak memory 210444 kb
Host smart-36d8f6b3-5e79-4731-be4f-c817a90e018d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303435707 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.303435707
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.376534836
Short name T47
Test name
Test status
Simulation time 489166296121 ps
CPU time 965.38 seconds
Started May 26 02:33:57 PM PDT 24
Finished May 26 02:50:03 PM PDT 24
Peak memory 201940 kb
Host smart-0c3b37cb-5ad1-4408-9b6f-5e2fc2ff35ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376534836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.376534836
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3454143397
Short name T36
Test name
Test status
Simulation time 557574478666 ps
CPU time 307.15 seconds
Started May 26 02:32:33 PM PDT 24
Finished May 26 02:37:41 PM PDT 24
Peak memory 218132 kb
Host smart-455288d4-c5d7-40d9-b84b-eb5885eb9734
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454143397 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3454143397
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1441221059
Short name T139
Test name
Test status
Simulation time 578583005611 ps
CPU time 381.68 seconds
Started May 26 02:35:29 PM PDT 24
Finished May 26 02:41:52 PM PDT 24
Peak memory 201852 kb
Host smart-26f01da6-d176-4880-83a9-e3a00dccd613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441221059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1441221059
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.677756167
Short name T147
Test name
Test status
Simulation time 481084451962 ps
CPU time 317.09 seconds
Started May 26 02:34:25 PM PDT 24
Finished May 26 02:39:43 PM PDT 24
Peak memory 201860 kb
Host smart-04901b3b-eea4-449a-8638-2fb31d575d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677756167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.677756167
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2783638446
Short name T32
Test name
Test status
Simulation time 550624496810 ps
CPU time 628.66 seconds
Started May 26 02:32:00 PM PDT 24
Finished May 26 02:42:30 PM PDT 24
Peak memory 201908 kb
Host smart-9a1b5420-eeeb-437e-8f1f-b92cc2e941ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783638446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2783638446
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1332204873
Short name T13
Test name
Test status
Simulation time 531089109896 ps
CPU time 215.02 seconds
Started May 26 02:36:59 PM PDT 24
Finished May 26 02:40:35 PM PDT 24
Peak memory 201924 kb
Host smart-3c83f346-f69e-45de-8717-ff3398a44ad7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332204873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1332204873
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.282480239
Short name T29
Test name
Test status
Simulation time 37077280366 ps
CPU time 90.69 seconds
Started May 26 02:32:59 PM PDT 24
Finished May 26 02:34:30 PM PDT 24
Peak memory 210108 kb
Host smart-4d85f262-f495-4d2b-8a30-ac219db5b270
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282480239 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.282480239
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3391064133
Short name T64
Test name
Test status
Simulation time 466809349 ps
CPU time 3.52 seconds
Started May 26 02:30:27 PM PDT 24
Finished May 26 02:30:31 PM PDT 24
Peak memory 202052 kb
Host smart-cdfe3f49-a056-4023-8bbd-43f58a51a43e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391064133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3391064133
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.911925640
Short name T215
Test name
Test status
Simulation time 506596093818 ps
CPU time 435.57 seconds
Started May 26 02:31:50 PM PDT 24
Finished May 26 02:39:06 PM PDT 24
Peak memory 201960 kb
Host smart-e91a69a3-30ce-477a-893f-659ce8cf5552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911925640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.911925640
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.368121876
Short name T26
Test name
Test status
Simulation time 328939614489 ps
CPU time 77.69 seconds
Started May 26 02:36:04 PM PDT 24
Finished May 26 02:37:23 PM PDT 24
Peak memory 201832 kb
Host smart-ae525087-b137-4cfc-a075-3c6e4795e567
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368121876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
368121876
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.731388406
Short name T138
Test name
Test status
Simulation time 342530521154 ps
CPU time 105.85 seconds
Started May 26 02:33:39 PM PDT 24
Finished May 26 02:35:25 PM PDT 24
Peak memory 201872 kb
Host smart-4db11224-788c-4821-b880-e9d3d9bce86e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731388406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.731388406
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3700757267
Short name T366
Test name
Test status
Simulation time 532381971 ps
CPU time 1.8 seconds
Started May 26 02:32:04 PM PDT 24
Finished May 26 02:32:07 PM PDT 24
Peak memory 201548 kb
Host smart-b58745ae-bea2-4c2a-b39f-be5c82a85192
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700757267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3700757267
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2050482397
Short name T239
Test name
Test status
Simulation time 572533527524 ps
CPU time 1302.73 seconds
Started May 26 02:32:41 PM PDT 24
Finished May 26 02:54:24 PM PDT 24
Peak memory 201820 kb
Host smart-d8c80cc9-fbbe-4a0d-ad57-63baa08a9db7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050482397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2050482397
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.280371392
Short name T27
Test name
Test status
Simulation time 497746221616 ps
CPU time 346.83 seconds
Started May 26 02:35:25 PM PDT 24
Finished May 26 02:41:13 PM PDT 24
Peak memory 201860 kb
Host smart-f07386be-9317-4b33-bab4-38457c586554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280371392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.280371392
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4155115556
Short name T55
Test name
Test status
Simulation time 46536287849 ps
CPU time 102.96 seconds
Started May 26 02:29:53 PM PDT 24
Finished May 26 02:31:37 PM PDT 24
Peak memory 202008 kb
Host smart-a4c8d859-01e5-4014-935f-55a3ef1f8456
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155115556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.4155115556
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.621959833
Short name T68
Test name
Test status
Simulation time 7863935788 ps
CPU time 9.78 seconds
Started May 26 02:31:26 PM PDT 24
Finished May 26 02:31:37 PM PDT 24
Peak memory 218452 kb
Host smart-eba0f3ca-6d62-45d0-ae8d-682e705871b6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621959833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.621959833
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1357658733
Short name T136
Test name
Test status
Simulation time 481767705218 ps
CPU time 842.56 seconds
Started May 26 02:31:50 PM PDT 24
Finished May 26 02:45:54 PM PDT 24
Peak memory 210396 kb
Host smart-ba9194d7-0553-47a4-83a9-a9768e9e4e8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357658733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1357658733
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.228034914
Short name T270
Test name
Test status
Simulation time 355741346245 ps
CPU time 306.05 seconds
Started May 26 02:35:28 PM PDT 24
Finished May 26 02:40:35 PM PDT 24
Peak memory 210516 kb
Host smart-7f1a85c6-c2f7-4c58-ac0a-29196995e6a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228034914 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.228034914
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3601044322
Short name T11
Test name
Test status
Simulation time 348018968639 ps
CPU time 741.43 seconds
Started May 26 02:33:43 PM PDT 24
Finished May 26 02:46:05 PM PDT 24
Peak memory 201908 kb
Host smart-6466ec36-2cee-4ec6-8f90-5c3eebcc8cd1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601044322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3601044322
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3989803964
Short name T254
Test name
Test status
Simulation time 338643030827 ps
CPU time 238.76 seconds
Started May 26 02:32:25 PM PDT 24
Finished May 26 02:36:24 PM PDT 24
Peak memory 201876 kb
Host smart-c1d10109-4e9a-4cbf-a22f-1930fa7cca0b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989803964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3989803964
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1490826358
Short name T153
Test name
Test status
Simulation time 531812823391 ps
CPU time 127.84 seconds
Started May 26 02:32:46 PM PDT 24
Finished May 26 02:34:54 PM PDT 24
Peak memory 201872 kb
Host smart-c51d29b0-093d-4a6c-a77a-385e6f706242
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490826358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1490826358
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.152066267
Short name T17
Test name
Test status
Simulation time 115571683927 ps
CPU time 268.02 seconds
Started May 26 02:36:13 PM PDT 24
Finished May 26 02:40:42 PM PDT 24
Peak memory 210164 kb
Host smart-cd83066c-1b64-49eb-b5a0-99b845772c05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152066267 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.152066267
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3261565914
Short name T38
Test name
Test status
Simulation time 407299990163 ps
CPU time 584.89 seconds
Started May 26 02:36:04 PM PDT 24
Finished May 26 02:45:50 PM PDT 24
Peak memory 210752 kb
Host smart-263b87c8-63e9-4634-a353-6cbbd00674f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261565914 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3261565914
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1238266337
Short name T226
Test name
Test status
Simulation time 514302534101 ps
CPU time 334.92 seconds
Started May 26 02:36:11 PM PDT 24
Finished May 26 02:41:48 PM PDT 24
Peak memory 201916 kb
Host smart-5f349615-700c-4b23-aab1-17787f4db62d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238266337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1238266337
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.530553481
Short name T110
Test name
Test status
Simulation time 169854941809 ps
CPU time 300.15 seconds
Started May 26 02:32:03 PM PDT 24
Finished May 26 02:37:04 PM PDT 24
Peak memory 201828 kb
Host smart-05457e1b-0412-4a75-a819-99901a10e467
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=530553481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrup
t_fixed.530553481
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.453382722
Short name T285
Test name
Test status
Simulation time 330106193835 ps
CPU time 768.15 seconds
Started May 26 02:32:32 PM PDT 24
Finished May 26 02:45:21 PM PDT 24
Peak memory 201876 kb
Host smart-6dd86544-5779-405b-ae01-88d80327fe10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453382722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.453382722
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.229257651
Short name T142
Test name
Test status
Simulation time 485036142831 ps
CPU time 272.94 seconds
Started May 26 02:34:23 PM PDT 24
Finished May 26 02:38:56 PM PDT 24
Peak memory 202004 kb
Host smart-7bef40ba-b25b-45cf-8430-6974ae6ef515
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229257651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.229257651
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.475908352
Short name T213
Test name
Test status
Simulation time 657816341819 ps
CPU time 164.51 seconds
Started May 26 02:32:05 PM PDT 24
Finished May 26 02:34:51 PM PDT 24
Peak memory 201752 kb
Host smart-907a6b92-7a88-46cf-b70c-d3fdb7cc565e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475908352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
475908352
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1580973200
Short name T61
Test name
Test status
Simulation time 8755964779 ps
CPU time 13.87 seconds
Started May 26 02:30:17 PM PDT 24
Finished May 26 02:30:32 PM PDT 24
Peak memory 202160 kb
Host smart-0fe2d4ce-7bff-41b6-ac88-59ed3ae46572
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580973200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1580973200
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.604934478
Short name T216
Test name
Test status
Simulation time 536782599265 ps
CPU time 783.44 seconds
Started May 26 02:33:18 PM PDT 24
Finished May 26 02:46:22 PM PDT 24
Peak memory 201932 kb
Host smart-477bc472-55c1-4aaa-9e30-858b0722c357
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604934478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.604934478
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1828899714
Short name T276
Test name
Test status
Simulation time 360438905147 ps
CPU time 246.86 seconds
Started May 26 02:35:48 PM PDT 24
Finished May 26 02:39:56 PM PDT 24
Peak memory 201864 kb
Host smart-89e76f40-a8a8-49f3-9852-7e4257eb9250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828899714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1828899714
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1837335797
Short name T157
Test name
Test status
Simulation time 345835423084 ps
CPU time 835.52 seconds
Started May 26 02:33:43 PM PDT 24
Finished May 26 02:47:39 PM PDT 24
Peak memory 201844 kb
Host smart-e5e44d4e-7c90-4980-89f7-85988166140d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837335797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1837335797
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2075308789
Short name T268
Test name
Test status
Simulation time 329053711594 ps
CPU time 108.73 seconds
Started May 26 02:34:48 PM PDT 24
Finished May 26 02:36:37 PM PDT 24
Peak memory 201868 kb
Host smart-5f57a8ac-846f-4494-bc15-9b22bde358f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075308789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2075308789
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.294907695
Short name T243
Test name
Test status
Simulation time 358440938697 ps
CPU time 803.53 seconds
Started May 26 02:36:51 PM PDT 24
Finished May 26 02:50:16 PM PDT 24
Peak memory 201872 kb
Host smart-40a7d35f-6156-428c-bee9-c4ad32c793f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294907695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
294907695
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1786902619
Short name T246
Test name
Test status
Simulation time 495373432652 ps
CPU time 558.51 seconds
Started May 26 02:31:37 PM PDT 24
Finished May 26 02:40:56 PM PDT 24
Peak memory 201796 kb
Host smart-be39cada-3221-4c89-904e-a9a0456ed5aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786902619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1786902619
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.278263656
Short name T199
Test name
Test status
Simulation time 204823928021 ps
CPU time 127.47 seconds
Started May 26 02:31:59 PM PDT 24
Finished May 26 02:34:08 PM PDT 24
Peak memory 201856 kb
Host smart-e6e3873a-dac2-4032-8469-e7c310c48f1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278263656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
278263656
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2065147713
Short name T294
Test name
Test status
Simulation time 525585243234 ps
CPU time 609.75 seconds
Started May 26 02:33:57 PM PDT 24
Finished May 26 02:44:07 PM PDT 24
Peak memory 201900 kb
Host smart-5dc67a65-b663-4835-bcbb-563a44aa72a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065147713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2065147713
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3295659512
Short name T321
Test name
Test status
Simulation time 531918170488 ps
CPU time 569.66 seconds
Started May 26 02:31:28 PM PDT 24
Finished May 26 02:40:59 PM PDT 24
Peak memory 201812 kb
Host smart-0fb61bdd-4419-4908-b8a8-2fe744f13597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295659512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3295659512
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.289112957
Short name T212
Test name
Test status
Simulation time 357031683772 ps
CPU time 780.82 seconds
Started May 26 02:32:25 PM PDT 24
Finished May 26 02:45:26 PM PDT 24
Peak memory 212272 kb
Host smart-47944f14-3889-4747-9f99-a1735379f97a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289112957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
289112957
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1109891119
Short name T141
Test name
Test status
Simulation time 573464251559 ps
CPU time 208.45 seconds
Started May 26 02:31:27 PM PDT 24
Finished May 26 02:34:57 PM PDT 24
Peak memory 201800 kb
Host smart-255cd412-079b-4660-b6f3-a1a18b5ae88d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109891119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1109891119
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1358446402
Short name T39
Test name
Test status
Simulation time 212404877327 ps
CPU time 108.28 seconds
Started May 26 02:33:48 PM PDT 24
Finished May 26 02:35:37 PM PDT 24
Peak memory 210516 kb
Host smart-c406f95d-f125-41bd-88fc-098adebf6ee8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358446402 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1358446402
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3838843642
Short name T114
Test name
Test status
Simulation time 460450544 ps
CPU time 0.99 seconds
Started May 26 02:29:52 PM PDT 24
Finished May 26 02:29:53 PM PDT 24
Peak memory 201740 kb
Host smart-f706aa90-8044-4ffd-b3c5-cd6a189421e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838843642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3838843642
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1147585471
Short name T113
Test name
Test status
Simulation time 729048936 ps
CPU time 3.86 seconds
Started May 26 02:29:45 PM PDT 24
Finished May 26 02:29:50 PM PDT 24
Peak memory 201908 kb
Host smart-dd134068-b207-4f5d-8edf-89e4a212a2ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147585471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1147585471
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.4135139257
Short name T33
Test name
Test status
Simulation time 350075017843 ps
CPU time 847.75 seconds
Started May 26 02:34:47 PM PDT 24
Finished May 26 02:48:55 PM PDT 24
Peak memory 201756 kb
Host smart-e4a49c8c-5f8c-4f37-99b6-4534f963ed81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135139257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.4135139257
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3734036207
Short name T271
Test name
Test status
Simulation time 145394337088 ps
CPU time 193.97 seconds
Started May 26 02:31:31 PM PDT 24
Finished May 26 02:34:45 PM PDT 24
Peak memory 210172 kb
Host smart-6a91b9cb-d4ef-46f5-93ad-00441d0caf57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734036207 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3734036207
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1460360209
Short name T320
Test name
Test status
Simulation time 357908242930 ps
CPU time 224.6 seconds
Started May 26 02:32:31 PM PDT 24
Finished May 26 02:36:17 PM PDT 24
Peak memory 201828 kb
Host smart-50eca0dc-0615-4bb4-a3cc-dadb9d24de14
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460360209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1460360209
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2664359502
Short name T190
Test name
Test status
Simulation time 490721495058 ps
CPU time 1229.44 seconds
Started May 26 02:32:41 PM PDT 24
Finished May 26 02:53:12 PM PDT 24
Peak memory 201940 kb
Host smart-d661c49a-8822-4a95-a04a-ffef6ae5b7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664359502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2664359502
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3676325183
Short name T250
Test name
Test status
Simulation time 326729077596 ps
CPU time 415.23 seconds
Started May 26 02:33:34 PM PDT 24
Finished May 26 02:40:30 PM PDT 24
Peak memory 201864 kb
Host smart-3bb06328-9612-4a2c-82ad-03a556011854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676325183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3676325183
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2589020489
Short name T35
Test name
Test status
Simulation time 93226152554 ps
CPU time 73.41 seconds
Started May 26 02:37:01 PM PDT 24
Finished May 26 02:38:15 PM PDT 24
Peak memory 202316 kb
Host smart-832d926a-8216-4b3f-8d26-497524c43b37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589020489 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2589020489
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3185616234
Short name T230
Test name
Test status
Simulation time 339010833838 ps
CPU time 162.52 seconds
Started May 26 02:31:34 PM PDT 24
Finished May 26 02:34:18 PM PDT 24
Peak memory 201820 kb
Host smart-f9382c89-e892-4673-833a-3fbbebac84aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185616234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3185616234
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.202585601
Short name T257
Test name
Test status
Simulation time 356872232927 ps
CPU time 246.49 seconds
Started May 26 02:33:03 PM PDT 24
Finished May 26 02:37:11 PM PDT 24
Peak memory 201868 kb
Host smart-d1188bb9-f052-45c7-bcce-f7857d99a232
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202585601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
202585601
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1613851627
Short name T288
Test name
Test status
Simulation time 98932283837 ps
CPU time 56.73 seconds
Started May 26 02:31:46 PM PDT 24
Finished May 26 02:32:44 PM PDT 24
Peak memory 202076 kb
Host smart-b44e95b9-f47c-4ece-8bd6-b6690ba24b0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613851627 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1613851627
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3362592046
Short name T284
Test name
Test status
Simulation time 162176835456 ps
CPU time 31.73 seconds
Started May 26 02:35:02 PM PDT 24
Finished May 26 02:35:35 PM PDT 24
Peak memory 201800 kb
Host smart-08c6a64c-a6ae-41a0-9051-624159b36db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362592046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3362592046
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1784371745
Short name T203
Test name
Test status
Simulation time 516174614401 ps
CPU time 680.55 seconds
Started May 26 02:31:39 PM PDT 24
Finished May 26 02:43:00 PM PDT 24
Peak memory 210428 kb
Host smart-d4322393-4a83-4f20-904a-5932a7482a0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784371745 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1784371745
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.617431901
Short name T161
Test name
Test status
Simulation time 568472839474 ps
CPU time 398.34 seconds
Started May 26 02:35:41 PM PDT 24
Finished May 26 02:42:21 PM PDT 24
Peak memory 201860 kb
Host smart-cf4b5c5b-fec8-4245-8e5a-c20afd338365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617431901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.617431901
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.218566781
Short name T311
Test name
Test status
Simulation time 171922585112 ps
CPU time 202.19 seconds
Started May 26 02:36:17 PM PDT 24
Finished May 26 02:39:40 PM PDT 24
Peak memory 201784 kb
Host smart-f17d46d0-6f7e-42a0-8f06-70e1a46da77c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218566781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.218566781
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3612110308
Short name T309
Test name
Test status
Simulation time 174914100959 ps
CPU time 378.3 seconds
Started May 26 02:31:38 PM PDT 24
Finished May 26 02:37:57 PM PDT 24
Peak memory 201868 kb
Host smart-ad193d31-b2c4-4715-a757-ad139be607c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612110308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3612110308
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3358351573
Short name T259
Test name
Test status
Simulation time 556629708849 ps
CPU time 313.55 seconds
Started May 26 02:32:15 PM PDT 24
Finished May 26 02:37:29 PM PDT 24
Peak memory 201856 kb
Host smart-5f292f96-09d9-4a84-b1b8-38210c32f7de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358351573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3358351573
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3002390037
Short name T231
Test name
Test status
Simulation time 493776426059 ps
CPU time 1237.98 seconds
Started May 26 02:32:47 PM PDT 24
Finished May 26 02:53:26 PM PDT 24
Peak memory 201924 kb
Host smart-6ce3ae26-87b7-4ce0-a0e3-ba3320bd56df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002390037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3002390037
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1802298481
Short name T245
Test name
Test status
Simulation time 487035670691 ps
CPU time 1192.54 seconds
Started May 26 02:36:10 PM PDT 24
Finished May 26 02:56:04 PM PDT 24
Peak memory 201828 kb
Host smart-266169e6-1686-450b-94ae-4550ce8d274d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802298481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1802298481
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.4210440914
Short name T316
Test name
Test status
Simulation time 320101159392 ps
CPU time 119.78 seconds
Started May 26 02:36:27 PM PDT 24
Finished May 26 02:38:28 PM PDT 24
Peak memory 201860 kb
Host smart-54a5a30e-5c67-4b99-9ae9-5bcf29edc28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210440914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.4210440914
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.500750537
Short name T287
Test name
Test status
Simulation time 83219137012 ps
CPU time 170.32 seconds
Started May 26 02:36:35 PM PDT 24
Finished May 26 02:39:26 PM PDT 24
Peak memory 210092 kb
Host smart-79bba851-c0fb-4d9c-b8b6-c3d290357e12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500750537 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.500750537
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1214447590
Short name T339
Test name
Test status
Simulation time 4285867412 ps
CPU time 4.05 seconds
Started May 26 02:30:35 PM PDT 24
Finished May 26 02:30:40 PM PDT 24
Peak memory 202004 kb
Host smart-0adefe8c-9904-4a64-b6c3-d67e6bb7848d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214447590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1214447590
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1843312368
Short name T301
Test name
Test status
Simulation time 1065371107215 ps
CPU time 391.75 seconds
Started May 26 02:31:58 PM PDT 24
Finished May 26 02:38:32 PM PDT 24
Peak memory 210480 kb
Host smart-72d740c2-1767-432a-a2c4-f7a1e58ec51e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843312368 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1843312368
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.405275675
Short name T291
Test name
Test status
Simulation time 572699509662 ps
CPU time 917.34 seconds
Started May 26 02:33:11 PM PDT 24
Finished May 26 02:48:29 PM PDT 24
Peak memory 201872 kb
Host smart-e01422fe-ebfb-470d-b93b-865c9f5030b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405275675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.405275675
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1974047821
Short name T241
Test name
Test status
Simulation time 216043305847 ps
CPU time 221.23 seconds
Started May 26 02:33:41 PM PDT 24
Finished May 26 02:37:23 PM PDT 24
Peak memory 210376 kb
Host smart-ae55d3d5-09d7-4bbf-8728-090f08345a02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974047821 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1974047821
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.153186950
Short name T269
Test name
Test status
Simulation time 332603511978 ps
CPU time 186.64 seconds
Started May 26 02:34:04 PM PDT 24
Finished May 26 02:37:11 PM PDT 24
Peak memory 201944 kb
Host smart-1f7b61dd-5a3e-4906-b4bf-151df11d0a8e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153186950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gati
ng.153186950
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2779433762
Short name T146
Test name
Test status
Simulation time 368295445121 ps
CPU time 547.96 seconds
Started May 26 02:34:15 PM PDT 24
Finished May 26 02:43:24 PM PDT 24
Peak memory 201856 kb
Host smart-8bfbad29-d37e-4baa-ba2e-6e8a386a1e55
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779433762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2779433762
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.726992193
Short name T317
Test name
Test status
Simulation time 342947956391 ps
CPU time 206.13 seconds
Started May 26 02:35:02 PM PDT 24
Finished May 26 02:38:29 PM PDT 24
Peak memory 201928 kb
Host smart-56e41d6f-ab07-4140-82d0-85c7619e8ac6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726992193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.726992193
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1826762308
Short name T263
Test name
Test status
Simulation time 202600207399 ps
CPU time 506.14 seconds
Started May 26 02:36:27 PM PDT 24
Finished May 26 02:44:55 PM PDT 24
Peak memory 201832 kb
Host smart-44da5a86-50be-49c4-b804-6fc372479e67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826762308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1826762308
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.4082253563
Short name T308
Test name
Test status
Simulation time 488150996948 ps
CPU time 557.54 seconds
Started May 26 02:36:28 PM PDT 24
Finished May 26 02:45:47 PM PDT 24
Peak memory 201868 kb
Host smart-fa249370-6f8b-4476-9a03-790ed82f9a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082253563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.4082253563
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.759576790
Short name T834
Test name
Test status
Simulation time 8395988404 ps
CPU time 6.72 seconds
Started May 26 02:30:33 PM PDT 24
Finished May 26 02:30:40 PM PDT 24
Peak memory 201984 kb
Host smart-7b456028-13e2-42d1-ae7f-65d7fe8831f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759576790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_in
tg_err.759576790
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.1924318175
Short name T345
Test name
Test status
Simulation time 107193295866 ps
CPU time 344.7 seconds
Started May 26 02:31:59 PM PDT 24
Finished May 26 02:37:46 PM PDT 24
Peak memory 202336 kb
Host smart-c9d7c002-61e8-4feb-a143-bc46f12c462e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924318175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1924318175
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2378849192
Short name T256
Test name
Test status
Simulation time 540963179552 ps
CPU time 949.96 seconds
Started May 26 02:32:01 PM PDT 24
Finished May 26 02:47:52 PM PDT 24
Peak memory 201828 kb
Host smart-6fc5bbf7-7811-42ef-8c96-3d00d2f2d32e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378849192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2378849192
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.40111614
Short name T303
Test name
Test status
Simulation time 492096839438 ps
CPU time 1213.17 seconds
Started May 26 02:31:59 PM PDT 24
Finished May 26 02:52:14 PM PDT 24
Peak memory 201872 kb
Host smart-928429db-bdbd-4798-a2e2-8dc1047b508c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40111614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.40111614
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1143167041
Short name T343
Test name
Test status
Simulation time 19682051412 ps
CPU time 57.58 seconds
Started May 26 02:32:15 PM PDT 24
Finished May 26 02:33:13 PM PDT 24
Peak memory 217956 kb
Host smart-96146aeb-a77c-4a54-8404-5729bb9dce89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143167041 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1143167041
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.4249617818
Short name T306
Test name
Test status
Simulation time 182229207161 ps
CPU time 412.91 seconds
Started May 26 02:32:55 PM PDT 24
Finished May 26 02:39:48 PM PDT 24
Peak memory 201916 kb
Host smart-5b79298b-5e17-447a-9f00-70aa2df6dac1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249617818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.4249617818
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1806630039
Short name T40
Test name
Test status
Simulation time 252018251215 ps
CPU time 195.3 seconds
Started May 26 02:33:56 PM PDT 24
Finished May 26 02:37:12 PM PDT 24
Peak memory 210184 kb
Host smart-a38082d7-772e-4ceb-9a15-3066083f5774
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806630039 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1806630039
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.2717588986
Short name T12
Test name
Test status
Simulation time 410463523244 ps
CPU time 192.27 seconds
Started May 26 02:34:16 PM PDT 24
Finished May 26 02:37:29 PM PDT 24
Peak memory 201844 kb
Host smart-0edef606-db50-47e1-ad6a-b11e6a3cfb07
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717588986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.2717588986
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.467361670
Short name T293
Test name
Test status
Simulation time 182594620209 ps
CPU time 100.69 seconds
Started May 26 02:34:54 PM PDT 24
Finished May 26 02:36:36 PM PDT 24
Peak memory 201840 kb
Host smart-4ced27da-da46-42a4-98b0-54de79481344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467361670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.467361670
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1931552484
Short name T240
Test name
Test status
Simulation time 115106936922 ps
CPU time 135.03 seconds
Started May 26 02:35:10 PM PDT 24
Finished May 26 02:37:25 PM PDT 24
Peak memory 210132 kb
Host smart-ab40e250-d022-4abf-9384-1c8e8b36bc9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931552484 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1931552484
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1401812884
Short name T258
Test name
Test status
Simulation time 348682615486 ps
CPU time 815.33 seconds
Started May 26 02:31:31 PM PDT 24
Finished May 26 02:45:07 PM PDT 24
Peak memory 201832 kb
Host smart-8b3ac28e-ccf4-4732-b4f0-af60e6ce387d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401812884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1401812884
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3621336548
Short name T351
Test name
Test status
Simulation time 111901264501 ps
CPU time 513.84 seconds
Started May 26 02:36:59 PM PDT 24
Finished May 26 02:45:33 PM PDT 24
Peak memory 202136 kb
Host smart-33d2fc16-1df0-4b0f-8a72-6625497f26ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621336548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3621336548
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3104559033
Short name T851
Test name
Test status
Simulation time 824693928 ps
CPU time 3.97 seconds
Started May 26 02:29:46 PM PDT 24
Finished May 26 02:29:51 PM PDT 24
Peak memory 201964 kb
Host smart-74756595-a4d1-4926-8318-be31e60b009a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104559033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3104559033
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2498191300
Short name T121
Test name
Test status
Simulation time 8624756542 ps
CPU time 4.39 seconds
Started May 26 02:29:53 PM PDT 24
Finished May 26 02:29:59 PM PDT 24
Peak memory 202008 kb
Host smart-31b5b7dc-07b0-4788-8df9-a89c007b3cc5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498191300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2498191300
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.443827530
Short name T133
Test name
Test status
Simulation time 1343532285 ps
CPU time 1.37 seconds
Started May 26 02:29:55 PM PDT 24
Finished May 26 02:29:57 PM PDT 24
Peak memory 201744 kb
Host smart-c7db76e2-4e65-4217-b26b-afaaec38677a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443827530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.443827530
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2969263795
Short name T869
Test name
Test status
Simulation time 575703279 ps
CPU time 2.15 seconds
Started May 26 02:29:52 PM PDT 24
Finished May 26 02:29:55 PM PDT 24
Peak memory 201780 kb
Host smart-0d5b4b98-2cc6-4448-838b-13b6cb669f68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969263795 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2969263795
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.30760740
Short name T804
Test name
Test status
Simulation time 386745884 ps
CPU time 0.85 seconds
Started May 26 02:29:53 PM PDT 24
Finished May 26 02:29:55 PM PDT 24
Peak memory 201684 kb
Host smart-3b085af4-5a15-4384-a680-aa5e7cbdc692
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30760740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.30760740
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.908647642
Short name T861
Test name
Test status
Simulation time 5033306559 ps
CPU time 7.18 seconds
Started May 26 02:29:47 PM PDT 24
Finished May 26 02:29:55 PM PDT 24
Peak memory 201880 kb
Host smart-e7278bb7-48b6-4e92-9ca3-6ad58ef75f18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908647642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.908647642
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.629224657
Short name T897
Test name
Test status
Simulation time 493483915 ps
CPU time 2.66 seconds
Started May 26 02:29:46 PM PDT 24
Finished May 26 02:29:50 PM PDT 24
Peak memory 201960 kb
Host smart-fcc33518-b58b-4425-b562-c832ae0c7149
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629224657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.629224657
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1106140222
Short name T813
Test name
Test status
Simulation time 10007615515 ps
CPU time 4.65 seconds
Started May 26 02:29:44 PM PDT 24
Finished May 26 02:29:50 PM PDT 24
Peak memory 201980 kb
Host smart-a57e7f3c-36e7-4031-99a4-ff9af37fe572
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106140222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1106140222
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3261708122
Short name T119
Test name
Test status
Simulation time 789570073 ps
CPU time 1.28 seconds
Started May 26 02:29:44 PM PDT 24
Finished May 26 02:29:46 PM PDT 24
Peak memory 201752 kb
Host smart-89c845cd-f2b9-474f-b4ca-ea982e9627ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261708122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3261708122
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3269613356
Short name T904
Test name
Test status
Simulation time 485035038 ps
CPU time 1.25 seconds
Started May 26 02:29:44 PM PDT 24
Finished May 26 02:29:46 PM PDT 24
Peak memory 201800 kb
Host smart-2120e0a2-8ad1-4947-a7bd-9385047bf17d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269613356 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3269613356
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.198638608
Short name T874
Test name
Test status
Simulation time 491456079 ps
CPU time 0.8 seconds
Started May 26 02:29:53 PM PDT 24
Finished May 26 02:29:55 PM PDT 24
Peak memory 201708 kb
Host smart-9f21fa91-839d-4019-9af2-c442fec3ff99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198638608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.198638608
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.716463855
Short name T801
Test name
Test status
Simulation time 442584564 ps
CPU time 1.72 seconds
Started May 26 02:29:44 PM PDT 24
Finished May 26 02:29:47 PM PDT 24
Peak memory 201720 kb
Host smart-81ca697d-6472-4fd3-8ca1-90adaaa79d95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716463855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.716463855
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3156917896
Short name T831
Test name
Test status
Simulation time 1815834243 ps
CPU time 1.26 seconds
Started May 26 02:29:45 PM PDT 24
Finished May 26 02:29:47 PM PDT 24
Peak memory 201728 kb
Host smart-2206fe33-2816-4814-b15d-1e979c3d44c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156917896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3156917896
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.24874330
Short name T879
Test name
Test status
Simulation time 581006490 ps
CPU time 2.09 seconds
Started May 26 02:29:53 PM PDT 24
Finished May 26 02:29:57 PM PDT 24
Peak memory 201972 kb
Host smart-eb91459f-1090-4652-a83f-c08c36f05c15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24874330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.24874330
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3186944304
Short name T887
Test name
Test status
Simulation time 4350395076 ps
CPU time 12.18 seconds
Started May 26 02:29:53 PM PDT 24
Finished May 26 02:30:06 PM PDT 24
Peak memory 202040 kb
Host smart-dd579dc6-054c-401c-a6bd-82e1488274ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186944304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3186944304
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3347217231
Short name T850
Test name
Test status
Simulation time 524651226 ps
CPU time 1.86 seconds
Started May 26 02:30:25 PM PDT 24
Finished May 26 02:30:28 PM PDT 24
Peak memory 201744 kb
Host smart-65ba3e6f-1f83-42e5-ba12-8ab18e8b07ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347217231 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3347217231
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.17085456
Short name T124
Test name
Test status
Simulation time 416901114 ps
CPU time 0.97 seconds
Started May 26 02:30:25 PM PDT 24
Finished May 26 02:30:27 PM PDT 24
Peak memory 201728 kb
Host smart-1673083b-babe-4210-ad0e-ed3d7649b98b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17085456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.17085456
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.651154019
Short name T896
Test name
Test status
Simulation time 424982696 ps
CPU time 1.67 seconds
Started May 26 02:30:25 PM PDT 24
Finished May 26 02:30:28 PM PDT 24
Peak memory 201704 kb
Host smart-f76914d9-34d5-4b2e-86fc-f87133082bc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651154019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.651154019
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2402694629
Short name T57
Test name
Test status
Simulation time 5240202926 ps
CPU time 5.83 seconds
Started May 26 02:30:26 PM PDT 24
Finished May 26 02:30:32 PM PDT 24
Peak memory 202064 kb
Host smart-bc68aa3f-1b9a-4ea5-93b5-9cdddb514ee7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402694629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2402694629
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4017592216
Short name T909
Test name
Test status
Simulation time 408353462 ps
CPU time 1.81 seconds
Started May 26 02:30:25 PM PDT 24
Finished May 26 02:30:27 PM PDT 24
Peak memory 202012 kb
Host smart-2f80c26f-2699-4bbd-81c7-7115e4c2b104
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017592216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.4017592216
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2841043146
Short name T839
Test name
Test status
Simulation time 4672848962 ps
CPU time 5.71 seconds
Started May 26 02:30:25 PM PDT 24
Finished May 26 02:30:32 PM PDT 24
Peak memory 201980 kb
Host smart-c74d4bb4-a7b3-45ab-ba49-520dcb53fd33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841043146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.2841043146
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.778596423
Short name T895
Test name
Test status
Simulation time 421089578 ps
CPU time 2.07 seconds
Started May 26 02:30:26 PM PDT 24
Finished May 26 02:30:29 PM PDT 24
Peak memory 201780 kb
Host smart-d6834674-3d57-4028-a152-286312e531f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778596423 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.778596423
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1654274104
Short name T902
Test name
Test status
Simulation time 515187341 ps
CPU time 0.85 seconds
Started May 26 02:30:26 PM PDT 24
Finished May 26 02:30:27 PM PDT 24
Peak memory 201752 kb
Host smart-00aa96ba-434a-42d1-88b8-ecc44197a0b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654274104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1654274104
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.4120581391
Short name T917
Test name
Test status
Simulation time 442294416 ps
CPU time 0.72 seconds
Started May 26 02:30:26 PM PDT 24
Finished May 26 02:30:28 PM PDT 24
Peak memory 201748 kb
Host smart-533cd159-f82b-4448-836e-fef6b8480424
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120581391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.4120581391
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3304305619
Short name T911
Test name
Test status
Simulation time 4777585057 ps
CPU time 16.44 seconds
Started May 26 02:30:28 PM PDT 24
Finished May 26 02:30:45 PM PDT 24
Peak memory 201980 kb
Host smart-b6b6c9e9-ba85-497d-ba2b-a075db344779
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304305619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3304305619
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.51823579
Short name T819
Test name
Test status
Simulation time 444834376 ps
CPU time 1.86 seconds
Started May 26 02:30:25 PM PDT 24
Finished May 26 02:30:28 PM PDT 24
Peak memory 201964 kb
Host smart-ec29e4fd-21c6-4234-9d04-c135b806fac3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51823579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.51823579
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3039304447
Short name T341
Test name
Test status
Simulation time 4424146458 ps
CPU time 3.17 seconds
Started May 26 02:30:25 PM PDT 24
Finished May 26 02:30:29 PM PDT 24
Peak memory 202016 kb
Host smart-be7141e2-9ad1-4256-8fcc-c6f11582fd17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039304447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3039304447
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2189484335
Short name T824
Test name
Test status
Simulation time 591951791 ps
CPU time 1 seconds
Started May 26 02:30:32 PM PDT 24
Finished May 26 02:30:33 PM PDT 24
Peak memory 201788 kb
Host smart-a6f6c8d4-1e97-48c5-86e2-6b0a452b0a5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189484335 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2189484335
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2373149335
Short name T126
Test name
Test status
Simulation time 372220630 ps
CPU time 1.73 seconds
Started May 26 02:30:24 PM PDT 24
Finished May 26 02:30:27 PM PDT 24
Peak memory 201708 kb
Host smart-419648c5-a2ef-4d23-b5f8-ea8053652f1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373149335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2373149335
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1364758713
Short name T865
Test name
Test status
Simulation time 451117963 ps
CPU time 0.76 seconds
Started May 26 02:30:26 PM PDT 24
Finished May 26 02:30:27 PM PDT 24
Peak memory 201692 kb
Host smart-7b904763-7569-4d73-ab8f-73e214be24c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364758713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1364758713
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.387414421
Short name T811
Test name
Test status
Simulation time 5030822656 ps
CPU time 19.03 seconds
Started May 26 02:30:28 PM PDT 24
Finished May 26 02:30:48 PM PDT 24
Peak memory 201952 kb
Host smart-58224675-9847-4ed0-a60a-08a81615294c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387414421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.387414421
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.908504175
Short name T913
Test name
Test status
Simulation time 8372368495 ps
CPU time 21.82 seconds
Started May 26 02:30:27 PM PDT 24
Finished May 26 02:30:50 PM PDT 24
Peak memory 202032 kb
Host smart-a3dbc770-88dc-44ed-8e6f-b52a8100e01b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908504175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.908504175
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1218399383
Short name T908
Test name
Test status
Simulation time 597412212 ps
CPU time 2.22 seconds
Started May 26 02:30:34 PM PDT 24
Finished May 26 02:30:37 PM PDT 24
Peak memory 201680 kb
Host smart-85d107b3-a961-4c91-8d43-c76e3e616bdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218399383 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1218399383
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1158764558
Short name T123
Test name
Test status
Simulation time 558838409 ps
CPU time 0.98 seconds
Started May 26 02:30:35 PM PDT 24
Finished May 26 02:30:36 PM PDT 24
Peak memory 201732 kb
Host smart-4d027d68-80da-4016-9689-752564064866
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158764558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1158764558
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3598973660
Short name T857
Test name
Test status
Simulation time 298005118 ps
CPU time 1.28 seconds
Started May 26 02:30:35 PM PDT 24
Finished May 26 02:30:37 PM PDT 24
Peak memory 201732 kb
Host smart-6342fadd-e60c-4650-9100-ed992c5af16a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598973660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3598973660
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.140261824
Short name T825
Test name
Test status
Simulation time 4978999026 ps
CPU time 8.66 seconds
Started May 26 02:30:33 PM PDT 24
Finished May 26 02:30:43 PM PDT 24
Peak memory 202008 kb
Host smart-65ce5462-2116-4a68-b2bb-b3e4edb7e3b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140261824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.140261824
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3922286099
Short name T63
Test name
Test status
Simulation time 518498050 ps
CPU time 1.81 seconds
Started May 26 02:30:34 PM PDT 24
Finished May 26 02:30:36 PM PDT 24
Peak memory 202020 kb
Host smart-c6865b44-67c5-4e91-a593-2f289d7ff743
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922286099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3922286099
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3370509576
Short name T88
Test name
Test status
Simulation time 582765448 ps
CPU time 2.41 seconds
Started May 26 02:30:33 PM PDT 24
Finished May 26 02:30:37 PM PDT 24
Peak memory 201788 kb
Host smart-0d2c1fd7-4fe1-4a2d-b67a-76ba0a6909ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370509576 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3370509576
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.536372286
Short name T878
Test name
Test status
Simulation time 649051210 ps
CPU time 1.05 seconds
Started May 26 02:30:33 PM PDT 24
Finished May 26 02:30:35 PM PDT 24
Peak memory 201752 kb
Host smart-4d41d848-d803-4601-8fc4-63f527684a2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536372286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.536372286
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.25228467
Short name T832
Test name
Test status
Simulation time 360712977 ps
CPU time 0.85 seconds
Started May 26 02:30:32 PM PDT 24
Finished May 26 02:30:33 PM PDT 24
Peak memory 201708 kb
Host smart-f9b4b730-0655-45a8-9130-afa47df11f4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25228467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.25228467
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1879521807
Short name T846
Test name
Test status
Simulation time 5297923230 ps
CPU time 6.54 seconds
Started May 26 02:30:35 PM PDT 24
Finished May 26 02:30:42 PM PDT 24
Peak memory 202032 kb
Host smart-7c6f2cac-4b67-4b0e-ad5b-14a4ca61ad51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879521807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1879521807
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1802927336
Short name T910
Test name
Test status
Simulation time 459202750 ps
CPU time 1.58 seconds
Started May 26 02:30:33 PM PDT 24
Finished May 26 02:30:35 PM PDT 24
Peak memory 201780 kb
Host smart-f66da325-7a74-457c-9990-e1a560d15066
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802927336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1802927336
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4213644937
Short name T337
Test name
Test status
Simulation time 4595897130 ps
CPU time 4.42 seconds
Started May 26 02:30:32 PM PDT 24
Finished May 26 02:30:37 PM PDT 24
Peak memory 201972 kb
Host smart-cc775018-1045-4ec9-a62b-dff57216ec63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213644937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.4213644937
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2796868214
Short name T894
Test name
Test status
Simulation time 589025304 ps
CPU time 1.49 seconds
Started May 26 02:30:35 PM PDT 24
Finished May 26 02:30:38 PM PDT 24
Peak memory 201760 kb
Host smart-93f73fe4-9ff6-4e85-8b82-8c1426c026c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796868214 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2796868214
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2999546582
Short name T125
Test name
Test status
Simulation time 531425234 ps
CPU time 2.17 seconds
Started May 26 02:30:44 PM PDT 24
Finished May 26 02:30:48 PM PDT 24
Peak memory 201756 kb
Host smart-b15f33cb-b2f3-416f-b346-bad6a626e786
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999546582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2999546582
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3500639904
Short name T805
Test name
Test status
Simulation time 488570932 ps
CPU time 1.96 seconds
Started May 26 02:30:33 PM PDT 24
Finished May 26 02:30:36 PM PDT 24
Peak memory 201652 kb
Host smart-159ce978-2a5f-435c-a686-9ba1601151b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500639904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3500639904
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3811160047
Short name T131
Test name
Test status
Simulation time 2047086607 ps
CPU time 1.67 seconds
Started May 26 02:30:32 PM PDT 24
Finished May 26 02:30:34 PM PDT 24
Peak memory 201748 kb
Host smart-c8f812e6-18d6-4334-9426-5b23dfcd65d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811160047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3811160047
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4048348358
Short name T866
Test name
Test status
Simulation time 776544964 ps
CPU time 3.32 seconds
Started May 26 02:30:32 PM PDT 24
Finished May 26 02:30:36 PM PDT 24
Peak memory 218316 kb
Host smart-5b7dbf75-e69f-47b0-ba0b-b30b426fb2f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048348358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.4048348358
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.836418782
Short name T867
Test name
Test status
Simulation time 686838689 ps
CPU time 1.53 seconds
Started May 26 02:30:33 PM PDT 24
Finished May 26 02:30:35 PM PDT 24
Peak memory 201772 kb
Host smart-ffeabeb5-ec9d-4bf6-825a-edcf2f7a191a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836418782 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.836418782
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.389920553
Short name T802
Test name
Test status
Simulation time 537185664 ps
CPU time 1.15 seconds
Started May 26 02:30:36 PM PDT 24
Finished May 26 02:30:38 PM PDT 24
Peak memory 201728 kb
Host smart-b3cae4f1-d721-42aa-9bdd-04b181bc379c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389920553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.389920553
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.835425246
Short name T806
Test name
Test status
Simulation time 488286348 ps
CPU time 1.21 seconds
Started May 26 02:30:33 PM PDT 24
Finished May 26 02:30:34 PM PDT 24
Peak memory 201712 kb
Host smart-df7920c7-b688-4209-a8c1-1920005af5a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835425246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.835425246
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.592200177
Short name T56
Test name
Test status
Simulation time 4419048414 ps
CPU time 18.53 seconds
Started May 26 02:30:36 PM PDT 24
Finished May 26 02:30:55 PM PDT 24
Peak memory 202024 kb
Host smart-b0b18870-76fe-44d1-9dd8-07c445c60648
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592200177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.592200177
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3441503644
Short name T915
Test name
Test status
Simulation time 492342035 ps
CPU time 3.23 seconds
Started May 26 02:30:34 PM PDT 24
Finished May 26 02:30:38 PM PDT 24
Peak memory 202124 kb
Host smart-e082639d-888b-4a03-968c-753d09f9c118
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441503644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3441503644
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3059741048
Short name T340
Test name
Test status
Simulation time 5601032123 ps
CPU time 2.78 seconds
Started May 26 02:30:34 PM PDT 24
Finished May 26 02:30:38 PM PDT 24
Peak memory 202036 kb
Host smart-a14ce81d-3a81-4a86-89b6-608c48aeb661
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059741048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3059741048
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3580879053
Short name T885
Test name
Test status
Simulation time 691793667 ps
CPU time 1.39 seconds
Started May 26 02:30:43 PM PDT 24
Finished May 26 02:30:46 PM PDT 24
Peak memory 201760 kb
Host smart-69508b1c-ef93-460d-94ec-a66c07b1ba22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580879053 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3580879053
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2963695493
Short name T829
Test name
Test status
Simulation time 576191272 ps
CPU time 2.3 seconds
Started May 26 02:30:43 PM PDT 24
Finished May 26 02:30:46 PM PDT 24
Peak memory 201704 kb
Host smart-afba2044-9c99-4a6e-8379-3caba1b00726
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963695493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2963695493
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.169104970
Short name T814
Test name
Test status
Simulation time 346996116 ps
CPU time 1.41 seconds
Started May 26 02:30:42 PM PDT 24
Finished May 26 02:30:44 PM PDT 24
Peak memory 201752 kb
Host smart-a28fc186-4af5-4da9-95ee-c9e2147377c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169104970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.169104970
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.39480560
Short name T905
Test name
Test status
Simulation time 4516977720 ps
CPU time 4.17 seconds
Started May 26 02:30:40 PM PDT 24
Finished May 26 02:30:45 PM PDT 24
Peak memory 202028 kb
Host smart-6f62c182-9463-4450-aab5-746b80565992
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39480560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ct
rl_same_csr_outstanding.39480560
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.832561974
Short name T876
Test name
Test status
Simulation time 394028647 ps
CPU time 1.31 seconds
Started May 26 02:30:42 PM PDT 24
Finished May 26 02:30:44 PM PDT 24
Peak memory 201976 kb
Host smart-d0976768-4842-4279-80cf-35772b8ae56b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832561974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.832561974
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1889537837
Short name T875
Test name
Test status
Simulation time 7942833288 ps
CPU time 21.11 seconds
Started May 26 02:30:42 PM PDT 24
Finished May 26 02:31:04 PM PDT 24
Peak memory 201976 kb
Host smart-5f2fb93b-9781-4544-993a-6a376dfcc4eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889537837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1889537837
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3247926854
Short name T838
Test name
Test status
Simulation time 775729313 ps
CPU time 1.2 seconds
Started May 26 02:30:41 PM PDT 24
Finished May 26 02:30:44 PM PDT 24
Peak memory 201800 kb
Host smart-5caef2e3-e705-4e22-a1c8-ef64cfca49b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247926854 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3247926854
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1776407494
Short name T837
Test name
Test status
Simulation time 440936807 ps
CPU time 1.75 seconds
Started May 26 02:30:43 PM PDT 24
Finished May 26 02:30:46 PM PDT 24
Peak memory 201880 kb
Host smart-bfcd76bf-8500-4d52-82b8-b33ec4bdaf04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776407494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1776407494
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3940736044
Short name T822
Test name
Test status
Simulation time 353262191 ps
CPU time 1.49 seconds
Started May 26 02:30:42 PM PDT 24
Finished May 26 02:30:45 PM PDT 24
Peak memory 201696 kb
Host smart-1d4a847a-aef5-4bcd-a200-c451ff6a8342
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940736044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3940736044
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3678822255
Short name T863
Test name
Test status
Simulation time 2545031179 ps
CPU time 3.64 seconds
Started May 26 02:30:41 PM PDT 24
Finished May 26 02:30:45 PM PDT 24
Peak memory 201984 kb
Host smart-933372b2-e118-4ed1-a553-b43f8c3e40c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678822255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3678822255
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1539128883
Short name T906
Test name
Test status
Simulation time 688988115 ps
CPU time 3.47 seconds
Started May 26 02:30:41 PM PDT 24
Finished May 26 02:30:46 PM PDT 24
Peak memory 202052 kb
Host smart-6fecd761-5d7e-49d5-b8d1-883e527c7d4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539128883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1539128883
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1487760310
Short name T59
Test name
Test status
Simulation time 4330819165 ps
CPU time 12.03 seconds
Started May 26 02:30:41 PM PDT 24
Finished May 26 02:30:54 PM PDT 24
Peak memory 202020 kb
Host smart-6d4d3714-5da5-4ad2-ae15-371289937572
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487760310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1487760310
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2419361938
Short name T809
Test name
Test status
Simulation time 409835660 ps
CPU time 1.36 seconds
Started May 26 02:30:42 PM PDT 24
Finished May 26 02:30:45 PM PDT 24
Peak memory 201780 kb
Host smart-9e2f3455-7cb0-4ef5-9268-b8c8cefdf263
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419361938 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2419361938
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1964522835
Short name T883
Test name
Test status
Simulation time 561039119 ps
CPU time 1.08 seconds
Started May 26 02:30:40 PM PDT 24
Finished May 26 02:30:42 PM PDT 24
Peak memory 201740 kb
Host smart-382859b8-34bc-4f88-876c-c48d0673b61c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964522835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1964522835
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1180111504
Short name T873
Test name
Test status
Simulation time 510108697 ps
CPU time 0.75 seconds
Started May 26 02:30:41 PM PDT 24
Finished May 26 02:30:43 PM PDT 24
Peak memory 201704 kb
Host smart-f8caa37f-50fc-4c8e-a6d9-bd5ae5cb0e23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180111504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1180111504
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2918550464
Short name T810
Test name
Test status
Simulation time 4478341394 ps
CPU time 3.31 seconds
Started May 26 02:30:41 PM PDT 24
Finished May 26 02:30:45 PM PDT 24
Peak memory 201988 kb
Host smart-f59792ff-30d4-44c5-a246-5012ae07f20a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918550464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2918550464
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3994211540
Short name T858
Test name
Test status
Simulation time 513160536 ps
CPU time 2.95 seconds
Started May 26 02:30:42 PM PDT 24
Finished May 26 02:30:47 PM PDT 24
Peak memory 201992 kb
Host smart-ff9e17bb-f1d2-47e5-8e99-7e1de90a4d91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994211540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3994211540
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2532127479
Short name T76
Test name
Test status
Simulation time 4338705356 ps
CPU time 6.25 seconds
Started May 26 02:30:43 PM PDT 24
Finished May 26 02:30:50 PM PDT 24
Peak memory 201844 kb
Host smart-b504bca7-4bd5-4414-8e63-0b0fe50b015f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532127479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2532127479
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2829245911
Short name T818
Test name
Test status
Simulation time 915700469 ps
CPU time 2.59 seconds
Started May 26 02:29:53 PM PDT 24
Finished May 26 02:29:57 PM PDT 24
Peak memory 201964 kb
Host smart-168788f5-d6e7-4d49-a576-b45d594c1200
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829245911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2829245911
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2237949554
Short name T118
Test name
Test status
Simulation time 1164648202 ps
CPU time 5.87 seconds
Started May 26 02:29:53 PM PDT 24
Finished May 26 02:30:00 PM PDT 24
Peak memory 201884 kb
Host smart-b9304e7f-4a48-4b2c-bc9c-5aa8af2568d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237949554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2237949554
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.623493718
Short name T900
Test name
Test status
Simulation time 1169478027 ps
CPU time 1.4 seconds
Started May 26 02:29:53 PM PDT 24
Finished May 26 02:29:56 PM PDT 24
Peak memory 201748 kb
Host smart-148a1da6-b4b5-4c8d-ad14-50a7e2d2befc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623493718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.623493718
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.471062831
Short name T62
Test name
Test status
Simulation time 500777752 ps
CPU time 1.31 seconds
Started May 26 02:29:53 PM PDT 24
Finished May 26 02:29:56 PM PDT 24
Peak memory 211704 kb
Host smart-563e95c7-3f83-4f74-b826-f6cdf6f27ba9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471062831 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.471062831
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1401701963
Short name T899
Test name
Test status
Simulation time 467482152 ps
CPU time 1.99 seconds
Started May 26 02:29:53 PM PDT 24
Finished May 26 02:29:57 PM PDT 24
Peak memory 201744 kb
Host smart-39442cbf-8ceb-41a7-bf47-85c00f04d4ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401701963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1401701963
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.161064901
Short name T877
Test name
Test status
Simulation time 476590320 ps
CPU time 1.64 seconds
Started May 26 02:29:55 PM PDT 24
Finished May 26 02:29:58 PM PDT 24
Peak memory 201716 kb
Host smart-8a304fe6-1e76-4d66-8080-6e0cd5106e64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161064901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.161064901
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2777046658
Short name T128
Test name
Test status
Simulation time 2428301337 ps
CPU time 3.04 seconds
Started May 26 02:29:52 PM PDT 24
Finished May 26 02:29:56 PM PDT 24
Peak memory 201940 kb
Host smart-1593b2bd-7a75-42fb-9b59-efaa7675bdb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777046658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2777046658
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1982332264
Short name T821
Test name
Test status
Simulation time 532550212 ps
CPU time 2.16 seconds
Started May 26 02:29:44 PM PDT 24
Finished May 26 02:29:47 PM PDT 24
Peak memory 201976 kb
Host smart-ef77b29e-b96c-4ec6-9f50-bd37a61d1adf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982332264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1982332264
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3199197815
Short name T854
Test name
Test status
Simulation time 8314940954 ps
CPU time 15.43 seconds
Started May 26 02:29:53 PM PDT 24
Finished May 26 02:30:10 PM PDT 24
Peak memory 201944 kb
Host smart-89eff062-52e5-4084-a857-cf5691aa596b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199197815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3199197815
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1119788167
Short name T803
Test name
Test status
Simulation time 289954149 ps
CPU time 1.35 seconds
Started May 26 02:30:41 PM PDT 24
Finished May 26 02:30:43 PM PDT 24
Peak memory 201736 kb
Host smart-7b2ae2ac-2a73-46ed-81af-cfa5fd145b6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119788167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1119788167
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1171778960
Short name T847
Test name
Test status
Simulation time 310150574 ps
CPU time 1.33 seconds
Started May 26 02:30:43 PM PDT 24
Finished May 26 02:30:46 PM PDT 24
Peak memory 201624 kb
Host smart-70b09ad7-ebcf-49c7-8f31-4c148ddf3d0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171778960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1171778960
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1613581580
Short name T916
Test name
Test status
Simulation time 508432704 ps
CPU time 1.27 seconds
Started May 26 02:30:43 PM PDT 24
Finished May 26 02:30:46 PM PDT 24
Peak memory 201868 kb
Host smart-7137f721-99a5-4c95-919f-f9f46ec699ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613581580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1613581580
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3178637377
Short name T892
Test name
Test status
Simulation time 324347246 ps
CPU time 1.32 seconds
Started May 26 02:30:42 PM PDT 24
Finished May 26 02:30:45 PM PDT 24
Peak memory 201744 kb
Host smart-47b4a42c-463e-41c9-a3d1-9caf3abc5de2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178637377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3178637377
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2855210733
Short name T886
Test name
Test status
Simulation time 374292580 ps
CPU time 1.03 seconds
Started May 26 02:30:43 PM PDT 24
Finished May 26 02:30:46 PM PDT 24
Peak memory 201636 kb
Host smart-67b4324e-e239-472c-b3ba-8fdd13fe0d27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855210733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2855210733
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1365962888
Short name T891
Test name
Test status
Simulation time 486673717 ps
CPU time 0.71 seconds
Started May 26 02:30:43 PM PDT 24
Finished May 26 02:30:45 PM PDT 24
Peak memory 201576 kb
Host smart-18a39ab0-d473-4e3b-93fe-d483b6f79ae8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365962888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1365962888
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1700641654
Short name T800
Test name
Test status
Simulation time 439096556 ps
CPU time 1.08 seconds
Started May 26 02:30:49 PM PDT 24
Finished May 26 02:30:51 PM PDT 24
Peak memory 201704 kb
Host smart-a55908d2-fb0b-4ffb-8329-58841c0df8fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700641654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1700641654
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2126457139
Short name T864
Test name
Test status
Simulation time 436473468 ps
CPU time 0.85 seconds
Started May 26 02:30:50 PM PDT 24
Finished May 26 02:30:52 PM PDT 24
Peak memory 201732 kb
Host smart-c48ef3e1-727c-45cd-82bc-7d4618abc3c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126457139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2126457139
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3234405847
Short name T872
Test name
Test status
Simulation time 282350081 ps
CPU time 1.21 seconds
Started May 26 02:30:50 PM PDT 24
Finished May 26 02:30:53 PM PDT 24
Peak memory 201712 kb
Host smart-3a66fad3-00fd-4631-a5fb-5a41ec742e13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234405847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3234405847
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3665471745
Short name T799
Test name
Test status
Simulation time 304276687 ps
CPU time 0.96 seconds
Started May 26 02:30:48 PM PDT 24
Finished May 26 02:30:49 PM PDT 24
Peak memory 201708 kb
Host smart-673b4164-e8da-4b02-b7e8-4692ee8b947d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665471745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3665471745
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.752630875
Short name T112
Test name
Test status
Simulation time 1095114337 ps
CPU time 2.97 seconds
Started May 26 02:30:02 PM PDT 24
Finished May 26 02:30:05 PM PDT 24
Peak memory 201952 kb
Host smart-59c02884-b63b-4195-92dd-9a563d7edca1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752630875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alias
ing.752630875
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2554924606
Short name T116
Test name
Test status
Simulation time 21123429514 ps
CPU time 16.86 seconds
Started May 26 02:30:03 PM PDT 24
Finished May 26 02:30:21 PM PDT 24
Peak memory 201944 kb
Host smart-b99304a6-b435-4aeb-b721-f7c7ecc22ffb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554924606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2554924606
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3354942883
Short name T120
Test name
Test status
Simulation time 1112602085 ps
CPU time 3.45 seconds
Started May 26 02:30:00 PM PDT 24
Finished May 26 02:30:04 PM PDT 24
Peak memory 201756 kb
Host smart-ab7b55ad-d4a4-4c0c-8248-d2ec8fdf3afc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354942883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3354942883
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.44732070
Short name T841
Test name
Test status
Simulation time 601022922 ps
CPU time 1.14 seconds
Started May 26 02:30:02 PM PDT 24
Finished May 26 02:30:04 PM PDT 24
Peak memory 201736 kb
Host smart-f2c241a1-e758-49e6-96e1-9e2eaa9ad1b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44732070 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.44732070
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1668882793
Short name T901
Test name
Test status
Simulation time 510930153 ps
CPU time 0.99 seconds
Started May 26 02:30:03 PM PDT 24
Finished May 26 02:30:04 PM PDT 24
Peak memory 201740 kb
Host smart-b0acd8ce-8f2f-418a-9ce5-86bd530b7d1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668882793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1668882793
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2872177774
Short name T890
Test name
Test status
Simulation time 532918239 ps
CPU time 0.93 seconds
Started May 26 02:30:01 PM PDT 24
Finished May 26 02:30:03 PM PDT 24
Peak memory 201744 kb
Host smart-e21e1f47-c813-4b98-83a7-7f55c8df5c5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872177774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2872177774
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2633098058
Short name T130
Test name
Test status
Simulation time 2747950842 ps
CPU time 6.64 seconds
Started May 26 02:30:01 PM PDT 24
Finished May 26 02:30:09 PM PDT 24
Peak memory 201792 kb
Host smart-3cadfe4c-8a3b-477b-8a61-324b7c872a57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633098058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2633098058
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3708666536
Short name T74
Test name
Test status
Simulation time 427332587 ps
CPU time 2.14 seconds
Started May 26 02:30:01 PM PDT 24
Finished May 26 02:30:04 PM PDT 24
Peak memory 202052 kb
Host smart-00e13496-5b50-449e-9cb2-d003627da4bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708666536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3708666536
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1554968836
Short name T73
Test name
Test status
Simulation time 4148026685 ps
CPU time 4.2 seconds
Started May 26 02:30:01 PM PDT 24
Finished May 26 02:30:06 PM PDT 24
Peak memory 202004 kb
Host smart-c358fcd8-09a7-485f-84ef-4d6b7f3bbf88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554968836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1554968836
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3553368518
Short name T856
Test name
Test status
Simulation time 475132622 ps
CPU time 1.2 seconds
Started May 26 02:30:48 PM PDT 24
Finished May 26 02:30:49 PM PDT 24
Peak memory 201736 kb
Host smart-15537378-fe67-419f-b196-be7a4681da59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553368518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3553368518
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1366819270
Short name T833
Test name
Test status
Simulation time 441829550 ps
CPU time 0.89 seconds
Started May 26 02:30:48 PM PDT 24
Finished May 26 02:30:49 PM PDT 24
Peak memory 201740 kb
Host smart-83f81e94-36b3-4e9d-a8d1-24bbbf84c288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366819270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1366819270
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.4170554131
Short name T880
Test name
Test status
Simulation time 350973206 ps
CPU time 0.89 seconds
Started May 26 02:30:50 PM PDT 24
Finished May 26 02:30:52 PM PDT 24
Peak memory 201692 kb
Host smart-42b6b50f-5721-4e8b-a109-7607d03dfb60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170554131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.4170554131
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.141388446
Short name T836
Test name
Test status
Simulation time 458025837 ps
CPU time 0.93 seconds
Started May 26 02:30:49 PM PDT 24
Finished May 26 02:30:50 PM PDT 24
Peak memory 201732 kb
Host smart-8d246b5f-f17d-4e57-ad98-54116263a0b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141388446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.141388446
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.133939271
Short name T830
Test name
Test status
Simulation time 414785675 ps
CPU time 1.6 seconds
Started May 26 02:30:49 PM PDT 24
Finished May 26 02:30:51 PM PDT 24
Peak memory 201756 kb
Host smart-712be7b8-0565-44d0-85b4-1f962c73cab4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133939271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.133939271
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3481055749
Short name T889
Test name
Test status
Simulation time 511191347 ps
CPU time 0.87 seconds
Started May 26 02:30:49 PM PDT 24
Finished May 26 02:30:51 PM PDT 24
Peak memory 201728 kb
Host smart-2c36e9c9-d7e2-4950-b300-b91ad076fee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481055749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3481055749
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1658048254
Short name T918
Test name
Test status
Simulation time 512556984 ps
CPU time 1.85 seconds
Started May 26 02:30:51 PM PDT 24
Finished May 26 02:30:53 PM PDT 24
Peak memory 201740 kb
Host smart-f7ba8169-7616-4a56-89d7-e9cb74d12313
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658048254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1658048254
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4271732328
Short name T870
Test name
Test status
Simulation time 483590210 ps
CPU time 1.15 seconds
Started May 26 02:30:48 PM PDT 24
Finished May 26 02:30:49 PM PDT 24
Peak memory 201736 kb
Host smart-4579ae49-a119-4604-8099-77b36f6db463
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271732328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.4271732328
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2182548033
Short name T881
Test name
Test status
Simulation time 421333072 ps
CPU time 1.56 seconds
Started May 26 02:30:48 PM PDT 24
Finished May 26 02:30:50 PM PDT 24
Peak memory 201748 kb
Host smart-4da3bf3c-02c6-4641-a33c-28d82f4824f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182548033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2182548033
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3020859622
Short name T844
Test name
Test status
Simulation time 454378043 ps
CPU time 1.71 seconds
Started May 26 02:30:50 PM PDT 24
Finished May 26 02:30:53 PM PDT 24
Peak memory 201628 kb
Host smart-3e5087f5-12d0-4c5c-bf53-f12a704a2d8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020859622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3020859622
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3509112628
Short name T808
Test name
Test status
Simulation time 1349129441 ps
CPU time 3.05 seconds
Started May 26 02:30:09 PM PDT 24
Finished May 26 02:30:12 PM PDT 24
Peak memory 201928 kb
Host smart-de16cf78-af5c-4679-8f73-f24073e35d57
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509112628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3509112628
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1097620548
Short name T122
Test name
Test status
Simulation time 7690820981 ps
CPU time 32.41 seconds
Started May 26 02:30:09 PM PDT 24
Finished May 26 02:30:42 PM PDT 24
Peak memory 202012 kb
Host smart-35ab255c-3ef2-452a-8fe4-87d52b720b1b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097620548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1097620548
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2418619253
Short name T115
Test name
Test status
Simulation time 1094553441 ps
CPU time 3.41 seconds
Started May 26 02:30:12 PM PDT 24
Finished May 26 02:30:16 PM PDT 24
Peak memory 201736 kb
Host smart-b80a7ff8-7839-44f6-a5bd-3ccdf9f30cb7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418619253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2418619253
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.814874710
Short name T827
Test name
Test status
Simulation time 427905005 ps
CPU time 1.11 seconds
Started May 26 02:30:10 PM PDT 24
Finished May 26 02:30:12 PM PDT 24
Peak memory 201804 kb
Host smart-9b5bdf74-f6a4-4597-aa40-157c0e6f3761
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814874710 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.814874710
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.4197474968
Short name T117
Test name
Test status
Simulation time 526131941 ps
CPU time 1.45 seconds
Started May 26 02:30:09 PM PDT 24
Finished May 26 02:30:12 PM PDT 24
Peak memory 201760 kb
Host smart-e31b8d36-f887-4981-a074-1b567df7cfdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197474968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.4197474968
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1503690302
Short name T842
Test name
Test status
Simulation time 303927089 ps
CPU time 1.38 seconds
Started May 26 02:30:11 PM PDT 24
Finished May 26 02:30:13 PM PDT 24
Peak memory 201744 kb
Host smart-69d2edb4-93ce-4fd9-88de-eee8b414a5c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503690302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1503690302
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.524862346
Short name T58
Test name
Test status
Simulation time 2807657430 ps
CPU time 10.07 seconds
Started May 26 02:30:11 PM PDT 24
Finished May 26 02:30:22 PM PDT 24
Peak memory 201976 kb
Host smart-77544a35-e489-4dfd-9cb8-38c2ad65c4fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524862346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.524862346
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2896412019
Short name T816
Test name
Test status
Simulation time 429103967 ps
CPU time 2.42 seconds
Started May 26 02:30:02 PM PDT 24
Finished May 26 02:30:05 PM PDT 24
Peak memory 201912 kb
Host smart-2022848f-f2d7-458a-9caa-d0d0e9c495a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896412019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2896412019
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2451162256
Short name T65
Test name
Test status
Simulation time 8335421970 ps
CPU time 22.22 seconds
Started May 26 02:30:12 PM PDT 24
Finished May 26 02:30:35 PM PDT 24
Peak memory 202056 kb
Host smart-b39d5990-af48-4e36-8406-4763a45a1d7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451162256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2451162256
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3177957713
Short name T912
Test name
Test status
Simulation time 371768877 ps
CPU time 1.48 seconds
Started May 26 02:30:49 PM PDT 24
Finished May 26 02:30:52 PM PDT 24
Peak memory 201736 kb
Host smart-4a102a79-1f2a-4825-b4e2-8d131ee49388
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177957713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3177957713
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3081423748
Short name T828
Test name
Test status
Simulation time 423113609 ps
CPU time 1.53 seconds
Started May 26 02:30:49 PM PDT 24
Finished May 26 02:30:52 PM PDT 24
Peak memory 201736 kb
Host smart-37b61ea9-e024-4cb3-9e20-59cc88da442e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081423748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3081423748
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3757057514
Short name T898
Test name
Test status
Simulation time 343614340 ps
CPU time 1.36 seconds
Started May 26 02:30:50 PM PDT 24
Finished May 26 02:30:53 PM PDT 24
Peak memory 201728 kb
Host smart-86c279df-1b6e-4a82-9d85-54e80354ea63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757057514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3757057514
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3607063499
Short name T914
Test name
Test status
Simulation time 542227087 ps
CPU time 0.98 seconds
Started May 26 02:30:49 PM PDT 24
Finished May 26 02:30:52 PM PDT 24
Peak memory 201728 kb
Host smart-3c13945d-7254-45dc-b5ab-5268c753e82c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607063499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3607063499
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1217440368
Short name T884
Test name
Test status
Simulation time 496867791 ps
CPU time 1.88 seconds
Started May 26 02:30:49 PM PDT 24
Finished May 26 02:30:51 PM PDT 24
Peak memory 201724 kb
Host smart-a719b3cd-1ec9-429b-9551-d46e2f9646dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217440368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1217440368
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2162080483
Short name T871
Test name
Test status
Simulation time 429894428 ps
CPU time 0.89 seconds
Started May 26 02:30:49 PM PDT 24
Finished May 26 02:30:52 PM PDT 24
Peak memory 201688 kb
Host smart-923384e6-c7d1-41c1-8c2e-be829d8df113
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162080483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2162080483
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3799390825
Short name T812
Test name
Test status
Simulation time 443992334 ps
CPU time 0.93 seconds
Started May 26 02:30:50 PM PDT 24
Finished May 26 02:30:52 PM PDT 24
Peak memory 201732 kb
Host smart-c380ca7f-3894-45d9-9b9d-2b8c13779d21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799390825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3799390825
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.4103633112
Short name T815
Test name
Test status
Simulation time 327773948 ps
CPU time 0.84 seconds
Started May 26 02:30:49 PM PDT 24
Finished May 26 02:30:51 PM PDT 24
Peak memory 201724 kb
Host smart-43a12267-d361-4e0d-8f0b-96262acfb935
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103633112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.4103633112
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2860147594
Short name T826
Test name
Test status
Simulation time 431394443 ps
CPU time 1.53 seconds
Started May 26 02:30:49 PM PDT 24
Finished May 26 02:30:52 PM PDT 24
Peak memory 201704 kb
Host smart-1e55a868-85e5-43ef-a011-62d3e3641190
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860147594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2860147594
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3768197279
Short name T868
Test name
Test status
Simulation time 315817298 ps
CPU time 1.31 seconds
Started May 26 02:30:49 PM PDT 24
Finished May 26 02:30:52 PM PDT 24
Peak memory 201716 kb
Host smart-04650385-9b7c-4f41-abad-780ac0af00e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768197279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3768197279
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3382973833
Short name T862
Test name
Test status
Simulation time 480434233 ps
CPU time 1.91 seconds
Started May 26 02:30:10 PM PDT 24
Finished May 26 02:30:13 PM PDT 24
Peak memory 201788 kb
Host smart-374d8e24-14f9-426d-b9d1-bc1623279f0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382973833 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3382973833
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3578202248
Short name T127
Test name
Test status
Simulation time 481841450 ps
CPU time 1.8 seconds
Started May 26 02:30:10 PM PDT 24
Finished May 26 02:30:13 PM PDT 24
Peak memory 201744 kb
Host smart-fd3b1385-1b79-4e69-b65b-c89d5089790b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578202248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3578202248
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2841192431
Short name T823
Test name
Test status
Simulation time 594650625 ps
CPU time 0.83 seconds
Started May 26 02:30:11 PM PDT 24
Finished May 26 02:30:13 PM PDT 24
Peak memory 201744 kb
Host smart-bae41f31-35e5-4c28-9f7f-8fba062cd9eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841192431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2841192431
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1307137720
Short name T888
Test name
Test status
Simulation time 4324846091 ps
CPU time 3.74 seconds
Started May 26 02:30:09 PM PDT 24
Finished May 26 02:30:14 PM PDT 24
Peak memory 201948 kb
Host smart-c5c92f34-61ee-458b-a750-167c2b331f2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307137720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1307137720
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1786395207
Short name T849
Test name
Test status
Simulation time 451885607 ps
CPU time 1.67 seconds
Started May 26 02:30:12 PM PDT 24
Finished May 26 02:30:15 PM PDT 24
Peak memory 201804 kb
Host smart-8ac965a7-a6b1-4ecf-9f85-436d0a857184
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786395207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1786395207
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.171118579
Short name T75
Test name
Test status
Simulation time 8473413921 ps
CPU time 21.58 seconds
Started May 26 02:30:09 PM PDT 24
Finished May 26 02:30:31 PM PDT 24
Peak memory 201972 kb
Host smart-e1b2e883-5baf-45d0-9a6b-66bf97f9eb3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171118579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.171118579
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.607272725
Short name T835
Test name
Test status
Simulation time 548605028 ps
CPU time 2.25 seconds
Started May 26 02:30:10 PM PDT 24
Finished May 26 02:30:13 PM PDT 24
Peak memory 201752 kb
Host smart-a7fa60dc-5788-4c5e-b2d5-81455dc9018b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607272725 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.607272725
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.748877515
Short name T129
Test name
Test status
Simulation time 569305318 ps
CPU time 1.15 seconds
Started May 26 02:30:10 PM PDT 24
Finished May 26 02:30:12 PM PDT 24
Peak memory 201756 kb
Host smart-d6e57395-150f-4954-8d8f-74e7f7d296f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748877515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.748877515
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3096337627
Short name T882
Test name
Test status
Simulation time 393841518 ps
CPU time 0.85 seconds
Started May 26 02:30:09 PM PDT 24
Finished May 26 02:30:11 PM PDT 24
Peak memory 201724 kb
Host smart-f71482b5-86a1-4ae2-8c1b-61df29e34d71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096337627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3096337627
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2979215421
Short name T845
Test name
Test status
Simulation time 2073170447 ps
CPU time 2.09 seconds
Started May 26 02:30:11 PM PDT 24
Finished May 26 02:30:14 PM PDT 24
Peak memory 201748 kb
Host smart-5e94ca7d-56a7-48ab-959e-c7005feb44be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979215421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2979215421
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2313141654
Short name T852
Test name
Test status
Simulation time 476816908 ps
CPU time 1.61 seconds
Started May 26 02:30:09 PM PDT 24
Finished May 26 02:30:11 PM PDT 24
Peak memory 202024 kb
Host smart-277a4b52-c699-4e75-ba7a-da4df964a6e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313141654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2313141654
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1204411636
Short name T907
Test name
Test status
Simulation time 4484408131 ps
CPU time 5.16 seconds
Started May 26 02:30:10 PM PDT 24
Finished May 26 02:30:16 PM PDT 24
Peak memory 201980 kb
Host smart-59e7776a-e037-40b4-a138-cdf627e104c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204411636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1204411636
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.153455750
Short name T853
Test name
Test status
Simulation time 451871970 ps
CPU time 2.08 seconds
Started May 26 02:30:18 PM PDT 24
Finished May 26 02:30:20 PM PDT 24
Peak memory 201796 kb
Host smart-cfedcf34-0945-4c8e-a681-4d5a36936e8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153455750 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.153455750
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1862630044
Short name T859
Test name
Test status
Simulation time 454451853 ps
CPU time 0.97 seconds
Started May 26 02:30:17 PM PDT 24
Finished May 26 02:30:19 PM PDT 24
Peak memory 201880 kb
Host smart-8ec70995-8029-40a0-8214-321f6cae9429
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862630044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1862630044
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.389672713
Short name T840
Test name
Test status
Simulation time 537718405 ps
CPU time 1.27 seconds
Started May 26 02:30:21 PM PDT 24
Finished May 26 02:30:23 PM PDT 24
Peak memory 201764 kb
Host smart-c61c43ca-039b-4c4e-9ba5-9046d5dee65e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389672713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.389672713
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1298187530
Short name T848
Test name
Test status
Simulation time 2434363891 ps
CPU time 2.26 seconds
Started May 26 02:30:20 PM PDT 24
Finished May 26 02:30:23 PM PDT 24
Peak memory 201820 kb
Host smart-58221262-e35b-4ce5-914c-5022386651d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298187530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1298187530
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2703532304
Short name T70
Test name
Test status
Simulation time 2111899595 ps
CPU time 2.75 seconds
Started May 26 02:30:21 PM PDT 24
Finished May 26 02:30:24 PM PDT 24
Peak memory 211244 kb
Host smart-71a5d0a1-2f07-4dcc-b816-160b98d4c6ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703532304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2703532304
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1344680071
Short name T338
Test name
Test status
Simulation time 8007052042 ps
CPU time 20.46 seconds
Started May 26 02:30:17 PM PDT 24
Finished May 26 02:30:38 PM PDT 24
Peak memory 202028 kb
Host smart-0be13e91-0b44-482f-a806-ac871511f3fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344680071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1344680071
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3207968751
Short name T820
Test name
Test status
Simulation time 474426003 ps
CPU time 1.38 seconds
Started May 26 02:30:17 PM PDT 24
Finished May 26 02:30:19 PM PDT 24
Peak memory 201804 kb
Host smart-0dd35ca5-0f03-444f-bae7-70c5d0b04447
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207968751 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3207968751
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2419931353
Short name T132
Test name
Test status
Simulation time 353812894 ps
CPU time 1.54 seconds
Started May 26 02:30:17 PM PDT 24
Finished May 26 02:30:19 PM PDT 24
Peak memory 201732 kb
Host smart-c2cd2694-e962-4947-9b4e-b670a864b0a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419931353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2419931353
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4064361171
Short name T893
Test name
Test status
Simulation time 420491568 ps
CPU time 0.73 seconds
Started May 26 02:30:20 PM PDT 24
Finished May 26 02:30:22 PM PDT 24
Peak memory 201720 kb
Host smart-0c480cc0-49ca-45a9-88eb-470bf33f04dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064361171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.4064361171
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.532948089
Short name T903
Test name
Test status
Simulation time 2480774589 ps
CPU time 3.25 seconds
Started May 26 02:30:18 PM PDT 24
Finished May 26 02:30:22 PM PDT 24
Peak memory 201792 kb
Host smart-3199a451-9156-425a-859b-ae9a151471b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532948089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_same_csr_outstanding.532948089
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3810281970
Short name T69
Test name
Test status
Simulation time 757003281 ps
CPU time 2.86 seconds
Started May 26 02:30:19 PM PDT 24
Finished May 26 02:30:22 PM PDT 24
Peak memory 201992 kb
Host smart-0ffefcdb-c146-45ae-b405-4c30c0badce2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810281970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3810281970
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2881414675
Short name T807
Test name
Test status
Simulation time 535481920 ps
CPU time 1.17 seconds
Started May 26 02:30:19 PM PDT 24
Finished May 26 02:30:21 PM PDT 24
Peak memory 201788 kb
Host smart-32032025-3a52-4b27-9d32-4ab15a26b96b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881414675 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2881414675
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2781503489
Short name T855
Test name
Test status
Simulation time 296682471 ps
CPU time 1.42 seconds
Started May 26 02:30:17 PM PDT 24
Finished May 26 02:30:19 PM PDT 24
Peak memory 201760 kb
Host smart-082ba662-cc10-43ec-844b-5862a328be1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781503489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2781503489
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2338507404
Short name T843
Test name
Test status
Simulation time 456642006 ps
CPU time 0.71 seconds
Started May 26 02:30:20 PM PDT 24
Finished May 26 02:30:22 PM PDT 24
Peak memory 201736 kb
Host smart-509d37ce-6d15-45e3-9126-27ef8444d77e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338507404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2338507404
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.861766600
Short name T860
Test name
Test status
Simulation time 2552038496 ps
CPU time 3.2 seconds
Started May 26 02:30:18 PM PDT 24
Finished May 26 02:30:22 PM PDT 24
Peak memory 201792 kb
Host smart-8b22fea9-f74a-44a8-8c14-c7f726cef229
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861766600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.861766600
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1539137183
Short name T817
Test name
Test status
Simulation time 675174985 ps
CPU time 4.22 seconds
Started May 26 02:30:19 PM PDT 24
Finished May 26 02:30:24 PM PDT 24
Peak memory 218080 kb
Host smart-bde14b01-db07-4369-9e85-ad2bd97a9c9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539137183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1539137183
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2910570973
Short name T60
Test name
Test status
Simulation time 8603355231 ps
CPU time 22.71 seconds
Started May 26 02:30:18 PM PDT 24
Finished May 26 02:30:42 PM PDT 24
Peak memory 201992 kb
Host smart-19fe0a32-0819-4124-8ee9-14d4b5dcc3ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910570973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2910570973
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1596107203
Short name T529
Test name
Test status
Simulation time 330494085 ps
CPU time 1.43 seconds
Started May 26 02:31:27 PM PDT 24
Finished May 26 02:31:29 PM PDT 24
Peak memory 201400 kb
Host smart-dcac1235-db2d-4626-8099-b0bf13dd0f38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596107203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1596107203
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1270602222
Short name T712
Test name
Test status
Simulation time 165191532276 ps
CPU time 184.72 seconds
Started May 26 02:31:26 PM PDT 24
Finished May 26 02:34:32 PM PDT 24
Peak memory 201868 kb
Host smart-68162183-8465-4b7f-bd3d-964c4b30e6be
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270602222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1270602222
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2549784886
Short name T726
Test name
Test status
Simulation time 341010188927 ps
CPU time 436.12 seconds
Started May 26 02:31:23 PM PDT 24
Finished May 26 02:38:40 PM PDT 24
Peak memory 201860 kb
Host smart-0259a5b2-5b0f-4f1c-bdf0-165f623e08cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549784886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2549784886
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2114323327
Short name T191
Test name
Test status
Simulation time 328456949844 ps
CPU time 360.99 seconds
Started May 26 02:31:35 PM PDT 24
Finished May 26 02:37:37 PM PDT 24
Peak memory 201892 kb
Host smart-85cad4fa-0915-4883-940a-d070541e084a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114323327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2114323327
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1317604390
Short name T786
Test name
Test status
Simulation time 493428155051 ps
CPU time 1097.09 seconds
Started May 26 02:31:24 PM PDT 24
Finished May 26 02:49:42 PM PDT 24
Peak memory 201816 kb
Host smart-64505726-b438-4160-96f5-04edac9406de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317604390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1317604390
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3719523143
Short name T5
Test name
Test status
Simulation time 480717868035 ps
CPU time 181.82 seconds
Started May 26 02:31:35 PM PDT 24
Finished May 26 02:34:38 PM PDT 24
Peak memory 201168 kb
Host smart-8c966fe9-5f2d-494f-8312-d0ac2dc81ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719523143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3719523143
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3723279137
Short name T662
Test name
Test status
Simulation time 493105847078 ps
CPU time 776.81 seconds
Started May 26 02:31:25 PM PDT 24
Finished May 26 02:44:23 PM PDT 24
Peak memory 201792 kb
Host smart-64a1caa3-4983-42ab-aab8-448d2e195a9e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723279137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3723279137
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.874139490
Short name T163
Test name
Test status
Simulation time 532077143458 ps
CPU time 191.91 seconds
Started May 26 02:31:25 PM PDT 24
Finished May 26 02:34:37 PM PDT 24
Peak memory 201880 kb
Host smart-d20d85f1-8a8f-4bc6-8f3f-09b8a26cf7e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874139490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.874139490
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.291875526
Short name T237
Test name
Test status
Simulation time 600469337290 ps
CPU time 354.41 seconds
Started May 26 02:31:25 PM PDT 24
Finished May 26 02:37:20 PM PDT 24
Peak memory 201808 kb
Host smart-0632de32-bee5-4256-9767-efeeade58f8e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291875526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.291875526
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3181357214
Short name T446
Test name
Test status
Simulation time 116143369619 ps
CPU time 586.26 seconds
Started May 26 02:31:26 PM PDT 24
Finished May 26 02:41:14 PM PDT 24
Peak memory 202164 kb
Host smart-af5f1af7-7f7d-4f8f-ac39-dd623ddb25c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181357214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3181357214
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.288674583
Short name T403
Test name
Test status
Simulation time 43641927321 ps
CPU time 23.15 seconds
Started May 26 02:31:26 PM PDT 24
Finished May 26 02:31:51 PM PDT 24
Peak memory 201576 kb
Host smart-584c1fd9-5bf4-484f-982d-8d873a97d42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288674583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.288674583
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2615547586
Short name T380
Test name
Test status
Simulation time 4446104065 ps
CPU time 5.25 seconds
Started May 26 02:31:26 PM PDT 24
Finished May 26 02:31:32 PM PDT 24
Peak memory 201660 kb
Host smart-6f9d83a4-a990-4509-9715-a49746b7e1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615547586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2615547586
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3559615006
Short name T414
Test name
Test status
Simulation time 5990127716 ps
CPU time 7.54 seconds
Started May 26 02:31:26 PM PDT 24
Finished May 26 02:31:35 PM PDT 24
Peak memory 201692 kb
Host smart-e5c44cad-14ff-4f41-a96c-f07f73b0ad0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559615006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3559615006
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.870888087
Short name T742
Test name
Test status
Simulation time 295893191779 ps
CPU time 166.68 seconds
Started May 26 02:31:24 PM PDT 24
Finished May 26 02:34:11 PM PDT 24
Peak memory 210192 kb
Host smart-30e138e8-89c2-48b7-8b1b-7008d24ded63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870888087 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.870888087
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.179502675
Short name T397
Test name
Test status
Simulation time 467827275 ps
CPU time 1.67 seconds
Started May 26 02:31:31 PM PDT 24
Finished May 26 02:31:33 PM PDT 24
Peak memory 201440 kb
Host smart-d60a1b3c-f3ff-4fe8-ba45-81812807b9e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179502675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.179502675
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1043848959
Short name T201
Test name
Test status
Simulation time 196662047691 ps
CPU time 43.06 seconds
Started May 26 02:31:26 PM PDT 24
Finished May 26 02:32:10 PM PDT 24
Peak memory 201868 kb
Host smart-a5027a02-f7ce-40a9-bbdd-899fda7190c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043848959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1043848959
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1568827284
Short name T31
Test name
Test status
Simulation time 158909145010 ps
CPU time 375.78 seconds
Started May 26 02:31:35 PM PDT 24
Finished May 26 02:37:52 PM PDT 24
Peak memory 201816 kb
Host smart-8ce3680e-1e96-4d44-a6af-815ef14d477f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568827284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1568827284
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2748646595
Short name T718
Test name
Test status
Simulation time 489348323067 ps
CPU time 266.42 seconds
Started May 26 02:31:28 PM PDT 24
Finished May 26 02:35:56 PM PDT 24
Peak memory 201828 kb
Host smart-b77ce74f-c5e5-4e88-93e1-2168143c70f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748646595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2748646595
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2230571155
Short name T483
Test name
Test status
Simulation time 325117426632 ps
CPU time 393 seconds
Started May 26 02:31:26 PM PDT 24
Finished May 26 02:38:00 PM PDT 24
Peak memory 201860 kb
Host smart-837cb173-6e03-4f55-87b1-75260705f740
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230571155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2230571155
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2159467157
Short name T251
Test name
Test status
Simulation time 322560421295 ps
CPU time 738.38 seconds
Started May 26 02:31:26 PM PDT 24
Finished May 26 02:43:46 PM PDT 24
Peak memory 201840 kb
Host smart-aa3dcacd-f146-4f69-ad6a-c72144816cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159467157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2159467157
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2049520222
Short name T520
Test name
Test status
Simulation time 490535570785 ps
CPU time 1154.68 seconds
Started May 26 02:31:35 PM PDT 24
Finished May 26 02:50:51 PM PDT 24
Peak memory 201120 kb
Host smart-69543f55-a092-49a2-8df7-1d89d9f01a11
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049520222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2049520222
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2991677018
Short name T552
Test name
Test status
Simulation time 609799362578 ps
CPU time 1455.51 seconds
Started May 26 02:31:27 PM PDT 24
Finished May 26 02:55:44 PM PDT 24
Peak memory 201816 kb
Host smart-de49c743-2ca7-491e-b51c-0c9a04a51479
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991677018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2991677018
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.903612359
Short name T202
Test name
Test status
Simulation time 93945663203 ps
CPU time 304.73 seconds
Started May 26 02:31:25 PM PDT 24
Finished May 26 02:36:31 PM PDT 24
Peak memory 202156 kb
Host smart-7885802e-07f8-4a66-bd1e-549da6d3b7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903612359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.903612359
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1880240427
Short name T537
Test name
Test status
Simulation time 37859760879 ps
CPU time 22.75 seconds
Started May 26 02:31:25 PM PDT 24
Finished May 26 02:31:49 PM PDT 24
Peak memory 201612 kb
Host smart-5e5d6532-ee94-4b4a-88be-d530586c5e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880240427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1880240427
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.4049815066
Short name T28
Test name
Test status
Simulation time 5169760586 ps
CPU time 3.57 seconds
Started May 26 02:31:35 PM PDT 24
Finished May 26 02:31:40 PM PDT 24
Peak memory 201636 kb
Host smart-77791e6a-a393-4454-b570-f39fdc645de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049815066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.4049815066
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1452227523
Short name T77
Test name
Test status
Simulation time 4420912041 ps
CPU time 9.55 seconds
Started May 26 02:31:34 PM PDT 24
Finished May 26 02:31:44 PM PDT 24
Peak memory 217380 kb
Host smart-1242301f-0ef5-4c30-a62a-49231d60ea35
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452227523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1452227523
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3045730642
Short name T570
Test name
Test status
Simulation time 6036443930 ps
CPU time 4.42 seconds
Started May 26 02:31:25 PM PDT 24
Finished May 26 02:31:30 PM PDT 24
Peak memory 201692 kb
Host smart-041a1307-6134-4be9-bea0-ad9b75ec1b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045730642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3045730642
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2637580586
Short name T367
Test name
Test status
Simulation time 508502051 ps
CPU time 0.93 seconds
Started May 26 02:32:00 PM PDT 24
Finished May 26 02:32:02 PM PDT 24
Peak memory 201528 kb
Host smart-cc25c6b0-a63a-4cef-be2d-3ced9e342bb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637580586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2637580586
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.68766187
Short name T156
Test name
Test status
Simulation time 164424747659 ps
CPU time 23.87 seconds
Started May 26 02:31:57 PM PDT 24
Finished May 26 02:32:23 PM PDT 24
Peak memory 201752 kb
Host smart-ec388716-ab95-4398-854e-ce006d5b6796
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68766187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gatin
g.68766187
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.52253429
Short name T232
Test name
Test status
Simulation time 338058378147 ps
CPU time 847 seconds
Started May 26 02:32:05 PM PDT 24
Finished May 26 02:46:13 PM PDT 24
Peak memory 201948 kb
Host smart-4b59dbe6-0f99-42c0-a19b-1fb6a0cf4781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52253429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.52253429
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.4145034180
Short name T134
Test name
Test status
Simulation time 480916272368 ps
CPU time 279.16 seconds
Started May 26 02:31:58 PM PDT 24
Finished May 26 02:36:38 PM PDT 24
Peak memory 201932 kb
Host smart-2e7e9024-2c01-4ddc-9b02-cb1a46bc9ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145034180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.4145034180
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.4169663943
Short name T144
Test name
Test status
Simulation time 168224928310 ps
CPU time 33.19 seconds
Started May 26 02:31:59 PM PDT 24
Finished May 26 02:32:34 PM PDT 24
Peak memory 201888 kb
Host smart-550d2973-291f-4d45-af7a-4b1a744806ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169663943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.4169663943
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.20299232
Short name T279
Test name
Test status
Simulation time 160945109156 ps
CPU time 158.76 seconds
Started May 26 02:31:59 PM PDT 24
Finished May 26 02:34:40 PM PDT 24
Peak memory 201928 kb
Host smart-4d2b8f88-4124-47dc-88da-d1c8e131fe19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20299232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.20299232
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1912188710
Short name T154
Test name
Test status
Simulation time 335397076594 ps
CPU time 180.33 seconds
Started May 26 02:31:57 PM PDT 24
Finished May 26 02:34:59 PM PDT 24
Peak memory 201848 kb
Host smart-b78a693c-0dbb-4550-9547-902c2fdda28a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912188710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1912188710
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1949060867
Short name T326
Test name
Test status
Simulation time 475287350205 ps
CPU time 959.39 seconds
Started May 26 02:31:57 PM PDT 24
Finished May 26 02:47:58 PM PDT 24
Peak memory 201936 kb
Host smart-56a96902-abf2-4771-b5a1-86521d7ab9a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949060867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1949060867
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.218986594
Short name T425
Test name
Test status
Simulation time 207310869743 ps
CPU time 475.94 seconds
Started May 26 02:31:57 PM PDT 24
Finished May 26 02:39:54 PM PDT 24
Peak memory 201752 kb
Host smart-8cf930b5-d9db-43ca-ad97-01c9827d4df5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218986594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.218986594
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3068635628
Short name T383
Test name
Test status
Simulation time 55109465844 ps
CPU time 225.03 seconds
Started May 26 02:31:58 PM PDT 24
Finished May 26 02:35:45 PM PDT 24
Peak memory 202212 kb
Host smart-49f41591-6839-441d-b9b7-f11750e23170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068635628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3068635628
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.408031992
Short name T548
Test name
Test status
Simulation time 34207046511 ps
CPU time 77.79 seconds
Started May 26 02:31:59 PM PDT 24
Finished May 26 02:33:18 PM PDT 24
Peak memory 201660 kb
Host smart-fec58d8a-c6f2-4dc7-91bf-2d3685a8904e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408031992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.408031992
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1983551199
Short name T499
Test name
Test status
Simulation time 3704383975 ps
CPU time 2.89 seconds
Started May 26 02:31:59 PM PDT 24
Finished May 26 02:32:03 PM PDT 24
Peak memory 201584 kb
Host smart-fbb1fffc-dd4d-4370-a983-fc44d44bade8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983551199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1983551199
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3841859016
Short name T473
Test name
Test status
Simulation time 5887185156 ps
CPU time 10.12 seconds
Started May 26 02:32:00 PM PDT 24
Finished May 26 02:32:12 PM PDT 24
Peak memory 201652 kb
Host smart-487c6664-e0ae-40aa-82c9-5fec1e7dfcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841859016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3841859016
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1613908218
Short name T642
Test name
Test status
Simulation time 609350428998 ps
CPU time 1422.69 seconds
Started May 26 02:31:59 PM PDT 24
Finished May 26 02:55:43 PM PDT 24
Peak memory 201964 kb
Host smart-4784f2c8-444e-458b-bb2c-24f55f7e8b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613908218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1613908218
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2658746698
Short name T20
Test name
Test status
Simulation time 20740513236 ps
CPU time 46.28 seconds
Started May 26 02:31:59 PM PDT 24
Finished May 26 02:32:47 PM PDT 24
Peak memory 210136 kb
Host smart-ecb0a2b7-0b17-465f-92f6-d8e04e05a438
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658746698 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2658746698
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3830415900
Short name T498
Test name
Test status
Simulation time 400954547 ps
CPU time 1.54 seconds
Started May 26 02:31:57 PM PDT 24
Finished May 26 02:32:00 PM PDT 24
Peak memory 201548 kb
Host smart-a54fe90d-968b-4f42-ab29-2ffa8575e226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830415900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3830415900
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.34958082
Short name T666
Test name
Test status
Simulation time 345516127157 ps
CPU time 195.76 seconds
Started May 26 02:32:00 PM PDT 24
Finished May 26 02:35:17 PM PDT 24
Peak memory 201856 kb
Host smart-4d7f07ec-2f66-4a96-a7b7-3911d3af1f63
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34958082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gatin
g.34958082
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3119434819
Short name T229
Test name
Test status
Simulation time 161750230703 ps
CPU time 184.68 seconds
Started May 26 02:32:05 PM PDT 24
Finished May 26 02:35:10 PM PDT 24
Peak memory 201848 kb
Host smart-ce0a00c7-6e9a-4cba-960d-c1e90ca873bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119434819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3119434819
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3822845239
Short name T266
Test name
Test status
Simulation time 481172423320 ps
CPU time 603.17 seconds
Started May 26 02:31:59 PM PDT 24
Finished May 26 02:42:03 PM PDT 24
Peak memory 201836 kb
Host smart-88c49580-9d9d-40aa-92b8-6a5a460f4f40
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822845239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3822845239
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.727772123
Short name T150
Test name
Test status
Simulation time 487632272601 ps
CPU time 296.81 seconds
Started May 26 02:32:01 PM PDT 24
Finished May 26 02:36:59 PM PDT 24
Peak memory 201812 kb
Host smart-ce1c47cb-36a4-46fb-9945-65c3ff114586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727772123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.727772123
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1213031682
Short name T602
Test name
Test status
Simulation time 485094943317 ps
CPU time 290.26 seconds
Started May 26 02:31:57 PM PDT 24
Finished May 26 02:36:49 PM PDT 24
Peak memory 201836 kb
Host smart-547c5f7b-adf2-457f-aea2-7d19212fc193
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213031682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1213031682
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1623441815
Short name T280
Test name
Test status
Simulation time 176303332826 ps
CPU time 385.9 seconds
Started May 26 02:31:56 PM PDT 24
Finished May 26 02:38:22 PM PDT 24
Peak memory 201956 kb
Host smart-066839f5-c561-4111-91bf-94cff2486720
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623441815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1623441815
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1205280218
Short name T389
Test name
Test status
Simulation time 396122933037 ps
CPU time 444.81 seconds
Started May 26 02:32:00 PM PDT 24
Finished May 26 02:39:26 PM PDT 24
Peak memory 201812 kb
Host smart-44e5fca6-0f49-485f-a8b8-3352029669f2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205280218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1205280218
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.143753879
Short name T413
Test name
Test status
Simulation time 26523740066 ps
CPU time 58.46 seconds
Started May 26 02:31:57 PM PDT 24
Finished May 26 02:32:57 PM PDT 24
Peak memory 201684 kb
Host smart-b01918ff-5c25-4ad2-bae7-6be0770d4987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143753879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.143753879
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2299497211
Short name T608
Test name
Test status
Simulation time 5124496142 ps
CPU time 10.23 seconds
Started May 26 02:32:05 PM PDT 24
Finished May 26 02:32:16 PM PDT 24
Peak memory 201684 kb
Host smart-d65d2db4-a3fd-45f7-b113-62619029c8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299497211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2299497211
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.4185767428
Short name T469
Test name
Test status
Simulation time 6089904166 ps
CPU time 4.54 seconds
Started May 26 02:31:57 PM PDT 24
Finished May 26 02:32:03 PM PDT 24
Peak memory 201668 kb
Host smart-397a3943-243d-4d82-995e-aae87442d482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185767428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.4185767428
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2682935212
Short name T668
Test name
Test status
Simulation time 407838743 ps
CPU time 0.87 seconds
Started May 26 02:32:04 PM PDT 24
Finished May 26 02:32:05 PM PDT 24
Peak memory 201536 kb
Host smart-4399d909-72ad-4329-9438-20868ba76475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682935212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2682935212
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.397082338
Short name T739
Test name
Test status
Simulation time 501700100668 ps
CPU time 1081.91 seconds
Started May 26 02:31:59 PM PDT 24
Finished May 26 02:50:02 PM PDT 24
Peak memory 201928 kb
Host smart-7056d38f-d162-4ae7-b71c-e11b720466e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397082338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.397082338
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2078056796
Short name T706
Test name
Test status
Simulation time 331661789147 ps
CPU time 718.63 seconds
Started May 26 02:31:58 PM PDT 24
Finished May 26 02:43:58 PM PDT 24
Peak memory 201808 kb
Host smart-b44f4067-9af1-43fe-ae17-c26dbe6bc5f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078056796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2078056796
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1475625847
Short name T524
Test name
Test status
Simulation time 160672601757 ps
CPU time 100.26 seconds
Started May 26 02:31:58 PM PDT 24
Finished May 26 02:33:40 PM PDT 24
Peak memory 201848 kb
Host smart-30f10273-1f65-400b-817b-1133cf290c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475625847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1475625847
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2789258006
Short name T165
Test name
Test status
Simulation time 160407924373 ps
CPU time 367 seconds
Started May 26 02:32:00 PM PDT 24
Finished May 26 02:38:08 PM PDT 24
Peak memory 201828 kb
Host smart-24d8fbed-e565-4c2e-8067-71a84a685c2e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789258006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2789258006
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2478258833
Short name T566
Test name
Test status
Simulation time 415269460495 ps
CPU time 660.16 seconds
Started May 26 02:31:59 PM PDT 24
Finished May 26 02:43:01 PM PDT 24
Peak memory 201896 kb
Host smart-8cb332cb-a2c6-40f6-bd26-1016dbd07b1f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478258833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.2478258833
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1617626791
Short name T714
Test name
Test status
Simulation time 124914660007 ps
CPU time 479.85 seconds
Started May 26 02:31:56 PM PDT 24
Finished May 26 02:39:56 PM PDT 24
Peak memory 202224 kb
Host smart-6689be77-af0c-4557-9eea-2fdc5888368d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617626791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1617626791
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3851765530
Short name T358
Test name
Test status
Simulation time 31370150980 ps
CPU time 70.62 seconds
Started May 26 02:31:58 PM PDT 24
Finished May 26 02:33:10 PM PDT 24
Peak memory 201692 kb
Host smart-755870d2-2d05-490a-abe5-7e3b0a47d75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851765530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3851765530
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1536413594
Short name T10
Test name
Test status
Simulation time 4725701977 ps
CPU time 3.23 seconds
Started May 26 02:31:57 PM PDT 24
Finished May 26 02:32:01 PM PDT 24
Peak memory 201680 kb
Host smart-f1217de5-0b90-4f5c-8ea4-93797fd0d7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536413594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1536413594
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2193813583
Short name T604
Test name
Test status
Simulation time 5724098714 ps
CPU time 4.29 seconds
Started May 26 02:31:59 PM PDT 24
Finished May 26 02:32:05 PM PDT 24
Peak memory 201668 kb
Host smart-6bc1fb6a-82f9-447a-a239-7c3631c7cf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193813583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2193813583
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1935878622
Short name T349
Test name
Test status
Simulation time 93974908672 ps
CPU time 343.83 seconds
Started May 26 02:32:06 PM PDT 24
Finished May 26 02:37:51 PM PDT 24
Peak memory 202180 kb
Host smart-57ef2ad6-405e-4b11-b5bc-73f6c7ec50b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935878622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1935878622
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.157090521
Short name T333
Test name
Test status
Simulation time 268686654088 ps
CPU time 159.73 seconds
Started May 26 02:32:06 PM PDT 24
Finished May 26 02:34:47 PM PDT 24
Peak memory 210156 kb
Host smart-b1f7537e-0061-4ad3-9353-b7ef76c4247d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157090521 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.157090521
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2765322717
Short name T512
Test name
Test status
Simulation time 202064776624 ps
CPU time 491.73 seconds
Started May 26 02:32:05 PM PDT 24
Finished May 26 02:40:17 PM PDT 24
Peak memory 201792 kb
Host smart-1092cea0-45de-4a89-91f2-39c8630fedbe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765322717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2765322717
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3214045901
Short name T331
Test name
Test status
Simulation time 357323633987 ps
CPU time 229.69 seconds
Started May 26 02:32:09 PM PDT 24
Finished May 26 02:35:59 PM PDT 24
Peak memory 201844 kb
Host smart-4ddee86f-3801-482b-9fa8-f74d6f05e9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214045901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3214045901
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.783397461
Short name T554
Test name
Test status
Simulation time 165143397377 ps
CPU time 101.39 seconds
Started May 26 02:32:04 PM PDT 24
Finished May 26 02:33:46 PM PDT 24
Peak memory 201840 kb
Host smart-c18d5805-0182-4f66-ac8b-655d218f356e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783397461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.783397461
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2366726087
Short name T649
Test name
Test status
Simulation time 158158035224 ps
CPU time 88.64 seconds
Started May 26 02:32:07 PM PDT 24
Finished May 26 02:33:37 PM PDT 24
Peak memory 201916 kb
Host smart-dbedffdc-6cf0-4d83-b90a-d0ec0c9d0dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366726087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2366726087
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2770374561
Short name T583
Test name
Test status
Simulation time 328889923059 ps
CPU time 267.32 seconds
Started May 26 02:32:06 PM PDT 24
Finished May 26 02:36:34 PM PDT 24
Peak memory 201808 kb
Host smart-413bac8d-50b2-4577-8085-39f8a154a782
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770374561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2770374561
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2388204916
Short name T325
Test name
Test status
Simulation time 340913898974 ps
CPU time 191.89 seconds
Started May 26 02:32:06 PM PDT 24
Finished May 26 02:35:19 PM PDT 24
Peak memory 201880 kb
Host smart-3c1b1925-3873-441e-9d67-de372bcd2f5c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388204916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2388204916
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2733666894
Short name T768
Test name
Test status
Simulation time 420198908272 ps
CPU time 919.14 seconds
Started May 26 02:32:07 PM PDT 24
Finished May 26 02:47:27 PM PDT 24
Peak memory 201828 kb
Host smart-780a9b0c-34ae-4d9d-88f0-3de8431bd238
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733666894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2733666894
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1887394259
Short name T476
Test name
Test status
Simulation time 135877994276 ps
CPU time 409.24 seconds
Started May 26 02:32:04 PM PDT 24
Finished May 26 02:38:54 PM PDT 24
Peak memory 202256 kb
Host smart-6fb41d59-bb58-4390-ab63-e735f52b525f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887394259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1887394259
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2150541739
Short name T438
Test name
Test status
Simulation time 35259200200 ps
CPU time 21.27 seconds
Started May 26 02:32:07 PM PDT 24
Finished May 26 02:32:29 PM PDT 24
Peak memory 201688 kb
Host smart-769998bb-b315-493a-bc3d-5508b5e452ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150541739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2150541739
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.804554487
Short name T618
Test name
Test status
Simulation time 3977536307 ps
CPU time 3.2 seconds
Started May 26 02:32:06 PM PDT 24
Finished May 26 02:32:10 PM PDT 24
Peak memory 201644 kb
Host smart-bdadfb93-ce43-4e02-98b9-1b32aee72345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804554487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.804554487
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1200264046
Short name T167
Test name
Test status
Simulation time 5675363990 ps
CPU time 3.6 seconds
Started May 26 02:32:04 PM PDT 24
Finished May 26 02:32:08 PM PDT 24
Peak memory 201672 kb
Host smart-10fccb00-6823-4577-8046-43f844bdc7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200264046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1200264046
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.345419866
Short name T749
Test name
Test status
Simulation time 64329694611 ps
CPU time 135.58 seconds
Started May 26 02:32:08 PM PDT 24
Finished May 26 02:34:24 PM PDT 24
Peak memory 210224 kb
Host smart-4d491692-2797-42da-952e-3d0cfd304140
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345419866 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.345419866
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1686741006
Short name T91
Test name
Test status
Simulation time 368916123 ps
CPU time 0.87 seconds
Started May 26 02:32:05 PM PDT 24
Finished May 26 02:32:07 PM PDT 24
Peak memory 201536 kb
Host smart-dca6a160-29dd-4c71-b353-6b62b119dc1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686741006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1686741006
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1909003155
Short name T657
Test name
Test status
Simulation time 334488090306 ps
CPU time 457.55 seconds
Started May 26 02:32:03 PM PDT 24
Finished May 26 02:39:42 PM PDT 24
Peak memory 201912 kb
Host smart-bf4a8ebc-1402-4700-bf86-39f01b48883e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909003155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1909003155
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.383942570
Short name T90
Test name
Test status
Simulation time 171145294218 ps
CPU time 62.83 seconds
Started May 26 02:32:10 PM PDT 24
Finished May 26 02:33:14 PM PDT 24
Peak memory 201848 kb
Host smart-6dd19700-a89f-43c7-8010-d058bcf556d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383942570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.383942570
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.572571889
Short name T791
Test name
Test status
Simulation time 329251772793 ps
CPU time 217.28 seconds
Started May 26 02:32:08 PM PDT 24
Finished May 26 02:35:46 PM PDT 24
Peak memory 201876 kb
Host smart-3233d97b-0d12-4117-ad40-909e3c50c97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572571889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.572571889
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2073923342
Short name T584
Test name
Test status
Simulation time 332960048221 ps
CPU time 796.51 seconds
Started May 26 02:32:08 PM PDT 24
Finished May 26 02:45:25 PM PDT 24
Peak memory 201800 kb
Host smart-6b29b672-65cf-49c2-baa5-784bf7cbeee7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073923342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2073923342
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2747281360
Short name T733
Test name
Test status
Simulation time 163092471316 ps
CPU time 94.07 seconds
Started May 26 02:32:05 PM PDT 24
Finished May 26 02:33:40 PM PDT 24
Peak memory 201852 kb
Host smart-564199bb-bb7f-4a77-9c89-a852eeef2b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747281360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2747281360
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2379172350
Short name T50
Test name
Test status
Simulation time 163772402000 ps
CPU time 46.97 seconds
Started May 26 02:32:06 PM PDT 24
Finished May 26 02:32:54 PM PDT 24
Peak memory 201888 kb
Host smart-dd210b29-a237-425e-8c22-ef93a60bef98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379172350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2379172350
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2754986577
Short name T296
Test name
Test status
Simulation time 546150835187 ps
CPU time 1313.36 seconds
Started May 26 02:32:07 PM PDT 24
Finished May 26 02:54:01 PM PDT 24
Peak memory 201844 kb
Host smart-e7c4578e-4a44-4b31-88a6-7537ca449ac8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754986577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2754986577
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1530452332
Short name T478
Test name
Test status
Simulation time 398346733648 ps
CPU time 997.94 seconds
Started May 26 02:32:06 PM PDT 24
Finished May 26 02:48:45 PM PDT 24
Peak memory 201836 kb
Host smart-283eb68d-7db8-43ef-8ea4-3370cab0f499
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530452332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1530452332
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2139063997
Short name T348
Test name
Test status
Simulation time 121520215261 ps
CPU time 449.92 seconds
Started May 26 02:32:07 PM PDT 24
Finished May 26 02:39:37 PM PDT 24
Peak memory 202136 kb
Host smart-cfa26d59-8332-4fb0-887f-85260f38dc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139063997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2139063997
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.671962684
Short name T603
Test name
Test status
Simulation time 45260899946 ps
CPU time 13.14 seconds
Started May 26 02:32:08 PM PDT 24
Finished May 26 02:32:22 PM PDT 24
Peak memory 201664 kb
Host smart-ac67fe57-d46f-40dd-97d4-e369076950d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671962684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.671962684
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3482631699
Short name T502
Test name
Test status
Simulation time 4656444343 ps
CPU time 6.37 seconds
Started May 26 02:32:05 PM PDT 24
Finished May 26 02:32:12 PM PDT 24
Peak memory 201648 kb
Host smart-27afd963-0442-4e6a-a187-11318001f8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482631699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3482631699
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.961831393
Short name T696
Test name
Test status
Simulation time 5998553048 ps
CPU time 2.7 seconds
Started May 26 02:32:09 PM PDT 24
Finished May 26 02:32:13 PM PDT 24
Peak memory 201688 kb
Host smart-969791ca-92cf-499b-b82e-e9976f10761b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961831393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.961831393
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3710765043
Short name T729
Test name
Test status
Simulation time 178799935330 ps
CPU time 115.04 seconds
Started May 26 02:32:06 PM PDT 24
Finished May 26 02:34:02 PM PDT 24
Peak memory 201828 kb
Host smart-2627f6a5-3cfa-4530-a513-0f4ea3421a3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710765043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3710765043
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3865248410
Short name T568
Test name
Test status
Simulation time 19623093789 ps
CPU time 42.31 seconds
Started May 26 02:32:03 PM PDT 24
Finished May 26 02:32:46 PM PDT 24
Peak memory 210144 kb
Host smart-90767ae9-7b00-46dc-a5b9-911054d9113e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865248410 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3865248410
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.814679198
Short name T596
Test name
Test status
Simulation time 374802562 ps
CPU time 0.83 seconds
Started May 26 02:32:14 PM PDT 24
Finished May 26 02:32:15 PM PDT 24
Peak memory 201544 kb
Host smart-418ce79e-53d0-4a24-b948-90bd244db5f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814679198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.814679198
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1731321898
Short name T674
Test name
Test status
Simulation time 323320486198 ps
CPU time 203.8 seconds
Started May 26 02:32:15 PM PDT 24
Finished May 26 02:35:40 PM PDT 24
Peak memory 201860 kb
Host smart-84389c5b-ceff-40b9-9308-21d83d9b5117
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731321898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1731321898
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2733726753
Short name T313
Test name
Test status
Simulation time 187774978434 ps
CPU time 214.83 seconds
Started May 26 02:32:15 PM PDT 24
Finished May 26 02:35:50 PM PDT 24
Peak memory 201812 kb
Host smart-41c837da-ecf5-412c-a8bd-2b1c4c2e0446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733726753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2733726753
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.978637581
Short name T267
Test name
Test status
Simulation time 496503860204 ps
CPU time 1159.55 seconds
Started May 26 02:32:14 PM PDT 24
Finished May 26 02:51:34 PM PDT 24
Peak memory 201916 kb
Host smart-f240ef30-1570-44a0-9794-02ca7455d9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978637581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.978637581
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.716737085
Short name T781
Test name
Test status
Simulation time 488275805980 ps
CPU time 325.05 seconds
Started May 26 02:32:17 PM PDT 24
Finished May 26 02:37:42 PM PDT 24
Peak memory 201728 kb
Host smart-06f90555-8f80-47c3-b608-fbea5178eb98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=716737085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrup
t_fixed.716737085
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.313661616
Short name T574
Test name
Test status
Simulation time 163508446675 ps
CPU time 348.41 seconds
Started May 26 02:32:08 PM PDT 24
Finished May 26 02:37:57 PM PDT 24
Peak memory 201904 kb
Host smart-5a34bd3c-ac2c-4788-a6e5-2adebc6505cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313661616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.313661616
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3709585671
Short name T495
Test name
Test status
Simulation time 331330775549 ps
CPU time 187.1 seconds
Started May 26 02:32:14 PM PDT 24
Finished May 26 02:35:22 PM PDT 24
Peak memory 201820 kb
Host smart-ef49f5aa-4c00-4965-817b-5a45523e6280
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709585671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3709585671
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.368423194
Short name T501
Test name
Test status
Simulation time 590400974858 ps
CPU time 161.24 seconds
Started May 26 02:32:17 PM PDT 24
Finished May 26 02:34:58 PM PDT 24
Peak memory 201816 kb
Host smart-908c7795-d198-4bf4-b82d-9dade2db0123
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368423194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
adc_ctrl_filters_wakeup_fixed.368423194
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1298083566
Short name T475
Test name
Test status
Simulation time 116281792932 ps
CPU time 660.47 seconds
Started May 26 02:32:14 PM PDT 24
Finished May 26 02:43:16 PM PDT 24
Peak memory 202256 kb
Host smart-507e951f-e50a-4e94-b97f-722c3846de17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298083566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1298083566
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1808996917
Short name T597
Test name
Test status
Simulation time 41803837999 ps
CPU time 51.39 seconds
Started May 26 02:32:15 PM PDT 24
Finished May 26 02:33:07 PM PDT 24
Peak memory 201680 kb
Host smart-1937c17c-c919-4096-9fdb-d476844fb0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808996917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1808996917
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3794691414
Short name T789
Test name
Test status
Simulation time 3617160429 ps
CPU time 4.63 seconds
Started May 26 02:32:15 PM PDT 24
Finished May 26 02:32:20 PM PDT 24
Peak memory 201580 kb
Host smart-6974c6b8-23cc-4c85-ba19-ba22135734c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794691414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3794691414
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2228774409
Short name T517
Test name
Test status
Simulation time 5961801834 ps
CPU time 15.87 seconds
Started May 26 02:32:07 PM PDT 24
Finished May 26 02:32:24 PM PDT 24
Peak memory 201668 kb
Host smart-33c50496-eb6a-450c-bbcd-b9b0e205d0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228774409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2228774409
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2899589429
Short name T252
Test name
Test status
Simulation time 199054125216 ps
CPU time 426.92 seconds
Started May 26 02:32:13 PM PDT 24
Finished May 26 02:39:21 PM PDT 24
Peak memory 201804 kb
Host smart-67d394cf-4435-4c9d-abf9-d0a0faa0236c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899589429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2899589429
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1398249987
Short name T489
Test name
Test status
Simulation time 325389278 ps
CPU time 0.82 seconds
Started May 26 02:32:25 PM PDT 24
Finished May 26 02:32:26 PM PDT 24
Peak memory 201532 kb
Host smart-8344ae3e-4e2d-4a66-bee7-a93d67a847d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398249987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1398249987
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.219490012
Short name T304
Test name
Test status
Simulation time 324849341789 ps
CPU time 393.2 seconds
Started May 26 02:32:27 PM PDT 24
Finished May 26 02:39:01 PM PDT 24
Peak memory 201864 kb
Host smart-58776aeb-c4c5-4987-9ede-d5dfef22d7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219490012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.219490012
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1442184530
Short name T323
Test name
Test status
Simulation time 322767431423 ps
CPU time 749.78 seconds
Started May 26 02:32:23 PM PDT 24
Finished May 26 02:44:53 PM PDT 24
Peak memory 201800 kb
Host smart-2b1aaa04-2106-40fe-b28d-127695856d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442184530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1442184530
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2336388916
Short name T463
Test name
Test status
Simulation time 321260730763 ps
CPU time 764.3 seconds
Started May 26 02:32:25 PM PDT 24
Finished May 26 02:45:10 PM PDT 24
Peak memory 201716 kb
Host smart-cb2607fe-42ae-40e0-8efa-06c6f63890bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336388916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2336388916
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1259389693
Short name T162
Test name
Test status
Simulation time 492473189992 ps
CPU time 297.04 seconds
Started May 26 02:32:24 PM PDT 24
Finished May 26 02:37:22 PM PDT 24
Peak memory 201884 kb
Host smart-91e94d8e-3f9a-4f1e-bd10-dd14d2beed78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259389693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1259389693
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1289312220
Short name T392
Test name
Test status
Simulation time 328554422545 ps
CPU time 195.62 seconds
Started May 26 02:32:26 PM PDT 24
Finished May 26 02:35:43 PM PDT 24
Peak memory 201828 kb
Host smart-b63c6f56-4561-4ce2-9d7e-878c29f30cbe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289312220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1289312220
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1347457344
Short name T274
Test name
Test status
Simulation time 369184251942 ps
CPU time 95.14 seconds
Started May 26 02:32:24 PM PDT 24
Finished May 26 02:33:59 PM PDT 24
Peak memory 201932 kb
Host smart-301dcd0a-d518-4923-a776-cfddd19c22db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347457344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1347457344
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1879516592
Short name T796
Test name
Test status
Simulation time 412874674705 ps
CPU time 299.39 seconds
Started May 26 02:32:25 PM PDT 24
Finished May 26 02:37:25 PM PDT 24
Peak memory 201864 kb
Host smart-77e6b759-7f78-43ee-85b1-aa3b7652f272
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879516592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1879516592
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.616252661
Short name T342
Test name
Test status
Simulation time 109216006156 ps
CPU time 533.96 seconds
Started May 26 02:32:24 PM PDT 24
Finished May 26 02:41:19 PM PDT 24
Peak memory 202148 kb
Host smart-4eed42aa-616b-4bf5-b2bc-ec06631932a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616252661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.616252661
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2474001430
Short name T636
Test name
Test status
Simulation time 40397194371 ps
CPU time 24.94 seconds
Started May 26 02:32:23 PM PDT 24
Finished May 26 02:32:48 PM PDT 24
Peak memory 201684 kb
Host smart-deb6dea5-32b2-4d3f-ad10-974f71805003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474001430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2474001430
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1777143236
Short name T544
Test name
Test status
Simulation time 5322604690 ps
CPU time 2.02 seconds
Started May 26 02:32:24 PM PDT 24
Finished May 26 02:32:26 PM PDT 24
Peak memory 201632 kb
Host smart-87e11c7b-af1e-42d2-9c04-45a0d8f1085b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777143236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1777143236
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1256058577
Short name T377
Test name
Test status
Simulation time 5917038983 ps
CPU time 13.98 seconds
Started May 26 02:32:16 PM PDT 24
Finished May 26 02:32:30 PM PDT 24
Peak memory 201668 kb
Host smart-441726ac-a069-4304-9cdb-b04f2ae2df89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256058577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1256058577
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2518368634
Short name T578
Test name
Test status
Simulation time 314482214022 ps
CPU time 251.01 seconds
Started May 26 02:32:25 PM PDT 24
Finished May 26 02:36:37 PM PDT 24
Peak memory 210416 kb
Host smart-16b223f6-bc34-4b7e-b122-4c19bfe6fe58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518368634 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2518368634
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3041584293
Short name T424
Test name
Test status
Simulation time 478164460 ps
CPU time 0.85 seconds
Started May 26 02:32:32 PM PDT 24
Finished May 26 02:32:34 PM PDT 24
Peak memory 201532 kb
Host smart-d94b132d-ecd0-46e8-b4f9-c27ebe0453fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041584293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3041584293
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2831456952
Short name T86
Test name
Test status
Simulation time 369162081444 ps
CPU time 60.62 seconds
Started May 26 02:32:24 PM PDT 24
Finished May 26 02:33:25 PM PDT 24
Peak memory 201828 kb
Host smart-b4176e4c-0141-4709-9917-d6d77cff3970
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831456952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2831456952
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.2182800726
Short name T756
Test name
Test status
Simulation time 162931015397 ps
CPU time 80.39 seconds
Started May 26 02:32:26 PM PDT 24
Finished May 26 02:33:47 PM PDT 24
Peak memory 201852 kb
Host smart-bba00211-77c3-45e4-bb70-155d40031e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182800726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.2182800726
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1390087599
Short name T678
Test name
Test status
Simulation time 164755312390 ps
CPU time 362.35 seconds
Started May 26 02:32:24 PM PDT 24
Finished May 26 02:38:27 PM PDT 24
Peak memory 201932 kb
Host smart-627f9628-ea65-48fc-8957-15a5e31d39ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390087599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1390087599
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3167101465
Short name T451
Test name
Test status
Simulation time 324212705355 ps
CPU time 676.55 seconds
Started May 26 02:32:24 PM PDT 24
Finished May 26 02:43:41 PM PDT 24
Peak memory 201828 kb
Host smart-17ed8e61-a31f-46ff-9f91-040aa4962d64
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167101465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.3167101465
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2990149071
Short name T611
Test name
Test status
Simulation time 167258538983 ps
CPU time 192.59 seconds
Started May 26 02:32:25 PM PDT 24
Finished May 26 02:35:38 PM PDT 24
Peak memory 201776 kb
Host smart-34dfa531-69c9-4daa-b9c1-03662fc5fe94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990149071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2990149071
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.656784724
Short name T692
Test name
Test status
Simulation time 168713412085 ps
CPU time 107.04 seconds
Started May 26 02:32:22 PM PDT 24
Finished May 26 02:34:10 PM PDT 24
Peak memory 201776 kb
Host smart-958e836a-6358-4d8b-ac69-f81dda93b375
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=656784724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.656784724
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2008629064
Short name T486
Test name
Test status
Simulation time 173370903942 ps
CPU time 201.86 seconds
Started May 26 02:32:24 PM PDT 24
Finished May 26 02:35:46 PM PDT 24
Peak memory 201828 kb
Host smart-1c8d2262-7e5b-4672-84c1-c46277c0729a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008629064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2008629064
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3454427708
Short name T422
Test name
Test status
Simulation time 400739020206 ps
CPU time 94.35 seconds
Started May 26 02:32:25 PM PDT 24
Finished May 26 02:34:00 PM PDT 24
Peak memory 201820 kb
Host smart-f252b38d-f274-41cc-9bf6-4f67daaab580
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454427708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3454427708
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2428326446
Short name T688
Test name
Test status
Simulation time 94788793571 ps
CPU time 342.29 seconds
Started May 26 02:32:32 PM PDT 24
Finished May 26 02:38:15 PM PDT 24
Peak memory 202160 kb
Host smart-fe663742-d51f-4a68-9cfa-4ced04dd8043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428326446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2428326446
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.4078208779
Short name T677
Test name
Test status
Simulation time 23465432533 ps
CPU time 27.37 seconds
Started May 26 02:32:23 PM PDT 24
Finished May 26 02:32:51 PM PDT 24
Peak memory 201672 kb
Host smart-7853fa67-9d26-4796-8bed-279f3a66f907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078208779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.4078208779
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.815783688
Short name T353
Test name
Test status
Simulation time 4004479733 ps
CPU time 9.69 seconds
Started May 26 02:32:26 PM PDT 24
Finished May 26 02:32:37 PM PDT 24
Peak memory 201540 kb
Host smart-ed48776a-30e2-4c44-9a23-11b871334683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815783688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.815783688
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3922779290
Short name T185
Test name
Test status
Simulation time 5627763559 ps
CPU time 9.38 seconds
Started May 26 02:32:26 PM PDT 24
Finished May 26 02:32:36 PM PDT 24
Peak memory 201688 kb
Host smart-322481ba-0795-479c-b2b8-ac47aa7f2474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922779290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3922779290
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2908138246
Short name T249
Test name
Test status
Simulation time 685412678014 ps
CPU time 738.83 seconds
Started May 26 02:32:32 PM PDT 24
Finished May 26 02:44:52 PM PDT 24
Peak memory 201900 kb
Host smart-b5a6527f-090b-4b8c-8868-f649974c1282
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908138246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2908138246
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.563272770
Short name T557
Test name
Test status
Simulation time 668725531 ps
CPU time 0.71 seconds
Started May 26 02:32:36 PM PDT 24
Finished May 26 02:32:37 PM PDT 24
Peak memory 201492 kb
Host smart-728fe68b-8f1c-441e-a143-d19ec9576ded
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563272770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.563272770
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.747035066
Short name T549
Test name
Test status
Simulation time 161556236391 ps
CPU time 187.25 seconds
Started May 26 02:32:33 PM PDT 24
Finished May 26 02:35:41 PM PDT 24
Peak memory 201752 kb
Host smart-bc17b7c8-3817-4530-921d-99028a3cfe1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747035066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.747035066
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1242341785
Short name T625
Test name
Test status
Simulation time 164554870237 ps
CPU time 389.39 seconds
Started May 26 02:32:32 PM PDT 24
Finished May 26 02:39:02 PM PDT 24
Peak memory 201852 kb
Host smart-c7d15999-07fc-4833-9782-23f5f75b6b6c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242341785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1242341785
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1536469946
Short name T547
Test name
Test status
Simulation time 162462308390 ps
CPU time 87.65 seconds
Started May 26 02:32:34 PM PDT 24
Finished May 26 02:34:02 PM PDT 24
Peak memory 201768 kb
Host smart-c6c4ed71-05d2-4cb7-b588-0d25bac9cb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536469946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1536469946
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.636369277
Short name T104
Test name
Test status
Simulation time 480655611755 ps
CPU time 204.96 seconds
Started May 26 02:32:31 PM PDT 24
Finished May 26 02:35:57 PM PDT 24
Peak memory 201856 kb
Host smart-1918a329-0e19-479e-a86f-6d346fd49933
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=636369277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.636369277
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2618900214
Short name T527
Test name
Test status
Simulation time 184620604302 ps
CPU time 216.67 seconds
Started May 26 02:32:33 PM PDT 24
Finished May 26 02:36:10 PM PDT 24
Peak memory 201860 kb
Host smart-ec52e66e-da88-4059-9de6-cfcb40b74159
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618900214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2618900214
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.158364871
Short name T448
Test name
Test status
Simulation time 197091248053 ps
CPU time 427.91 seconds
Started May 26 02:32:31 PM PDT 24
Finished May 26 02:39:40 PM PDT 24
Peak memory 201844 kb
Host smart-2a6191f1-deaf-4f56-892f-11b03c010636
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158364871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
adc_ctrl_filters_wakeup_fixed.158364871
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.731100904
Short name T715
Test name
Test status
Simulation time 85339394741 ps
CPU time 285.89 seconds
Started May 26 02:32:33 PM PDT 24
Finished May 26 02:37:19 PM PDT 24
Peak memory 202124 kb
Host smart-7b486871-74d4-49dd-81b0-9ee6cb541aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731100904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.731100904
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.4008717914
Short name T619
Test name
Test status
Simulation time 43043081118 ps
CPU time 29.19 seconds
Started May 26 02:32:35 PM PDT 24
Finished May 26 02:33:05 PM PDT 24
Peak memory 201636 kb
Host smart-0f33ff76-dff9-4456-935e-d1f81a16a11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008717914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.4008717914
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1193665971
Short name T599
Test name
Test status
Simulation time 4896737084 ps
CPU time 3.53 seconds
Started May 26 02:32:33 PM PDT 24
Finished May 26 02:32:37 PM PDT 24
Peak memory 201564 kb
Host smart-01a6cf5c-d229-4404-8814-c9f72ffc1907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193665971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1193665971
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3214560854
Short name T525
Test name
Test status
Simulation time 6100570557 ps
CPU time 14.84 seconds
Started May 26 02:32:32 PM PDT 24
Finished May 26 02:32:48 PM PDT 24
Peak memory 201652 kb
Host smart-c47bde17-da92-4aba-8572-aaea66030a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214560854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3214560854
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2121334450
Short name T334
Test name
Test status
Simulation time 297653921352 ps
CPU time 569.9 seconds
Started May 26 02:32:31 PM PDT 24
Finished May 26 02:42:02 PM PDT 24
Peak memory 210432 kb
Host smart-9232fe45-e482-41eb-8cca-b0c50a1dc724
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121334450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2121334450
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2203718413
Short name T19
Test name
Test status
Simulation time 95262704301 ps
CPU time 115.85 seconds
Started May 26 02:32:32 PM PDT 24
Finished May 26 02:34:28 PM PDT 24
Peak memory 210460 kb
Host smart-02c9a1c5-9447-4070-aa78-c4c8de02b0db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203718413 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2203718413
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2272270396
Short name T400
Test name
Test status
Simulation time 477676980 ps
CPU time 0.88 seconds
Started May 26 02:32:40 PM PDT 24
Finished May 26 02:32:42 PM PDT 24
Peak memory 201548 kb
Host smart-c134f85e-64a2-41e8-997e-2edd7230247a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272270396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2272270396
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1355563239
Short name T621
Test name
Test status
Simulation time 332400214004 ps
CPU time 216.41 seconds
Started May 26 02:32:39 PM PDT 24
Finished May 26 02:36:16 PM PDT 24
Peak memory 201936 kb
Host smart-8ffe2d3b-1cbb-4ad5-a743-97c77d19706f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355563239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1355563239
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1523563729
Short name T329
Test name
Test status
Simulation time 172412679762 ps
CPU time 396.48 seconds
Started May 26 02:32:41 PM PDT 24
Finished May 26 02:39:19 PM PDT 24
Peak memory 201828 kb
Host smart-f113022f-c223-4d20-bb2b-1b8e0a7eb48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523563729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1523563729
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.4139293799
Short name T693
Test name
Test status
Simulation time 501984572754 ps
CPU time 302.05 seconds
Started May 26 02:32:33 PM PDT 24
Finished May 26 02:37:36 PM PDT 24
Peak memory 202020 kb
Host smart-5ef8fc76-90ea-426b-ad2e-efa48df066ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139293799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.4139293799
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2022848302
Short name T665
Test name
Test status
Simulation time 164788719915 ps
CPU time 316.97 seconds
Started May 26 02:32:32 PM PDT 24
Finished May 26 02:37:50 PM PDT 24
Peak memory 201964 kb
Host smart-0ebddf0e-064d-43f3-9ccb-3830311c096f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022848302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2022848302
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2682492186
Short name T713
Test name
Test status
Simulation time 160765095696 ps
CPU time 348.57 seconds
Started May 26 02:32:32 PM PDT 24
Finished May 26 02:38:21 PM PDT 24
Peak memory 201828 kb
Host smart-7cc9f189-aa55-425e-9ee0-d1af355c501d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682492186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2682492186
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1149576314
Short name T2
Test name
Test status
Simulation time 322753182751 ps
CPU time 202.26 seconds
Started May 26 02:32:32 PM PDT 24
Finished May 26 02:35:55 PM PDT 24
Peak memory 201772 kb
Host smart-213643da-defb-4d1d-82ff-57922d2ebde1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149576314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1149576314
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2499419553
Short name T300
Test name
Test status
Simulation time 623720671478 ps
CPU time 799.62 seconds
Started May 26 02:32:39 PM PDT 24
Finished May 26 02:46:00 PM PDT 24
Peak memory 201956 kb
Host smart-dc7394c7-e75b-4cb7-a432-f0943d9af402
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499419553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2499419553
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.364032099
Short name T656
Test name
Test status
Simulation time 590419389670 ps
CPU time 1040.05 seconds
Started May 26 02:32:40 PM PDT 24
Finished May 26 02:50:01 PM PDT 24
Peak memory 201844 kb
Host smart-56224019-fbbf-46c4-adfe-f3c64d8de2c6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364032099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.364032099
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3900646859
Short name T707
Test name
Test status
Simulation time 84701653242 ps
CPU time 431.44 seconds
Started May 26 02:32:38 PM PDT 24
Finished May 26 02:39:51 PM PDT 24
Peak memory 202176 kb
Host smart-ffb92e46-0d67-48ad-91aa-e185371ac767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900646859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3900646859
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1324298891
Short name T555
Test name
Test status
Simulation time 31365255408 ps
CPU time 77.19 seconds
Started May 26 02:32:40 PM PDT 24
Finished May 26 02:33:58 PM PDT 24
Peak memory 201656 kb
Host smart-7606b20e-cf04-40ba-8be4-e3a2830f3996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324298891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1324298891
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3271946623
Short name T94
Test name
Test status
Simulation time 3489204721 ps
CPU time 4.96 seconds
Started May 26 02:32:41 PM PDT 24
Finished May 26 02:32:47 PM PDT 24
Peak memory 201544 kb
Host smart-1eb0fd98-6637-4535-a272-09364e84183d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271946623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3271946623
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1711342635
Short name T748
Test name
Test status
Simulation time 5700064340 ps
CPU time 9.25 seconds
Started May 26 02:32:31 PM PDT 24
Finished May 26 02:32:41 PM PDT 24
Peak memory 201672 kb
Host smart-61dc6d00-629b-4d52-9951-814cf8f1796c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711342635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1711342635
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.2287304684
Short name T376
Test name
Test status
Simulation time 51740945236 ps
CPU time 64.58 seconds
Started May 26 02:32:39 PM PDT 24
Finished May 26 02:33:45 PM PDT 24
Peak memory 201644 kb
Host smart-1ece3129-8997-4510-b211-17a9ba4babc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287304684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.2287304684
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3176530738
Short name T108
Test name
Test status
Simulation time 239580309771 ps
CPU time 198.35 seconds
Started May 26 02:32:39 PM PDT 24
Finished May 26 02:35:58 PM PDT 24
Peak memory 210520 kb
Host smart-e35e0d71-e1d7-4cac-a3e7-b0750c7d34e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176530738 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3176530738
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.957983675
Short name T355
Test name
Test status
Simulation time 401911700 ps
CPU time 0.86 seconds
Started May 26 02:31:33 PM PDT 24
Finished May 26 02:31:35 PM PDT 24
Peak memory 201548 kb
Host smart-0bf9aded-6a3f-4acf-8295-6e3440493397
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957983675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.957983675
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3621711101
Short name T8
Test name
Test status
Simulation time 361572719058 ps
CPU time 197.54 seconds
Started May 26 02:31:31 PM PDT 24
Finished May 26 02:34:50 PM PDT 24
Peak memory 201828 kb
Host smart-e15967e2-54ac-4bc8-b084-7b9b497ef677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621711101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3621711101
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3128897797
Short name T595
Test name
Test status
Simulation time 321399253672 ps
CPU time 190.31 seconds
Started May 26 02:31:31 PM PDT 24
Finished May 26 02:34:42 PM PDT 24
Peak memory 201868 kb
Host smart-3153d392-03e4-4cb9-869b-5b85e406bbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128897797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3128897797
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3559718962
Short name T741
Test name
Test status
Simulation time 325788128204 ps
CPU time 211.46 seconds
Started May 26 02:31:29 PM PDT 24
Finished May 26 02:35:01 PM PDT 24
Peak memory 201860 kb
Host smart-67949d21-64ec-4340-9a70-43be474ac534
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559718962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3559718962
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3254445841
Short name T775
Test name
Test status
Simulation time 325234050073 ps
CPU time 748.12 seconds
Started May 26 02:31:31 PM PDT 24
Finished May 26 02:43:59 PM PDT 24
Peak memory 201884 kb
Host smart-5c3b73e7-ba34-4b16-95b0-8f6187b3e2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254445841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3254445841
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3741379254
Short name T416
Test name
Test status
Simulation time 495470227347 ps
CPU time 289.06 seconds
Started May 26 02:31:39 PM PDT 24
Finished May 26 02:36:29 PM PDT 24
Peak memory 201840 kb
Host smart-18cc7587-df0d-4b00-a287-83aea77ab4f7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741379254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3741379254
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3013285297
Short name T175
Test name
Test status
Simulation time 601463371470 ps
CPU time 364.96 seconds
Started May 26 02:31:38 PM PDT 24
Finished May 26 02:37:43 PM PDT 24
Peak memory 201932 kb
Host smart-e39f1b43-c37a-41dc-a63b-23bddea91cc1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013285297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3013285297
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.4038358050
Short name T788
Test name
Test status
Simulation time 610452986151 ps
CPU time 104.03 seconds
Started May 26 02:31:33 PM PDT 24
Finished May 26 02:33:18 PM PDT 24
Peak memory 201880 kb
Host smart-8b95c175-8cd5-4a30-adc4-e38fd452aeae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038358050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.4038358050
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2417649643
Short name T538
Test name
Test status
Simulation time 108921068062 ps
CPU time 382.13 seconds
Started May 26 02:31:46 PM PDT 24
Finished May 26 02:38:08 PM PDT 24
Peak memory 202164 kb
Host smart-8863fe04-07c6-4fc1-89a7-35d5dc6aa15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417649643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2417649643
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2752974375
Short name T374
Test name
Test status
Simulation time 29777893636 ps
CPU time 15.52 seconds
Started May 26 02:31:32 PM PDT 24
Finished May 26 02:31:48 PM PDT 24
Peak memory 201816 kb
Host smart-48f46f74-2584-4852-8ab1-96cb1b4be120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752974375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2752974375
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3595114712
Short name T753
Test name
Test status
Simulation time 4681321518 ps
CPU time 3.23 seconds
Started May 26 02:31:46 PM PDT 24
Finished May 26 02:31:50 PM PDT 24
Peak memory 201676 kb
Host smart-12c9e945-6e00-48dd-b9af-d60d12ea5465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595114712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3595114712
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1347626411
Short name T78
Test name
Test status
Simulation time 8041671719 ps
CPU time 2.96 seconds
Started May 26 02:31:37 PM PDT 24
Finished May 26 02:31:41 PM PDT 24
Peak memory 217408 kb
Host smart-250cd8ff-8ee0-4d16-a16f-0b72ba2ff58b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347626411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1347626411
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3765654103
Short name T710
Test name
Test status
Simulation time 5899934962 ps
CPU time 3.94 seconds
Started May 26 02:31:47 PM PDT 24
Finished May 26 02:31:51 PM PDT 24
Peak memory 201688 kb
Host smart-064be863-e25e-44fa-9ca5-ed03902f9aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765654103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3765654103
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3181445512
Short name T188
Test name
Test status
Simulation time 241226584890 ps
CPU time 72.06 seconds
Started May 26 02:31:46 PM PDT 24
Finished May 26 02:32:59 PM PDT 24
Peak memory 201912 kb
Host smart-eaaf6e9b-aa45-4c15-83af-1395f8455745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181445512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3181445512
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3920971792
Short name T21
Test name
Test status
Simulation time 378924913969 ps
CPU time 80.54 seconds
Started May 26 02:31:34 PM PDT 24
Finished May 26 02:32:56 PM PDT 24
Peak memory 210140 kb
Host smart-6cb6d098-7f6e-4b94-a2e0-1886e1fb156e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920971792 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3920971792
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1106272538
Short name T571
Test name
Test status
Simulation time 443479139 ps
CPU time 1.09 seconds
Started May 26 02:32:48 PM PDT 24
Finished May 26 02:32:49 PM PDT 24
Peak memory 201564 kb
Host smart-9248b742-272d-4fcd-9427-a3094933e091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106272538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1106272538
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.876565995
Short name T332
Test name
Test status
Simulation time 154814021748 ps
CPU time 89.68 seconds
Started May 26 02:32:41 PM PDT 24
Finished May 26 02:34:12 PM PDT 24
Peak memory 202060 kb
Host smart-e062fa89-ccc2-47d7-8863-34c645557508
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876565995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gati
ng.876565995
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2300994349
Short name T107
Test name
Test status
Simulation time 357298527435 ps
CPU time 287.37 seconds
Started May 26 02:32:41 PM PDT 24
Finished May 26 02:37:29 PM PDT 24
Peak memory 201824 kb
Host smart-0a38749e-db2b-4406-b227-0b9a086dddb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300994349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2300994349
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.867992086
Short name T370
Test name
Test status
Simulation time 326906655159 ps
CPU time 52.67 seconds
Started May 26 02:32:40 PM PDT 24
Finished May 26 02:33:34 PM PDT 24
Peak memory 201816 kb
Host smart-570345a0-8033-4182-bf10-54dd3d7623c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=867992086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.867992086
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1575644561
Short name T109
Test name
Test status
Simulation time 492697193200 ps
CPU time 546.49 seconds
Started May 26 02:32:41 PM PDT 24
Finished May 26 02:41:49 PM PDT 24
Peak memory 201880 kb
Host smart-e10ba537-4af2-4ec3-a112-07de8b0359d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575644561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1575644561
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.614081955
Short name T436
Test name
Test status
Simulation time 490302985421 ps
CPU time 1106.69 seconds
Started May 26 02:32:40 PM PDT 24
Finished May 26 02:51:08 PM PDT 24
Peak memory 201864 kb
Host smart-fa8d3dd1-3532-455a-8d57-3003da2c7e93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=614081955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixe
d.614081955
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3435976426
Short name T654
Test name
Test status
Simulation time 592379631438 ps
CPU time 1263.44 seconds
Started May 26 02:32:39 PM PDT 24
Finished May 26 02:53:43 PM PDT 24
Peak memory 201860 kb
Host smart-7d9c2a65-a779-409e-b4b3-0f13e9a161f4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435976426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3435976426
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.293896157
Short name T211
Test name
Test status
Simulation time 110777835053 ps
CPU time 368.74 seconds
Started May 26 02:32:40 PM PDT 24
Finished May 26 02:38:49 PM PDT 24
Peak memory 202180 kb
Host smart-dea5dbf4-69f9-4cc0-8771-6ac1363ed903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293896157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.293896157
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2582501681
Short name T567
Test name
Test status
Simulation time 26718536212 ps
CPU time 15.58 seconds
Started May 26 02:32:42 PM PDT 24
Finished May 26 02:32:58 PM PDT 24
Peak memory 201616 kb
Host smart-347284c8-3818-481d-885b-1dd1d0487655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582501681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2582501681
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1095563416
Short name T197
Test name
Test status
Simulation time 5063649682 ps
CPU time 2.71 seconds
Started May 26 02:32:39 PM PDT 24
Finished May 26 02:32:43 PM PDT 24
Peak memory 201672 kb
Host smart-76025cf4-f5d7-4d6f-8278-a25ce5396d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095563416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1095563416
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3075353142
Short name T738
Test name
Test status
Simulation time 5788016702 ps
CPU time 10.42 seconds
Started May 26 02:32:40 PM PDT 24
Finished May 26 02:32:51 PM PDT 24
Peak memory 201668 kb
Host smart-049bebaf-f420-41b7-8060-66b82b1f025c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075353142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3075353142
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3347008574
Short name T663
Test name
Test status
Simulation time 172244617772 ps
CPU time 153.62 seconds
Started May 26 02:32:40 PM PDT 24
Finished May 26 02:35:15 PM PDT 24
Peak memory 201864 kb
Host smart-c3393653-a37d-48c5-8c1f-8906426ec321
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347008574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3347008574
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2520654065
Short name T18
Test name
Test status
Simulation time 412728910667 ps
CPU time 429.17 seconds
Started May 26 02:32:39 PM PDT 24
Finished May 26 02:39:49 PM PDT 24
Peak memory 210456 kb
Host smart-cfd245f2-fc04-4e0b-9921-e40e4c626c4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520654065 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2520654065
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3584331185
Short name T361
Test name
Test status
Simulation time 294200147 ps
CPU time 1.36 seconds
Started May 26 02:32:46 PM PDT 24
Finished May 26 02:32:48 PM PDT 24
Peak memory 201548 kb
Host smart-9198e898-846d-48c6-a415-87512830fc1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584331185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3584331185
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2115486354
Short name T487
Test name
Test status
Simulation time 360969580144 ps
CPU time 750.77 seconds
Started May 26 02:32:47 PM PDT 24
Finished May 26 02:45:18 PM PDT 24
Peak memory 201844 kb
Host smart-effd9d6e-d181-47f2-a651-8294cab84069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115486354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2115486354
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1741598527
Short name T592
Test name
Test status
Simulation time 336158300814 ps
CPU time 790.78 seconds
Started May 26 02:32:50 PM PDT 24
Finished May 26 02:46:01 PM PDT 24
Peak memory 201856 kb
Host smart-3590b7c2-b175-4624-ba6d-598fe7d51428
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741598527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1741598527
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2944669038
Short name T458
Test name
Test status
Simulation time 166633722167 ps
CPU time 203.98 seconds
Started May 26 02:32:47 PM PDT 24
Finished May 26 02:36:11 PM PDT 24
Peak memory 201916 kb
Host smart-05da3cf7-0516-46ed-853a-08a2af49ae21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944669038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2944669038
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3329403147
Short name T708
Test name
Test status
Simulation time 325736015064 ps
CPU time 768.12 seconds
Started May 26 02:32:48 PM PDT 24
Finished May 26 02:45:37 PM PDT 24
Peak memory 201832 kb
Host smart-e6ff35a3-94db-4b9f-93f1-c2322e49f76c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329403147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3329403147
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.326764868
Short name T500
Test name
Test status
Simulation time 370855551170 ps
CPU time 912.84 seconds
Started May 26 02:32:47 PM PDT 24
Finished May 26 02:48:01 PM PDT 24
Peak memory 201928 kb
Host smart-136f9fd2-d85f-4789-a0f3-cee6534cb15c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326764868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.326764868
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.4200968077
Short name T511
Test name
Test status
Simulation time 595243366403 ps
CPU time 686.5 seconds
Started May 26 02:32:47 PM PDT 24
Finished May 26 02:44:14 PM PDT 24
Peak memory 201852 kb
Host smart-a60eda35-8c4a-425c-b7d6-df5123126b7e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200968077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.4200968077
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.4109940352
Short name T727
Test name
Test status
Simulation time 93731477350 ps
CPU time 505.75 seconds
Started May 26 02:32:47 PM PDT 24
Finished May 26 02:41:14 PM PDT 24
Peak memory 202200 kb
Host smart-f06f8e12-1629-4d5e-9371-5820c8242198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109940352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.4109940352
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1788619919
Short name T746
Test name
Test status
Simulation time 28130754757 ps
CPU time 14.94 seconds
Started May 26 02:32:49 PM PDT 24
Finished May 26 02:33:04 PM PDT 24
Peak memory 201684 kb
Host smart-4c53b8dd-9536-4d84-8916-ada98aebfc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788619919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1788619919
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1712644256
Short name T563
Test name
Test status
Simulation time 3326294062 ps
CPU time 4.58 seconds
Started May 26 02:32:50 PM PDT 24
Finished May 26 02:32:55 PM PDT 24
Peak memory 201628 kb
Host smart-ca5429cf-4117-408f-b8b2-f66aa3cfdd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712644256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1712644256
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.917463609
Short name T378
Test name
Test status
Simulation time 5555532062 ps
CPU time 13.65 seconds
Started May 26 02:32:48 PM PDT 24
Finished May 26 02:33:02 PM PDT 24
Peak memory 201656 kb
Host smart-c5861685-a6bb-4af7-94c6-6f1cde80eeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917463609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.917463609
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1279395830
Short name T634
Test name
Test status
Simulation time 255294773900 ps
CPU time 854.2 seconds
Started May 26 02:32:47 PM PDT 24
Finished May 26 02:47:02 PM PDT 24
Peak memory 210372 kb
Host smart-4fb0b5fe-ebd6-4066-852b-2e868b22f2ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279395830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1279395830
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3594683974
Short name T736
Test name
Test status
Simulation time 19104597317 ps
CPU time 65.33 seconds
Started May 26 02:32:49 PM PDT 24
Finished May 26 02:33:55 PM PDT 24
Peak memory 210564 kb
Host smart-b1e53d51-6321-436d-9578-c86091d53016
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594683974 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3594683974
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3925094032
Short name T196
Test name
Test status
Simulation time 455309731 ps
CPU time 0.88 seconds
Started May 26 02:33:02 PM PDT 24
Finished May 26 02:33:04 PM PDT 24
Peak memory 201456 kb
Host smart-4ad09012-0c8e-44dd-b8e9-bb938cb89ad9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925094032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3925094032
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1509222630
Short name T261
Test name
Test status
Simulation time 545538845711 ps
CPU time 340.55 seconds
Started May 26 02:32:54 PM PDT 24
Finished May 26 02:38:35 PM PDT 24
Peak memory 201916 kb
Host smart-69710ec0-7af8-4832-9269-48ed13b651f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509222630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1509222630
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.225801339
Short name T223
Test name
Test status
Simulation time 492018760245 ps
CPU time 1251.79 seconds
Started May 26 02:33:02 PM PDT 24
Finished May 26 02:53:55 PM PDT 24
Peak memory 201804 kb
Host smart-4d258e36-1830-4ad2-8c10-102f22a457dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225801339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.225801339
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2531276222
Short name T704
Test name
Test status
Simulation time 163406074542 ps
CPU time 361.71 seconds
Started May 26 02:32:55 PM PDT 24
Finished May 26 02:38:57 PM PDT 24
Peak memory 201812 kb
Host smart-3fa959d3-a2f4-44c1-b213-7092936557d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531276222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2531276222
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.4055718220
Short name T189
Test name
Test status
Simulation time 334412658725 ps
CPU time 198.32 seconds
Started May 26 02:32:54 PM PDT 24
Finished May 26 02:36:13 PM PDT 24
Peak memory 201832 kb
Host smart-bdd1975f-39cd-45e3-b7b7-cc2bc38b6b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055718220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.4055718220
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1385401528
Short name T480
Test name
Test status
Simulation time 325379092394 ps
CPU time 202.03 seconds
Started May 26 02:32:56 PM PDT 24
Finished May 26 02:36:19 PM PDT 24
Peak memory 201800 kb
Host smart-33365a7f-10db-4921-a74c-2dfea9d41200
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385401528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1385401528
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2026993545
Short name T290
Test name
Test status
Simulation time 344969219951 ps
CPU time 803.23 seconds
Started May 26 02:33:00 PM PDT 24
Finished May 26 02:46:24 PM PDT 24
Peak memory 201816 kb
Host smart-bc683fde-2bc9-4f94-8995-9d89ae70a8ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026993545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2026993545
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.416746099
Short name T470
Test name
Test status
Simulation time 221002270762 ps
CPU time 131.36 seconds
Started May 26 02:32:55 PM PDT 24
Finished May 26 02:35:07 PM PDT 24
Peak memory 201856 kb
Host smart-2e3a0927-7568-4535-b3d3-7bc5ff25bd87
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416746099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.416746099
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.199617148
Short name T408
Test name
Test status
Simulation time 90569232766 ps
CPU time 324 seconds
Started May 26 02:33:00 PM PDT 24
Finished May 26 02:38:24 PM PDT 24
Peak memory 202172 kb
Host smart-634b7bba-77c6-4d0c-b510-c46da1abc9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199617148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.199617148
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.2465551662
Short name T89
Test name
Test status
Simulation time 41359014919 ps
CPU time 25.92 seconds
Started May 26 02:32:55 PM PDT 24
Finished May 26 02:33:22 PM PDT 24
Peak memory 201672 kb
Host smart-cf5f3680-cee9-4734-9f0f-3365b29e73f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465551662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.2465551662
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1246296913
Short name T365
Test name
Test status
Simulation time 3324606159 ps
CPU time 2.14 seconds
Started May 26 02:32:54 PM PDT 24
Finished May 26 02:32:56 PM PDT 24
Peak memory 201600 kb
Host smart-81e54795-b2f6-4f6c-962b-75f786d50d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246296913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1246296913
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2523517646
Short name T598
Test name
Test status
Simulation time 5735775784 ps
CPU time 4.12 seconds
Started May 26 02:32:55 PM PDT 24
Finished May 26 02:32:59 PM PDT 24
Peak memory 201696 kb
Host smart-c8b47bdc-81a8-4a94-a03c-4434fa530cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523517646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2523517646
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2908930881
Short name T83
Test name
Test status
Simulation time 427468984 ps
CPU time 1.66 seconds
Started May 26 02:33:13 PM PDT 24
Finished May 26 02:33:15 PM PDT 24
Peak memory 201564 kb
Host smart-8eba9408-950d-49de-967d-18a21ec69987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908930881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2908930881
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3270337248
Short name T200
Test name
Test status
Simulation time 162412287345 ps
CPU time 248.47 seconds
Started May 26 02:33:04 PM PDT 24
Finished May 26 02:37:14 PM PDT 24
Peak memory 201836 kb
Host smart-bfec838f-a531-48aa-be5c-5901bdb4cf2b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270337248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3270337248
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.323920945
Short name T740
Test name
Test status
Simulation time 513938350356 ps
CPU time 955.29 seconds
Started May 26 02:33:06 PM PDT 24
Finished May 26 02:49:02 PM PDT 24
Peak memory 201856 kb
Host smart-f72b1ec7-2487-4237-b008-1f0401bf441e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323920945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.323920945
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3180107859
Short name T176
Test name
Test status
Simulation time 335673922282 ps
CPU time 199.8 seconds
Started May 26 02:33:03 PM PDT 24
Finished May 26 02:36:24 PM PDT 24
Peak memory 201796 kb
Host smart-66f0140b-69c0-42f4-8882-104c86631229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180107859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3180107859
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.974823994
Short name T106
Test name
Test status
Simulation time 498310586827 ps
CPU time 1196.96 seconds
Started May 26 02:33:06 PM PDT 24
Finished May 26 02:53:04 PM PDT 24
Peak memory 201840 kb
Host smart-06ece197-28fd-4752-8591-b934d51e040b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=974823994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.974823994
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.972067487
Short name T575
Test name
Test status
Simulation time 500236989358 ps
CPU time 1093.21 seconds
Started May 26 02:33:03 PM PDT 24
Finished May 26 02:51:17 PM PDT 24
Peak memory 201856 kb
Host smart-0075ee48-ff3b-4815-8034-edf6e5eb732a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972067487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.972067487
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3962478477
Short name T709
Test name
Test status
Simulation time 163942482028 ps
CPU time 70.79 seconds
Started May 26 02:33:04 PM PDT 24
Finished May 26 02:34:16 PM PDT 24
Peak memory 201792 kb
Host smart-5c2dea43-0571-4a0f-844c-8e5bbfc7b1c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962478477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3962478477
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.316440692
Short name T314
Test name
Test status
Simulation time 171004425914 ps
CPU time 190.83 seconds
Started May 26 02:33:03 PM PDT 24
Finished May 26 02:36:15 PM PDT 24
Peak memory 201888 kb
Host smart-cb416caa-ccce-4dc6-87ea-d206f93e7b19
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316440692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.316440692
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3586406790
Short name T558
Test name
Test status
Simulation time 616239847666 ps
CPU time 1500.64 seconds
Started May 26 02:33:02 PM PDT 24
Finished May 26 02:58:04 PM PDT 24
Peak memory 201828 kb
Host smart-b7ef7386-ee47-4b10-a42d-1bf6145f5066
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586406790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3586406790
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.210854034
Short name T346
Test name
Test status
Simulation time 110462711146 ps
CPU time 474 seconds
Started May 26 02:33:11 PM PDT 24
Finished May 26 02:41:06 PM PDT 24
Peak memory 202136 kb
Host smart-da9bbf27-54cd-4392-bb6d-07c6eb006df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210854034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.210854034
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.417572581
Short name T798
Test name
Test status
Simulation time 38829362087 ps
CPU time 22.15 seconds
Started May 26 02:33:10 PM PDT 24
Finished May 26 02:33:33 PM PDT 24
Peak memory 201676 kb
Host smart-5da1eaa1-dea6-49fc-8977-02604a2d9d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417572581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.417572581
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3194199776
Short name T111
Test name
Test status
Simulation time 3457805765 ps
CPU time 8.83 seconds
Started May 26 02:33:12 PM PDT 24
Finished May 26 02:33:21 PM PDT 24
Peak memory 201592 kb
Host smart-004f0c02-9b75-4fc2-bd90-b1f3edbac236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194199776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3194199776
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2852809766
Short name T79
Test name
Test status
Simulation time 5986245581 ps
CPU time 14.67 seconds
Started May 26 02:33:02 PM PDT 24
Finished May 26 02:33:17 PM PDT 24
Peak memory 201664 kb
Host smart-1a3cef7a-17e2-46a1-a171-0c6872dd2583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852809766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2852809766
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3032604524
Short name T793
Test name
Test status
Simulation time 198035348854 ps
CPU time 584.9 seconds
Started May 26 02:33:11 PM PDT 24
Finished May 26 02:42:57 PM PDT 24
Peak memory 202212 kb
Host smart-b3fc8d46-f565-4c2d-9bdc-a4bd61a6880d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032604524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3032604524
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.678841324
Short name T273
Test name
Test status
Simulation time 138284424477 ps
CPU time 191.28 seconds
Started May 26 02:33:13 PM PDT 24
Finished May 26 02:36:25 PM PDT 24
Peak memory 212296 kb
Host smart-7c0df977-565b-4965-99b5-8e6df142a152
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678841324 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.678841324
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.540170948
Short name T447
Test name
Test status
Simulation time 374230163 ps
CPU time 1.03 seconds
Started May 26 02:33:20 PM PDT 24
Finished May 26 02:33:21 PM PDT 24
Peak memory 201556 kb
Host smart-34daa434-7c98-4616-9448-e37a9c270445
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540170948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.540170948
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2679333578
Short name T647
Test name
Test status
Simulation time 169983796106 ps
CPU time 254.71 seconds
Started May 26 02:33:12 PM PDT 24
Finished May 26 02:37:27 PM PDT 24
Peak memory 201884 kb
Host smart-181ba07c-4dc2-4b4a-b3b4-98a0de587a81
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679333578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2679333578
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3195783359
Short name T669
Test name
Test status
Simulation time 491864180180 ps
CPU time 558.77 seconds
Started May 26 02:33:13 PM PDT 24
Finished May 26 02:42:32 PM PDT 24
Peak memory 201876 kb
Host smart-cb48c2be-b00f-4f63-8879-92e0f38f67d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195783359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3195783359
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.432748686
Short name T42
Test name
Test status
Simulation time 322083620104 ps
CPU time 675.67 seconds
Started May 26 02:33:11 PM PDT 24
Finished May 26 02:44:27 PM PDT 24
Peak memory 201776 kb
Host smart-eb3a210e-101b-4838-9862-08403620ddbd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=432748686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.432748686
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2121255613
Short name T228
Test name
Test status
Simulation time 489327998447 ps
CPU time 1118.89 seconds
Started May 26 02:33:11 PM PDT 24
Finished May 26 02:51:51 PM PDT 24
Peak memory 201816 kb
Host smart-62f2e611-167f-413c-856d-ebe7bbd769e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121255613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2121255613
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1994278126
Short name T658
Test name
Test status
Simulation time 327496780462 ps
CPU time 195.51 seconds
Started May 26 02:33:13 PM PDT 24
Finished May 26 02:36:29 PM PDT 24
Peak memory 201784 kb
Host smart-cc185d48-6a2d-4fc2-90db-58cdf7c29c4b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994278126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1994278126
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.4209397298
Short name T394
Test name
Test status
Simulation time 206606409457 ps
CPU time 128.66 seconds
Started May 26 02:33:11 PM PDT 24
Finished May 26 02:35:21 PM PDT 24
Peak memory 201748 kb
Host smart-1df87903-d207-48eb-a255-c734d012593d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209397298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.4209397298
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2800479467
Short name T629
Test name
Test status
Simulation time 89105156759 ps
CPU time 399 seconds
Started May 26 02:33:18 PM PDT 24
Finished May 26 02:39:57 PM PDT 24
Peak memory 202240 kb
Host smart-73d6b677-535a-4bbd-80aa-9433a18e57e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800479467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2800479467
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2984405891
Short name T521
Test name
Test status
Simulation time 37322368919 ps
CPU time 42.76 seconds
Started May 26 02:33:19 PM PDT 24
Finished May 26 02:34:03 PM PDT 24
Peak memory 201616 kb
Host smart-25d5ccfe-88ac-4b36-88df-385085cddc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984405891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2984405891
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.3775264125
Short name T453
Test name
Test status
Simulation time 2889866926 ps
CPU time 7.51 seconds
Started May 26 02:33:20 PM PDT 24
Finished May 26 02:33:28 PM PDT 24
Peak memory 201632 kb
Host smart-1f0a1f3c-a78c-4514-b95e-0eeaf405dd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775264125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.3775264125
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.878776417
Short name T467
Test name
Test status
Simulation time 5597148625 ps
CPU time 12.85 seconds
Started May 26 02:33:11 PM PDT 24
Finished May 26 02:33:25 PM PDT 24
Peak memory 201692 kb
Host smart-1e1f539d-3032-437f-93e8-9f8252c442f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878776417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.878776417
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1271642212
Short name T330
Test name
Test status
Simulation time 1717084858576 ps
CPU time 669.01 seconds
Started May 26 02:33:18 PM PDT 24
Finished May 26 02:44:28 PM PDT 24
Peak memory 210352 kb
Host smart-5ad18ed0-06db-4783-bc7f-de5dec571479
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271642212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1271642212
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3080490864
Short name T16
Test name
Test status
Simulation time 57415939029 ps
CPU time 94.08 seconds
Started May 26 02:33:21 PM PDT 24
Finished May 26 02:34:55 PM PDT 24
Peak memory 210548 kb
Host smart-12fedebe-523d-4d18-82db-e517a6b32f4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080490864 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3080490864
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3418592675
Short name T497
Test name
Test status
Simulation time 515507495 ps
CPU time 1.28 seconds
Started May 26 02:33:26 PM PDT 24
Finished May 26 02:33:28 PM PDT 24
Peak memory 201536 kb
Host smart-9c7510ee-76a0-4825-8edb-b875c0648019
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418592675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3418592675
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1262014292
Short name T703
Test name
Test status
Simulation time 339692007541 ps
CPU time 51.51 seconds
Started May 26 02:33:26 PM PDT 24
Finished May 26 02:34:18 PM PDT 24
Peak memory 201836 kb
Host smart-fd301ed8-8f39-4c68-82be-aa1c2cfa74df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262014292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1262014292
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3631734235
Short name T148
Test name
Test status
Simulation time 494026161432 ps
CPU time 1107.11 seconds
Started May 26 02:33:25 PM PDT 24
Finished May 26 02:51:53 PM PDT 24
Peak memory 201856 kb
Host smart-2b7a0928-f954-4f23-b409-8bee3960f42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631734235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3631734235
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.811381262
Short name T272
Test name
Test status
Simulation time 166029004544 ps
CPU time 195.13 seconds
Started May 26 02:33:17 PM PDT 24
Finished May 26 02:36:33 PM PDT 24
Peak memory 201804 kb
Host smart-8970f151-1209-4238-8005-0f15078937f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811381262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.811381262
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1081192105
Short name T673
Test name
Test status
Simulation time 166096472679 ps
CPU time 362.44 seconds
Started May 26 02:33:18 PM PDT 24
Finished May 26 02:39:22 PM PDT 24
Peak memory 201844 kb
Host smart-b2540f09-8e01-48c2-ab5c-8e07c0672832
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081192105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1081192105
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3281652096
Short name T556
Test name
Test status
Simulation time 486132750984 ps
CPU time 1163.7 seconds
Started May 26 02:33:20 PM PDT 24
Finished May 26 02:52:44 PM PDT 24
Peak memory 201920 kb
Host smart-8bf2c2b9-e8c5-4d3e-82fa-c9d7e845a760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281652096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3281652096
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.2603768259
Short name T164
Test name
Test status
Simulation time 488406908801 ps
CPU time 1179.91 seconds
Started May 26 02:33:19 PM PDT 24
Finished May 26 02:53:00 PM PDT 24
Peak memory 201832 kb
Host smart-75b3e8f2-dac7-42b1-9b0a-27afeefc81d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603768259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.2603768259
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.884693969
Short name T734
Test name
Test status
Simulation time 608505284508 ps
CPU time 674.85 seconds
Started May 26 02:33:18 PM PDT 24
Finished May 26 02:44:34 PM PDT 24
Peak memory 201848 kb
Host smart-e393ea8e-8361-4028-801f-e547ddee563c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884693969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.884693969
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2245900131
Short name T600
Test name
Test status
Simulation time 93147130487 ps
CPU time 455.41 seconds
Started May 26 02:33:28 PM PDT 24
Finished May 26 02:41:04 PM PDT 24
Peak memory 202224 kb
Host smart-2777b879-79be-4a63-b415-4baaecb63623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245900131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2245900131
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1127809686
Short name T7
Test name
Test status
Simulation time 43931963557 ps
CPU time 94.1 seconds
Started May 26 02:33:27 PM PDT 24
Finished May 26 02:35:01 PM PDT 24
Peak memory 201640 kb
Host smart-cca9d7f0-c337-4c0b-b233-170b1079db36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127809686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1127809686
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1963817386
Short name T687
Test name
Test status
Simulation time 4548472030 ps
CPU time 1.37 seconds
Started May 26 02:33:28 PM PDT 24
Finished May 26 02:33:30 PM PDT 24
Peak memory 201604 kb
Host smart-5b8d8e2c-250a-43e3-a045-eaee6857d732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963817386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1963817386
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1366793895
Short name T409
Test name
Test status
Simulation time 5863429859 ps
CPU time 7.95 seconds
Started May 26 02:33:19 PM PDT 24
Finished May 26 02:33:28 PM PDT 24
Peak memory 201680 kb
Host smart-58ec225e-5c8f-451e-acc4-900f66b80a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366793895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1366793895
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1094498561
Short name T725
Test name
Test status
Simulation time 3885243125678 ps
CPU time 949.33 seconds
Started May 26 02:33:26 PM PDT 24
Finished May 26 02:49:16 PM PDT 24
Peak memory 210432 kb
Host smart-6a0745af-e04d-4a7a-aff0-a79de3bcdd43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094498561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1094498561
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.101595877
Short name T227
Test name
Test status
Simulation time 138272680761 ps
CPU time 124.36 seconds
Started May 26 02:33:27 PM PDT 24
Finished May 26 02:35:32 PM PDT 24
Peak memory 210184 kb
Host smart-faf61a16-5242-4ff3-96a5-54501086d1e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101595877 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.101595877
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1975714175
Short name T363
Test name
Test status
Simulation time 386859193 ps
CPU time 1.53 seconds
Started May 26 02:33:36 PM PDT 24
Finished May 26 02:33:38 PM PDT 24
Peak memory 201568 kb
Host smart-f34890e9-2e3d-4e4a-a9c5-a5e45307dc1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975714175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1975714175
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1729011516
Short name T640
Test name
Test status
Simulation time 165820916580 ps
CPU time 204.51 seconds
Started May 26 02:33:25 PM PDT 24
Finished May 26 02:36:50 PM PDT 24
Peak memory 201860 kb
Host smart-4dcc0043-631c-467f-a4b9-d38903565de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729011516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1729011516
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3001948490
Short name T747
Test name
Test status
Simulation time 494954400254 ps
CPU time 613.13 seconds
Started May 26 02:33:29 PM PDT 24
Finished May 26 02:43:42 PM PDT 24
Peak memory 201856 kb
Host smart-32223ea0-db98-4b67-9d2e-c67753350c95
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001948490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3001948490
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1000330592
Short name T515
Test name
Test status
Simulation time 334750101257 ps
CPU time 763.29 seconds
Started May 26 02:33:26 PM PDT 24
Finished May 26 02:46:10 PM PDT 24
Peak memory 201824 kb
Host smart-9669141d-b6a7-49ab-a113-c0e78bbe5245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000330592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1000330592
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2624049076
Short name T523
Test name
Test status
Simulation time 495266786302 ps
CPU time 548.11 seconds
Started May 26 02:33:25 PM PDT 24
Finished May 26 02:42:33 PM PDT 24
Peak memory 201840 kb
Host smart-03315d46-022e-4e90-a9bb-2562af4679d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624049076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2624049076
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2910890484
Short name T152
Test name
Test status
Simulation time 351785328023 ps
CPU time 825.29 seconds
Started May 26 02:33:25 PM PDT 24
Finished May 26 02:47:11 PM PDT 24
Peak memory 201920 kb
Host smart-915b8f0d-3ad9-490b-8f9f-9b0c25874f5c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910890484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2910890484
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3182105923
Short name T169
Test name
Test status
Simulation time 618206694398 ps
CPU time 491.12 seconds
Started May 26 02:33:35 PM PDT 24
Finished May 26 02:41:46 PM PDT 24
Peak memory 201848 kb
Host smart-c415b3d1-bdba-4233-b558-3265e3797922
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182105923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3182105923
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3650031712
Short name T208
Test name
Test status
Simulation time 130834192003 ps
CPU time 682.72 seconds
Started May 26 02:33:37 PM PDT 24
Finished May 26 02:45:00 PM PDT 24
Peak memory 202148 kb
Host smart-c7f9ee06-f775-4235-85c9-7d73cb36f0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650031712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3650031712
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1683395968
Short name T580
Test name
Test status
Simulation time 32779307454 ps
CPU time 21.41 seconds
Started May 26 02:33:35 PM PDT 24
Finished May 26 02:33:57 PM PDT 24
Peak memory 201652 kb
Host smart-6e1e376b-5761-478c-9e3d-451fb48325a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683395968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1683395968
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3782273514
Short name T393
Test name
Test status
Simulation time 5547823398 ps
CPU time 14.75 seconds
Started May 26 02:33:35 PM PDT 24
Finished May 26 02:33:50 PM PDT 24
Peak memory 201632 kb
Host smart-ec5c4fb8-44f9-4f65-afd2-e0d483fe1882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782273514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3782273514
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2255162109
Short name T645
Test name
Test status
Simulation time 5898724258 ps
CPU time 7.73 seconds
Started May 26 02:33:27 PM PDT 24
Finished May 26 02:33:35 PM PDT 24
Peak memory 201668 kb
Host smart-f70c0140-ac5d-43ba-9c9c-d64df335209b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255162109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2255162109
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1143219024
Short name T396
Test name
Test status
Simulation time 168444346074 ps
CPU time 80.01 seconds
Started May 26 02:33:34 PM PDT 24
Finished May 26 02:34:55 PM PDT 24
Peak memory 201932 kb
Host smart-4caed326-2651-4ce0-bcff-95d86817ee72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143219024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1143219024
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3273645930
Short name T610
Test name
Test status
Simulation time 143790136477 ps
CPU time 189.83 seconds
Started May 26 02:33:36 PM PDT 24
Finished May 26 02:36:46 PM PDT 24
Peak memory 210440 kb
Host smart-8bc26b47-12aa-49dc-a82f-3232945e89b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273645930 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3273645930
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.4076454489
Short name T432
Test name
Test status
Simulation time 329664708 ps
CPU time 0.99 seconds
Started May 26 02:33:41 PM PDT 24
Finished May 26 02:33:43 PM PDT 24
Peak memory 201548 kb
Host smart-dc427a96-85e0-44d6-b190-04e716623c19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076454489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.4076454489
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1666853564
Short name T310
Test name
Test status
Simulation time 162449333453 ps
CPU time 98.87 seconds
Started May 26 02:33:42 PM PDT 24
Finished May 26 02:35:21 PM PDT 24
Peak memory 201932 kb
Host smart-7f2486a8-498d-4e46-b88e-64859d54971a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666853564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1666853564
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3450712877
Short name T82
Test name
Test status
Simulation time 163578652405 ps
CPU time 391.5 seconds
Started May 26 02:34:10 PM PDT 24
Finished May 26 02:40:42 PM PDT 24
Peak memory 201792 kb
Host smart-a5c6aa22-3a42-42ad-85cf-85c526eb2681
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450712877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3450712877
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.4251230933
Short name T6
Test name
Test status
Simulation time 323214711596 ps
CPU time 185.2 seconds
Started May 26 02:33:35 PM PDT 24
Finished May 26 02:36:41 PM PDT 24
Peak memory 201932 kb
Host smart-ee254710-044c-43e7-92be-76c7171da791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251230933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.4251230933
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1664584861
Short name T419
Test name
Test status
Simulation time 490964203407 ps
CPU time 366.59 seconds
Started May 26 02:33:36 PM PDT 24
Finished May 26 02:39:43 PM PDT 24
Peak memory 201808 kb
Host smart-d058edb0-20b8-4622-b971-9b7162bc6392
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664584861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1664584861
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2034584341
Short name T780
Test name
Test status
Simulation time 195144987328 ps
CPU time 461.84 seconds
Started May 26 02:33:42 PM PDT 24
Finished May 26 02:41:24 PM PDT 24
Peak memory 201948 kb
Host smart-cd4606ef-5bff-4263-8550-592db9a59379
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034584341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2034584341
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2772305818
Short name T671
Test name
Test status
Simulation time 607148158469 ps
CPU time 1403.91 seconds
Started May 26 02:33:41 PM PDT 24
Finished May 26 02:57:05 PM PDT 24
Peak memory 201880 kb
Host smart-6ae05717-8c48-4692-a5aa-e05800ac34bf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772305818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2772305818
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.557950630
Short name T516
Test name
Test status
Simulation time 128849603473 ps
CPU time 685.63 seconds
Started May 26 02:33:41 PM PDT 24
Finished May 26 02:45:08 PM PDT 24
Peak memory 202164 kb
Host smart-af602f77-7708-454f-8928-5cf663bb4c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557950630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.557950630
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2384733685
Short name T534
Test name
Test status
Simulation time 34513708503 ps
CPU time 7.38 seconds
Started May 26 02:33:42 PM PDT 24
Finished May 26 02:33:50 PM PDT 24
Peak memory 201696 kb
Host smart-5ab01662-b531-4797-80be-7db7f3f223b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384733685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2384733685
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.4263423050
Short name T41
Test name
Test status
Simulation time 3459126914 ps
CPU time 1.51 seconds
Started May 26 02:33:42 PM PDT 24
Finished May 26 02:33:44 PM PDT 24
Peak memory 201620 kb
Host smart-b2756ebf-e710-493f-9683-ff9ed589998c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263423050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.4263423050
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2607388557
Short name T532
Test name
Test status
Simulation time 5860453755 ps
CPU time 14.79 seconds
Started May 26 02:33:37 PM PDT 24
Finished May 26 02:33:53 PM PDT 24
Peak memory 201668 kb
Host smart-84db026b-9d25-4dbd-8fdc-d63aa6aee747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607388557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2607388557
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3063581104
Short name T282
Test name
Test status
Simulation time 332911436462 ps
CPU time 791.27 seconds
Started May 26 02:33:42 PM PDT 24
Finished May 26 02:46:54 PM PDT 24
Peak memory 201864 kb
Host smart-1b04c59c-ad6f-49fb-bbee-8c457e7f259a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063581104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3063581104
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3161002584
Short name T460
Test name
Test status
Simulation time 391382259 ps
CPU time 1.43 seconds
Started May 26 02:33:50 PM PDT 24
Finished May 26 02:33:52 PM PDT 24
Peak memory 201564 kb
Host smart-7574f87d-5cb8-41c3-8abd-257c3368f244
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161002584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3161002584
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.419313647
Short name T145
Test name
Test status
Simulation time 171744124086 ps
CPU time 6.4 seconds
Started May 26 02:33:50 PM PDT 24
Finished May 26 02:33:57 PM PDT 24
Peak memory 201868 kb
Host smart-18a126f4-7e15-451b-884e-9b039f219553
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419313647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.419313647
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3618254899
Short name T264
Test name
Test status
Simulation time 492480595476 ps
CPU time 1107.12 seconds
Started May 26 02:33:50 PM PDT 24
Finished May 26 02:52:18 PM PDT 24
Peak memory 201860 kb
Host smart-ab1b4415-3d51-4a4f-ba98-502590eebf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618254899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3618254899
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2320591488
Short name T752
Test name
Test status
Simulation time 492204479602 ps
CPU time 1210.82 seconds
Started May 26 02:33:49 PM PDT 24
Finished May 26 02:54:00 PM PDT 24
Peak memory 201868 kb
Host smart-7841c0d4-0197-41c3-aec2-10c99394beb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320591488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2320591488
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1643559522
Short name T551
Test name
Test status
Simulation time 327332348639 ps
CPU time 246.17 seconds
Started May 26 02:33:49 PM PDT 24
Finished May 26 02:37:56 PM PDT 24
Peak memory 201852 kb
Host smart-500f27c3-06cc-4d24-b86e-f8af3dfc86e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643559522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1643559522
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3288670140
Short name T695
Test name
Test status
Simulation time 327382832581 ps
CPU time 446.34 seconds
Started May 26 02:33:51 PM PDT 24
Finished May 26 02:41:18 PM PDT 24
Peak memory 201884 kb
Host smart-441ce336-584e-41ee-aee7-cb1a77e29942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288670140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3288670140
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.433731819
Short name T443
Test name
Test status
Simulation time 337888191317 ps
CPU time 388.87 seconds
Started May 26 02:33:48 PM PDT 24
Finished May 26 02:40:18 PM PDT 24
Peak memory 201820 kb
Host smart-6e3b8b4c-20b8-461a-80f8-14634c44a95c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=433731819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.433731819
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3132706606
Short name T679
Test name
Test status
Simulation time 586314677631 ps
CPU time 1292.97 seconds
Started May 26 02:33:48 PM PDT 24
Finished May 26 02:55:22 PM PDT 24
Peak memory 201896 kb
Host smart-109c837e-29a6-4342-bc9e-26b4822e453a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132706606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3132706606
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3513354038
Short name T388
Test name
Test status
Simulation time 197905810467 ps
CPU time 487.13 seconds
Started May 26 02:33:49 PM PDT 24
Finished May 26 02:41:57 PM PDT 24
Peak memory 201824 kb
Host smart-3dbb0024-7862-43c0-bd3b-f440150d6a0e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513354038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3513354038
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.375022946
Short name T347
Test name
Test status
Simulation time 124046391339 ps
CPU time 449.13 seconds
Started May 26 02:33:50 PM PDT 24
Finished May 26 02:41:20 PM PDT 24
Peak memory 202152 kb
Host smart-e80fbba9-d45b-4a25-9e37-4dbceae9275b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375022946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.375022946
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.2950344542
Short name T359
Test name
Test status
Simulation time 33485373753 ps
CPU time 40.2 seconds
Started May 26 02:33:48 PM PDT 24
Finished May 26 02:34:29 PM PDT 24
Peak memory 201700 kb
Host smart-c79a33d6-dc21-4080-b880-5ac758713295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950344542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.2950344542
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.322591362
Short name T705
Test name
Test status
Simulation time 4777697318 ps
CPU time 7.06 seconds
Started May 26 02:33:48 PM PDT 24
Finished May 26 02:33:55 PM PDT 24
Peak memory 201628 kb
Host smart-867330d6-4322-478b-87e7-9090f9ef8bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322591362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.322591362
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1547851924
Short name T728
Test name
Test status
Simulation time 5886503690 ps
CPU time 8.06 seconds
Started May 26 02:33:42 PM PDT 24
Finished May 26 02:33:50 PM PDT 24
Peak memory 201700 kb
Host smart-4ca7950a-a750-4dc6-8619-e70c3994e4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547851924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1547851924
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2087769826
Short name T84
Test name
Test status
Simulation time 411857579129 ps
CPU time 186.54 seconds
Started May 26 02:33:49 PM PDT 24
Finished May 26 02:36:56 PM PDT 24
Peak memory 201820 kb
Host smart-b7d2af31-f57c-47ac-b251-0e53d0b92936
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087769826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2087769826
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.2362957634
Short name T650
Test name
Test status
Simulation time 408973292 ps
CPU time 1.35 seconds
Started May 26 02:33:57 PM PDT 24
Finished May 26 02:33:59 PM PDT 24
Peak memory 201576 kb
Host smart-6f41e769-18da-4bf0-b62b-42ee957b6512
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362957634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.2362957634
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.2303457645
Short name T244
Test name
Test status
Simulation time 510425486800 ps
CPU time 896.04 seconds
Started May 26 02:33:56 PM PDT 24
Finished May 26 02:48:53 PM PDT 24
Peak memory 201832 kb
Host smart-e16d108a-0945-4916-a593-d9e7046117ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303457645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.2303457645
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3762886528
Short name T646
Test name
Test status
Simulation time 330033457060 ps
CPU time 717.99 seconds
Started May 26 02:33:50 PM PDT 24
Finished May 26 02:45:48 PM PDT 24
Peak memory 201928 kb
Host smart-ff57dc00-7985-4d5a-93c6-1f82b3b1dd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762886528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3762886528
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1750709886
Short name T778
Test name
Test status
Simulation time 166556895901 ps
CPU time 209.27 seconds
Started May 26 02:33:57 PM PDT 24
Finished May 26 02:37:26 PM PDT 24
Peak memory 201740 kb
Host smart-e386a648-4e86-478a-ae85-5e640141a044
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750709886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1750709886
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3795643557
Short name T732
Test name
Test status
Simulation time 161621922743 ps
CPU time 100.76 seconds
Started May 26 02:33:50 PM PDT 24
Finished May 26 02:35:32 PM PDT 24
Peak memory 201912 kb
Host smart-e19e43a3-4336-4970-80c1-b90a7f71db1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795643557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3795643557
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3799095538
Short name T737
Test name
Test status
Simulation time 168604205671 ps
CPU time 190.61 seconds
Started May 26 02:33:48 PM PDT 24
Finished May 26 02:36:59 PM PDT 24
Peak memory 201824 kb
Host smart-4db36ba8-5c45-4334-8f81-69be6f503176
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799095538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3799095538
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2209003994
Short name T255
Test name
Test status
Simulation time 191974509375 ps
CPU time 473.73 seconds
Started May 26 02:33:57 PM PDT 24
Finished May 26 02:41:51 PM PDT 24
Peak memory 201920 kb
Host smart-c2c12c24-6cd9-4e53-b2a1-d605cbaf5eaa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209003994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2209003994
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2022361166
Short name T427
Test name
Test status
Simulation time 600259990095 ps
CPU time 356.74 seconds
Started May 26 02:33:57 PM PDT 24
Finished May 26 02:39:54 PM PDT 24
Peak memory 201860 kb
Host smart-53131a0f-c641-475c-a17e-9cd24161dea4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022361166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2022361166
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3197948553
Short name T609
Test name
Test status
Simulation time 76529580447 ps
CPU time 440.28 seconds
Started May 26 02:34:00 PM PDT 24
Finished May 26 02:41:20 PM PDT 24
Peak memory 202144 kb
Host smart-1c7dcef7-1610-4987-ab88-eec9cc03b248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197948553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3197948553
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2160193173
Short name T564
Test name
Test status
Simulation time 28074925324 ps
CPU time 69.3 seconds
Started May 26 02:33:57 PM PDT 24
Finished May 26 02:35:07 PM PDT 24
Peak memory 201660 kb
Host smart-0576a362-bc58-442a-bb78-0127a481a13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160193173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2160193173
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3551047025
Short name T356
Test name
Test status
Simulation time 4519545037 ps
CPU time 2.48 seconds
Started May 26 02:33:56 PM PDT 24
Finished May 26 02:34:00 PM PDT 24
Peak memory 201668 kb
Host smart-ed0c2147-88ca-451e-befc-fa03f2ca5316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551047025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3551047025
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3373302340
Short name T406
Test name
Test status
Simulation time 5682143341 ps
CPU time 5.66 seconds
Started May 26 02:33:48 PM PDT 24
Finished May 26 02:33:55 PM PDT 24
Peak memory 201544 kb
Host smart-351fa3f3-6910-4cc1-a4e0-05c5febd6cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373302340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3373302340
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1630957486
Short name T14
Test name
Test status
Simulation time 516390231 ps
CPU time 0.8 seconds
Started May 26 02:31:34 PM PDT 24
Finished May 26 02:31:35 PM PDT 24
Peak memory 201560 kb
Host smart-1c53058d-f3c5-456b-b663-93fe9e951dfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630957486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1630957486
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1642420674
Short name T295
Test name
Test status
Simulation time 520419733314 ps
CPU time 768.4 seconds
Started May 26 02:31:46 PM PDT 24
Finished May 26 02:44:35 PM PDT 24
Peak memory 201792 kb
Host smart-901a2fa5-ea27-480f-a860-369912c32db0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642420674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1642420674
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3993822301
Short name T247
Test name
Test status
Simulation time 165034689070 ps
CPU time 93.76 seconds
Started May 26 02:31:36 PM PDT 24
Finished May 26 02:33:11 PM PDT 24
Peak memory 202008 kb
Host smart-9acdc198-e343-4292-a73b-3f110c92896f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993822301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3993822301
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3356561233
Short name T283
Test name
Test status
Simulation time 494591686479 ps
CPU time 597.73 seconds
Started May 26 02:31:38 PM PDT 24
Finished May 26 02:41:37 PM PDT 24
Peak memory 201912 kb
Host smart-40895d6f-39a2-4d0b-ac2d-dd1264b2370a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356561233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3356561233
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.21251174
Short name T644
Test name
Test status
Simulation time 486595324026 ps
CPU time 130.86 seconds
Started May 26 02:31:31 PM PDT 24
Finished May 26 02:33:43 PM PDT 24
Peak memory 201840 kb
Host smart-1c8152c6-b3f9-4b69-9257-8aa161225761
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=21251174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt_
fixed.21251174
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2820526147
Short name T686
Test name
Test status
Simulation time 163915802303 ps
CPU time 88.77 seconds
Started May 26 02:31:46 PM PDT 24
Finished May 26 02:33:16 PM PDT 24
Peak memory 201136 kb
Host smart-9c7d2611-0cfe-42ed-a396-0628a6e4bd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820526147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2820526147
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.4089632893
Short name T360
Test name
Test status
Simulation time 488568321808 ps
CPU time 553.59 seconds
Started May 26 02:31:32 PM PDT 24
Finished May 26 02:40:46 PM PDT 24
Peak memory 201864 kb
Host smart-d95ddf14-3b04-4b05-a362-3f3de47f53e7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089632893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.4089632893
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.4153440095
Short name T174
Test name
Test status
Simulation time 180835931084 ps
CPU time 114.08 seconds
Started May 26 02:31:37 PM PDT 24
Finished May 26 02:33:32 PM PDT 24
Peak memory 201908 kb
Host smart-96341ecb-8800-4405-bb9d-bd4f29fa668a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153440095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.4153440095
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.210618988
Short name T435
Test name
Test status
Simulation time 205211779421 ps
CPU time 429.16 seconds
Started May 26 02:31:31 PM PDT 24
Finished May 26 02:38:40 PM PDT 24
Peak memory 201784 kb
Host smart-59f1d6ef-458f-4276-b2de-cf9cf6c41069
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210618988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.210618988
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.928597877
Short name T30
Test name
Test status
Simulation time 94284368284 ps
CPU time 294.27 seconds
Started May 26 02:31:33 PM PDT 24
Finished May 26 02:36:28 PM PDT 24
Peak memory 202216 kb
Host smart-982404fc-f313-4b7f-ab9e-47b921503a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928597877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.928597877
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.441852983
Short name T440
Test name
Test status
Simulation time 44875362334 ps
CPU time 30.87 seconds
Started May 26 02:31:34 PM PDT 24
Finished May 26 02:32:06 PM PDT 24
Peak memory 201672 kb
Host smart-0bc5eb90-a981-46fe-95ce-5080787b8825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441852983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.441852983
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2568665872
Short name T439
Test name
Test status
Simulation time 4304986087 ps
CPU time 11.43 seconds
Started May 26 02:31:38 PM PDT 24
Finished May 26 02:31:50 PM PDT 24
Peak memory 201656 kb
Host smart-bdf12068-cc0b-4ae9-b908-f52490328b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568665872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2568665872
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1068271775
Short name T66
Test name
Test status
Simulation time 8449899082 ps
CPU time 2.5 seconds
Started May 26 02:31:32 PM PDT 24
Finished May 26 02:31:35 PM PDT 24
Peak memory 218480 kb
Host smart-a596ecf6-d813-4e75-bd02-1daf315e86a1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068271775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1068271775
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1132069172
Short name T372
Test name
Test status
Simulation time 6055862386 ps
CPU time 14.38 seconds
Started May 26 02:31:47 PM PDT 24
Finished May 26 02:32:02 PM PDT 24
Peak memory 201692 kb
Host smart-5e889d06-4168-423c-a280-c7154a0441c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132069172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1132069172
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2616579827
Short name T34
Test name
Test status
Simulation time 488190382637 ps
CPU time 304.12 seconds
Started May 26 02:31:33 PM PDT 24
Finished May 26 02:36:38 PM PDT 24
Peak memory 201900 kb
Host smart-3028161d-1d3a-48dd-9e80-b81cd4891d3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616579827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2616579827
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.799947204
Short name T536
Test name
Test status
Simulation time 428290368 ps
CPU time 0.79 seconds
Started May 26 02:34:04 PM PDT 24
Finished May 26 02:34:06 PM PDT 24
Peak memory 201540 kb
Host smart-819b64f2-9050-417c-a176-b0233c1b14e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799947204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.799947204
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1660477599
Short name T493
Test name
Test status
Simulation time 166886688042 ps
CPU time 286.11 seconds
Started May 26 02:34:05 PM PDT 24
Finished May 26 02:38:51 PM PDT 24
Peak memory 201812 kb
Host smart-149bf181-d453-40ac-8ae7-16f3e10b1847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660477599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1660477599
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2877807503
Short name T85
Test name
Test status
Simulation time 161771506364 ps
CPU time 367.12 seconds
Started May 26 02:34:00 PM PDT 24
Finished May 26 02:40:08 PM PDT 24
Peak memory 201840 kb
Host smart-34bd8494-09a9-4058-a030-9d781c0993f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877807503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2877807503
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.458947099
Short name T482
Test name
Test status
Simulation time 320317406316 ps
CPU time 392.24 seconds
Started May 26 02:34:04 PM PDT 24
Finished May 26 02:40:37 PM PDT 24
Peak memory 201860 kb
Host smart-ad5734d4-55e1-4e9c-92bf-d659e59c29ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=458947099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrup
t_fixed.458947099
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.696721316
Short name T643
Test name
Test status
Simulation time 166041944556 ps
CPU time 368.64 seconds
Started May 26 02:34:00 PM PDT 24
Finished May 26 02:40:09 PM PDT 24
Peak memory 201900 kb
Host smart-17eb9882-0d2f-4d88-b9a9-d496f58ad8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696721316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.696721316
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.917133730
Short name T559
Test name
Test status
Simulation time 160573603063 ps
CPU time 39.75 seconds
Started May 26 02:33:58 PM PDT 24
Finished May 26 02:34:38 PM PDT 24
Peak memory 201724 kb
Host smart-9e9048c3-dddb-441d-8a53-59b102e5d7c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=917133730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.917133730
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3266972899
Short name T659
Test name
Test status
Simulation time 191623263803 ps
CPU time 466.46 seconds
Started May 26 02:34:04 PM PDT 24
Finished May 26 02:41:51 PM PDT 24
Peak memory 201844 kb
Host smart-938df1c9-44fa-42ef-bbe5-235115999974
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266972899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3266972899
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2093654354
Short name T452
Test name
Test status
Simulation time 388660557185 ps
CPU time 913.66 seconds
Started May 26 02:34:03 PM PDT 24
Finished May 26 02:49:17 PM PDT 24
Peak memory 201852 kb
Host smart-7dced9ca-3706-4a3c-a3ba-0256f056a77b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093654354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2093654354
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1828696316
Short name T553
Test name
Test status
Simulation time 89251814710 ps
CPU time 292.51 seconds
Started May 26 02:34:06 PM PDT 24
Finished May 26 02:38:59 PM PDT 24
Peak memory 202160 kb
Host smart-323b4065-0189-49b3-b42c-3e23d79f3b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828696316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1828696316
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.4199866476
Short name T410
Test name
Test status
Simulation time 38777242332 ps
CPU time 25.05 seconds
Started May 26 02:34:04 PM PDT 24
Finished May 26 02:34:29 PM PDT 24
Peak memory 201652 kb
Host smart-ce5ee46f-2846-49fd-8c38-3360d15dc692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199866476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.4199866476
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.2027172536
Short name T506
Test name
Test status
Simulation time 3958399777 ps
CPU time 2.29 seconds
Started May 26 02:34:05 PM PDT 24
Finished May 26 02:34:08 PM PDT 24
Peak memory 201600 kb
Host smart-4b00747e-74b1-4cc3-adbd-db1aabe26bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027172536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2027172536
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2397604045
Short name T402
Test name
Test status
Simulation time 5876414076 ps
CPU time 3.7 seconds
Started May 26 02:33:59 PM PDT 24
Finished May 26 02:34:03 PM PDT 24
Peak memory 201668 kb
Host smart-a612ab25-c7d2-4175-bdac-408e84001b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397604045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2397604045
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2201355575
Short name T593
Test name
Test status
Simulation time 172875593140 ps
CPU time 423.92 seconds
Started May 26 02:34:05 PM PDT 24
Finished May 26 02:41:09 PM PDT 24
Peak memory 218304 kb
Host smart-8bb01bfb-fc6b-42e4-85af-55cd81b24355
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201355575 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2201355575
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.1037892406
Short name T765
Test name
Test status
Simulation time 507944110 ps
CPU time 1.83 seconds
Started May 26 02:34:25 PM PDT 24
Finished May 26 02:34:28 PM PDT 24
Peak memory 201540 kb
Host smart-519d81fe-2e3b-4368-9256-f6acf248bcfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037892406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1037892406
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2608639220
Short name T716
Test name
Test status
Simulation time 159493197464 ps
CPU time 206.01 seconds
Started May 26 02:34:16 PM PDT 24
Finished May 26 02:37:43 PM PDT 24
Peak memory 201912 kb
Host smart-90892bca-fae0-4892-97c4-7ed506bb70ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608639220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2608639220
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.1359305993
Short name T179
Test name
Test status
Simulation time 492454137328 ps
CPU time 302.2 seconds
Started May 26 02:34:16 PM PDT 24
Finished May 26 02:39:19 PM PDT 24
Peak memory 201752 kb
Host smart-dbbf01c9-59b1-4016-a864-3d36e63c2c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359305993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.1359305993
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3999066518
Short name T757
Test name
Test status
Simulation time 324849963592 ps
CPU time 198.27 seconds
Started May 26 02:34:16 PM PDT 24
Finished May 26 02:37:35 PM PDT 24
Peak memory 201856 kb
Host smart-6f8fd1ad-a003-41f7-9cfc-77d4b6a0fc84
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999066518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3999066518
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.698841222
Short name T4
Test name
Test status
Simulation time 163579074194 ps
CPU time 191.65 seconds
Started May 26 02:34:04 PM PDT 24
Finished May 26 02:37:16 PM PDT 24
Peak memory 201880 kb
Host smart-cfa73ae2-fe52-4775-ad25-90d37c77ced8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698841222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.698841222
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.150924204
Short name T676
Test name
Test status
Simulation time 484516834335 ps
CPU time 1150 seconds
Started May 26 02:34:16 PM PDT 24
Finished May 26 02:53:27 PM PDT 24
Peak memory 201808 kb
Host smart-a979b9bb-b1a8-48d9-a9dc-376d02161e51
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=150924204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.150924204
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2520670966
Short name T531
Test name
Test status
Simulation time 209825375775 ps
CPU time 128.99 seconds
Started May 26 02:34:15 PM PDT 24
Finished May 26 02:36:25 PM PDT 24
Peak memory 202008 kb
Host smart-f3456eb5-41a3-4775-b505-792a8767b09f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520670966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.2520670966
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.179822407
Short name T785
Test name
Test status
Simulation time 109237083534 ps
CPU time 437.94 seconds
Started May 26 02:34:16 PM PDT 24
Finished May 26 02:41:35 PM PDT 24
Peak memory 202128 kb
Host smart-228bfa66-3051-4970-b6a3-88dac86385b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179822407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.179822407
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.131240623
Short name T721
Test name
Test status
Simulation time 42649898221 ps
CPU time 19.81 seconds
Started May 26 02:34:16 PM PDT 24
Finished May 26 02:34:36 PM PDT 24
Peak memory 201680 kb
Host smart-4e6e05e2-4305-4628-948a-5a202fb87881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131240623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.131240623
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3486245074
Short name T423
Test name
Test status
Simulation time 4360946963 ps
CPU time 5.28 seconds
Started May 26 02:34:16 PM PDT 24
Finished May 26 02:34:22 PM PDT 24
Peak memory 201676 kb
Host smart-a66b5633-373e-4976-9e21-de880e9cb109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486245074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3486245074
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3308559588
Short name T398
Test name
Test status
Simulation time 6030705275 ps
CPU time 4.52 seconds
Started May 26 02:34:05 PM PDT 24
Finished May 26 02:34:10 PM PDT 24
Peak memory 201680 kb
Host smart-07a8efa7-c89e-4ffc-943c-904095a39ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308559588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3308559588
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3499716310
Short name T767
Test name
Test status
Simulation time 197785637041 ps
CPU time 115.7 seconds
Started May 26 02:34:25 PM PDT 24
Finished May 26 02:36:21 PM PDT 24
Peak memory 201936 kb
Host smart-97f42a22-8e7c-4ba3-9ceb-5b6f1562d3ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499716310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3499716310
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3298088835
Short name T503
Test name
Test status
Simulation time 401809697 ps
CPU time 0.87 seconds
Started May 26 02:34:25 PM PDT 24
Finished May 26 02:34:26 PM PDT 24
Peak memory 201540 kb
Host smart-0a9077cd-c52e-46ba-8ab4-df663aa24064
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298088835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3298088835
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2432325653
Short name T479
Test name
Test status
Simulation time 160148664682 ps
CPU time 29.95 seconds
Started May 26 02:34:23 PM PDT 24
Finished May 26 02:34:54 PM PDT 24
Peak memory 201856 kb
Host smart-935b048b-6c97-451d-b2bb-0432b811e7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432325653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2432325653
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.100385945
Short name T661
Test name
Test status
Simulation time 161812938547 ps
CPU time 373.53 seconds
Started May 26 02:34:24 PM PDT 24
Finished May 26 02:40:38 PM PDT 24
Peak memory 201908 kb
Host smart-8b015d62-c684-4bec-92bf-88de6040d205
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=100385945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.100385945
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1268204215
Short name T221
Test name
Test status
Simulation time 330393521000 ps
CPU time 570.37 seconds
Started May 26 02:34:23 PM PDT 24
Finished May 26 02:43:54 PM PDT 24
Peak memory 201800 kb
Host smart-c19fe8b7-574c-4640-98e5-7ac012c66b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268204215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1268204215
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3161266055
Short name T723
Test name
Test status
Simulation time 163636066861 ps
CPU time 87.35 seconds
Started May 26 02:34:23 PM PDT 24
Finished May 26 02:35:51 PM PDT 24
Peak memory 201840 kb
Host smart-0c9ee894-bb29-4e6f-8d39-0efe13f51426
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161266055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3161266055
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1610075128
Short name T140
Test name
Test status
Simulation time 538076105553 ps
CPU time 125 seconds
Started May 26 02:34:25 PM PDT 24
Finished May 26 02:36:31 PM PDT 24
Peak memory 201924 kb
Host smart-f8fd6b22-f812-4c16-beea-4490eb888b2d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610075128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1610075128
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.131009302
Short name T561
Test name
Test status
Simulation time 400586059251 ps
CPU time 469.71 seconds
Started May 26 02:34:24 PM PDT 24
Finished May 26 02:42:14 PM PDT 24
Peak memory 201928 kb
Host smart-c947dccb-d869-41c6-91b0-739b2522fee1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131009302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.131009302
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.843258401
Short name T411
Test name
Test status
Simulation time 79798284419 ps
CPU time 309.35 seconds
Started May 26 02:34:24 PM PDT 24
Finished May 26 02:39:35 PM PDT 24
Peak memory 202228 kb
Host smart-d0028575-c659-47b6-87ae-cdb47621ced9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843258401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.843258401
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2834432814
Short name T579
Test name
Test status
Simulation time 29763415812 ps
CPU time 66 seconds
Started May 26 02:34:25 PM PDT 24
Finished May 26 02:35:32 PM PDT 24
Peak memory 201644 kb
Host smart-f4b06b34-4aad-4f0a-aba3-9020983b9f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834432814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2834432814
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3405928483
Short name T490
Test name
Test status
Simulation time 3922679006 ps
CPU time 2.87 seconds
Started May 26 02:34:24 PM PDT 24
Finished May 26 02:34:27 PM PDT 24
Peak memory 201584 kb
Host smart-b6c0c1f3-e6f1-43d5-a731-be5b6d1cc38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405928483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3405928483
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2607294806
Short name T462
Test name
Test status
Simulation time 6101918327 ps
CPU time 2 seconds
Started May 26 02:34:25 PM PDT 24
Finished May 26 02:34:28 PM PDT 24
Peak memory 201696 kb
Host smart-eaf75f1f-dc74-449c-ac75-6b411dfaa88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607294806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2607294806
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1876520775
Short name T80
Test name
Test status
Simulation time 332418734720 ps
CPU time 758.55 seconds
Started May 26 02:34:24 PM PDT 24
Finished May 26 02:47:03 PM PDT 24
Peak memory 201828 kb
Host smart-bed3c039-9122-40b4-b05a-cc6f95435f97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876520775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1876520775
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1891151038
Short name T327
Test name
Test status
Simulation time 538495049512 ps
CPU time 236.49 seconds
Started May 26 02:34:24 PM PDT 24
Finished May 26 02:38:22 PM PDT 24
Peak memory 210220 kb
Host smart-c0bc797c-f335-4f47-8d98-8df6823c6121
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891151038 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1891151038
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.851111908
Short name T717
Test name
Test status
Simulation time 614551105 ps
CPU time 0.79 seconds
Started May 26 02:34:30 PM PDT 24
Finished May 26 02:34:32 PM PDT 24
Peak memory 201416 kb
Host smart-dab788ce-b860-4437-96a0-5e2f8f3cefcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851111908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.851111908
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2695337947
Short name T37
Test name
Test status
Simulation time 322576420691 ps
CPU time 92.45 seconds
Started May 26 02:34:23 PM PDT 24
Finished May 26 02:35:57 PM PDT 24
Peak memory 201828 kb
Host smart-bc4fff4e-4c86-4a01-82d0-d7c744c1130a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695337947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2695337947
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2948052284
Short name T755
Test name
Test status
Simulation time 354018673252 ps
CPU time 414 seconds
Started May 26 02:34:31 PM PDT 24
Finished May 26 02:41:26 PM PDT 24
Peak memory 201868 kb
Host smart-ffb6b776-e45b-489d-a467-e9baa009413f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948052284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2948052284
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1799625553
Short name T322
Test name
Test status
Simulation time 162065199236 ps
CPU time 356.42 seconds
Started May 26 02:34:25 PM PDT 24
Finished May 26 02:40:22 PM PDT 24
Peak memory 201900 kb
Host smart-29ec0514-59bd-4a75-ac27-8f47752fb83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799625553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1799625553
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3445328248
Short name T166
Test name
Test status
Simulation time 326435207451 ps
CPU time 730.43 seconds
Started May 26 02:34:24 PM PDT 24
Finished May 26 02:46:35 PM PDT 24
Peak memory 201856 kb
Host smart-d4ecbae9-2ca6-4fb6-a5f2-0efd8abe414c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445328248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3445328248
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2155991778
Short name T262
Test name
Test status
Simulation time 496551912084 ps
CPU time 576.56 seconds
Started May 26 02:34:23 PM PDT 24
Finished May 26 02:44:00 PM PDT 24
Peak memory 201848 kb
Host smart-d83f35a5-6f3e-42ac-ae6c-4dc10b198c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155991778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2155991778
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2461863639
Short name T442
Test name
Test status
Simulation time 495488813412 ps
CPU time 562.77 seconds
Started May 26 02:34:26 PM PDT 24
Finished May 26 02:43:49 PM PDT 24
Peak memory 201840 kb
Host smart-be66362c-de12-475e-b064-c3d3e8b7c8c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461863639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2461863639
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3247411906
Short name T44
Test name
Test status
Simulation time 258821443875 ps
CPU time 552.64 seconds
Started May 26 02:34:22 PM PDT 24
Finished May 26 02:43:35 PM PDT 24
Peak memory 201856 kb
Host smart-e44e76d3-018b-4e8a-b47c-2e1f58b49c8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247411906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3247411906
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1486066574
Short name T494
Test name
Test status
Simulation time 197150627959 ps
CPU time 105.61 seconds
Started May 26 02:34:25 PM PDT 24
Finished May 26 02:36:11 PM PDT 24
Peak memory 201852 kb
Host smart-622462d7-324b-4865-b0b1-9bc07a562857
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486066574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1486066574
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.4033076472
Short name T420
Test name
Test status
Simulation time 86525014987 ps
CPU time 329.14 seconds
Started May 26 02:34:31 PM PDT 24
Finished May 26 02:40:01 PM PDT 24
Peak memory 202184 kb
Host smart-4a513e0c-4053-4188-8049-5415739ceacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033076472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.4033076472
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3299504784
Short name T655
Test name
Test status
Simulation time 42394077836 ps
CPU time 6.09 seconds
Started May 26 02:34:33 PM PDT 24
Finished May 26 02:34:39 PM PDT 24
Peak memory 201648 kb
Host smart-2cdd9d97-c577-48e7-a887-41db086b6cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299504784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3299504784
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1272932703
Short name T508
Test name
Test status
Simulation time 4918757326 ps
CPU time 7.15 seconds
Started May 26 02:34:30 PM PDT 24
Finished May 26 02:34:38 PM PDT 24
Peak memory 201656 kb
Host smart-5368e647-884a-40ab-a40d-110c405cfa56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272932703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1272932703
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.799403983
Short name T682
Test name
Test status
Simulation time 6137355203 ps
CPU time 4.77 seconds
Started May 26 02:34:25 PM PDT 24
Finished May 26 02:34:31 PM PDT 24
Peak memory 201684 kb
Host smart-e2e01f1c-eb22-48e3-bf9f-675ec2a980c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799403983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.799403983
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3270733148
Short name T760
Test name
Test status
Simulation time 499507366783 ps
CPU time 316.56 seconds
Started May 26 02:34:31 PM PDT 24
Finished May 26 02:39:49 PM PDT 24
Peak memory 201812 kb
Host smart-a93817bb-327c-460a-812a-442e4cc7bb61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270733148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3270733148
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2028636958
Short name T415
Test name
Test status
Simulation time 63140970407 ps
CPU time 130.36 seconds
Started May 26 02:34:30 PM PDT 24
Finished May 26 02:36:41 PM PDT 24
Peak memory 201912 kb
Host smart-bef0f1ed-fc5f-4c98-a762-d48abc270cb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028636958 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2028636958
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.265399464
Short name T381
Test name
Test status
Simulation time 383349670 ps
CPU time 1.07 seconds
Started May 26 02:34:38 PM PDT 24
Finished May 26 02:34:40 PM PDT 24
Peak memory 201416 kb
Host smart-bf2df950-d36f-4654-82d3-5cd6e7d86296
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265399464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.265399464
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2406808104
Short name T248
Test name
Test status
Simulation time 345442237125 ps
CPU time 53.46 seconds
Started May 26 02:34:31 PM PDT 24
Finished May 26 02:35:25 PM PDT 24
Peak memory 201832 kb
Host smart-d4eebc09-4ca8-450e-9e8c-066fb0ce900f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406808104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2406808104
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.126180404
Short name T623
Test name
Test status
Simulation time 240324224056 ps
CPU time 566.42 seconds
Started May 26 02:34:39 PM PDT 24
Finished May 26 02:44:06 PM PDT 24
Peak memory 201848 kb
Host smart-b586ad0d-2395-4de5-af1d-8acb42cd7158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126180404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.126180404
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2369446186
Short name T198
Test name
Test status
Simulation time 326377100785 ps
CPU time 749.31 seconds
Started May 26 02:34:33 PM PDT 24
Finished May 26 02:47:03 PM PDT 24
Peak memory 201828 kb
Host smart-f259afb8-9fd7-4a29-8eef-8ad7efad9571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369446186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2369446186
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3315859581
Short name T607
Test name
Test status
Simulation time 329647848082 ps
CPU time 199.96 seconds
Started May 26 02:34:30 PM PDT 24
Finished May 26 02:37:50 PM PDT 24
Peak memory 201832 kb
Host smart-99e78137-e90f-4b4d-8229-aee30cc542c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315859581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3315859581
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1365106719
Short name T648
Test name
Test status
Simulation time 332434589131 ps
CPU time 573.02 seconds
Started May 26 02:34:32 PM PDT 24
Finished May 26 02:44:06 PM PDT 24
Peak memory 201920 kb
Host smart-c8bddf4c-8c4a-4af0-9307-e9597f74d4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365106719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1365106719
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3632122975
Short name T758
Test name
Test status
Simulation time 320700779078 ps
CPU time 723.4 seconds
Started May 26 02:34:31 PM PDT 24
Finished May 26 02:46:35 PM PDT 24
Peak memory 201844 kb
Host smart-eb97e083-1110-4e22-bc38-97cf2cca0bd5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632122975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3632122975
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2321179319
Short name T615
Test name
Test status
Simulation time 470993516009 ps
CPU time 585.13 seconds
Started May 26 02:34:31 PM PDT 24
Finished May 26 02:44:17 PM PDT 24
Peak memory 201916 kb
Host smart-f4bc9d42-dd6c-43b8-883e-4640d10d9323
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321179319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2321179319
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2952171764
Short name T195
Test name
Test status
Simulation time 611729441643 ps
CPU time 721.12 seconds
Started May 26 02:34:32 PM PDT 24
Finished May 26 02:46:34 PM PDT 24
Peak memory 201872 kb
Host smart-9918c7ca-22e3-4ed8-886b-fece3ffbe7ad
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952171764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2952171764
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.726962509
Short name T344
Test name
Test status
Simulation time 95536117798 ps
CPU time 381.8 seconds
Started May 26 02:34:39 PM PDT 24
Finished May 26 02:41:02 PM PDT 24
Peak memory 202176 kb
Host smart-5c67889f-d805-4c17-bb52-3644e1d96637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726962509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.726962509
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3216733167
Short name T9
Test name
Test status
Simulation time 44818559747 ps
CPU time 25.58 seconds
Started May 26 02:34:40 PM PDT 24
Finished May 26 02:35:06 PM PDT 24
Peak memory 201708 kb
Host smart-a7bf6239-df7a-430e-9edf-0bbb6ee418e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216733167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3216733167
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.616501994
Short name T461
Test name
Test status
Simulation time 4080046333 ps
CPU time 11.36 seconds
Started May 26 02:34:39 PM PDT 24
Finished May 26 02:34:50 PM PDT 24
Peak memory 201588 kb
Host smart-7ccc33c5-11ef-4059-bb12-838138e0e1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616501994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.616501994
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.4078675687
Short name T421
Test name
Test status
Simulation time 5545600922 ps
CPU time 14.46 seconds
Started May 26 02:34:30 PM PDT 24
Finished May 26 02:34:46 PM PDT 24
Peak memory 201680 kb
Host smart-69c359e0-5acc-4588-a7d1-54c96f432f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078675687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.4078675687
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.4196139623
Short name T426
Test name
Test status
Simulation time 116597634940 ps
CPU time 453.03 seconds
Started May 26 02:34:40 PM PDT 24
Finished May 26 02:42:13 PM PDT 24
Peak memory 210456 kb
Host smart-bfa7ecd9-55ff-4b9c-956a-e1576ba3a2f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196139623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.4196139623
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.716353355
Short name T92
Test name
Test status
Simulation time 418006297522 ps
CPU time 263.55 seconds
Started May 26 02:34:38 PM PDT 24
Finished May 26 02:39:02 PM PDT 24
Peak memory 210220 kb
Host smart-91ac31c6-ab19-4d36-a58f-356d01f6e8b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716353355 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.716353355
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1945108066
Short name T369
Test name
Test status
Simulation time 380315333 ps
CPU time 1.48 seconds
Started May 26 02:34:49 PM PDT 24
Finished May 26 02:34:51 PM PDT 24
Peak memory 201528 kb
Host smart-89fb6c0d-4bfd-40d4-a0ea-f294d6b538e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945108066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1945108066
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3064625421
Short name T299
Test name
Test status
Simulation time 166162257256 ps
CPU time 106.71 seconds
Started May 26 02:34:38 PM PDT 24
Finished May 26 02:36:26 PM PDT 24
Peak memory 201836 kb
Host smart-4b40ff94-ac8a-4d5b-97ea-f545ca7f8d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064625421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3064625421
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3262962092
Short name T589
Test name
Test status
Simulation time 163465643846 ps
CPU time 190.12 seconds
Started May 26 02:34:40 PM PDT 24
Finished May 26 02:37:50 PM PDT 24
Peak memory 201800 kb
Host smart-665d30f5-babe-4bab-ac66-c328a5756f2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262962092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3262962092
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3718963684
Short name T155
Test name
Test status
Simulation time 331139040732 ps
CPU time 114.21 seconds
Started May 26 02:34:40 PM PDT 24
Finished May 26 02:36:34 PM PDT 24
Peak memory 201904 kb
Host smart-5d8f6a24-94ee-473b-ac2c-fd024101d4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718963684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3718963684
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1607984051
Short name T540
Test name
Test status
Simulation time 486005582138 ps
CPU time 289.73 seconds
Started May 26 02:34:38 PM PDT 24
Finished May 26 02:39:28 PM PDT 24
Peak memory 201804 kb
Host smart-9e6cc940-e2ca-43ce-aba7-156531891f8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607984051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1607984051
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2312573329
Short name T219
Test name
Test status
Simulation time 536626834885 ps
CPU time 416.7 seconds
Started May 26 02:34:41 PM PDT 24
Finished May 26 02:41:38 PM PDT 24
Peak memory 201872 kb
Host smart-4fbb98f2-4e31-4cdf-92a0-3ea7aec05dc7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312573329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2312573329
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.476168870
Short name T173
Test name
Test status
Simulation time 199100824892 ps
CPU time 109.42 seconds
Started May 26 02:34:48 PM PDT 24
Finished May 26 02:36:38 PM PDT 24
Peak memory 201868 kb
Host smart-1b82a949-4e86-47b0-adfc-a594dfa72b6e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476168870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.476168870
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.675303678
Short name T735
Test name
Test status
Simulation time 140790485086 ps
CPU time 710.84 seconds
Started May 26 02:34:48 PM PDT 24
Finished May 26 02:46:39 PM PDT 24
Peak memory 202140 kb
Host smart-11cbeee4-edb7-4f6a-ae5d-c5e343c44b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675303678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.675303678
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.4210533934
Short name T472
Test name
Test status
Simulation time 26962684609 ps
CPU time 61.35 seconds
Started May 26 02:34:46 PM PDT 24
Finished May 26 02:35:48 PM PDT 24
Peak memory 201656 kb
Host smart-79916acc-ead9-4b7b-9d0c-c1ff573adc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210533934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.4210533934
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.707716008
Short name T622
Test name
Test status
Simulation time 3805555031 ps
CPU time 1.86 seconds
Started May 26 02:34:49 PM PDT 24
Finished May 26 02:34:51 PM PDT 24
Peak memory 201596 kb
Host smart-7147c715-e112-46a7-990c-963c2116ec9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707716008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.707716008
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.132440847
Short name T774
Test name
Test status
Simulation time 5825122733 ps
CPU time 8.17 seconds
Started May 26 02:34:39 PM PDT 24
Finished May 26 02:34:48 PM PDT 24
Peak memory 201684 kb
Host smart-ea5875b5-d5f5-44c8-86f1-49db3af6eb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132440847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.132440847
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3130450680
Short name T784
Test name
Test status
Simulation time 54380223680 ps
CPU time 15.63 seconds
Started May 26 02:34:49 PM PDT 24
Finished May 26 02:35:05 PM PDT 24
Peak memory 201660 kb
Host smart-97a187af-7a38-4956-87b5-5e97510e42a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130450680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3130450680
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1804701067
Short name T627
Test name
Test status
Simulation time 110308688911 ps
CPU time 107.04 seconds
Started May 26 02:34:47 PM PDT 24
Finished May 26 02:36:35 PM PDT 24
Peak memory 210488 kb
Host smart-1fd7cef4-f0d1-4ae4-bdfd-78eb25505420
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804701067 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1804701067
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.782446374
Short name T87
Test name
Test status
Simulation time 470643410 ps
CPU time 0.92 seconds
Started May 26 02:35:03 PM PDT 24
Finished May 26 02:35:06 PM PDT 24
Peak memory 201560 kb
Host smart-e1523ca6-e716-47f7-90f0-fff9d0c2b7c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782446374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.782446374
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.232497555
Short name T298
Test name
Test status
Simulation time 330861566826 ps
CPU time 168.79 seconds
Started May 26 02:35:03 PM PDT 24
Finished May 26 02:37:53 PM PDT 24
Peak memory 201928 kb
Host smart-e1e6433f-a4b0-475b-94da-6215fbadf993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232497555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.232497555
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1574153002
Short name T541
Test name
Test status
Simulation time 495288501822 ps
CPU time 1167.39 seconds
Started May 26 02:35:03 PM PDT 24
Finished May 26 02:54:32 PM PDT 24
Peak memory 201860 kb
Host smart-0bf802de-26da-4ba7-b319-d20bf31ad3f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574153002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.1574153002
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.734676905
Short name T193
Test name
Test status
Simulation time 493898079292 ps
CPU time 1135.43 seconds
Started May 26 02:34:48 PM PDT 24
Finished May 26 02:53:45 PM PDT 24
Peak memory 201824 kb
Host smart-e4c802d2-5554-4af9-b231-36847093d941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734676905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.734676905
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.548987996
Short name T587
Test name
Test status
Simulation time 334908667459 ps
CPU time 372.23 seconds
Started May 26 02:34:46 PM PDT 24
Finished May 26 02:40:59 PM PDT 24
Peak memory 201752 kb
Host smart-55c8a86b-c874-4c82-a77f-c3ef5d156769
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=548987996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.548987996
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2928403481
Short name T97
Test name
Test status
Simulation time 639116168915 ps
CPU time 414.37 seconds
Started May 26 02:35:06 PM PDT 24
Finished May 26 02:42:01 PM PDT 24
Peak memory 201880 kb
Host smart-138b65ca-ad49-493f-8c2f-2e29772316dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928403481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2928403481
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3352137501
Short name T236
Test name
Test status
Simulation time 403538931741 ps
CPU time 464.64 seconds
Started May 26 02:34:55 PM PDT 24
Finished May 26 02:42:41 PM PDT 24
Peak memory 201848 kb
Host smart-82202a8b-7ad0-4513-b3f9-a355617b3691
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352137501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.3352137501
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1564550690
Short name T395
Test name
Test status
Simulation time 95439700279 ps
CPU time 376.37 seconds
Started May 26 02:35:03 PM PDT 24
Finished May 26 02:41:21 PM PDT 24
Peak memory 202252 kb
Host smart-cd866dac-6842-4620-8c66-afed71d536de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564550690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1564550690
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2131874153
Short name T702
Test name
Test status
Simulation time 22263680294 ps
CPU time 49.19 seconds
Started May 26 02:34:55 PM PDT 24
Finished May 26 02:35:45 PM PDT 24
Peak memory 201612 kb
Host smart-5fef7639-8c61-4665-8b55-5d4e4f8c7f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131874153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2131874153
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2859388001
Short name T782
Test name
Test status
Simulation time 4597577102 ps
CPU time 5.69 seconds
Started May 26 02:34:54 PM PDT 24
Finished May 26 02:35:01 PM PDT 24
Peak memory 201644 kb
Host smart-c699afc2-181e-4368-888e-da34d1343ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859388001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2859388001
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.689853691
Short name T719
Test name
Test status
Simulation time 5888702016 ps
CPU time 13.52 seconds
Started May 26 02:34:47 PM PDT 24
Finished May 26 02:35:01 PM PDT 24
Peak memory 201684 kb
Host smart-3ac5181d-c390-42f1-8264-0cdef65e11d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689853691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.689853691
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.1818535984
Short name T171
Test name
Test status
Simulation time 440536287642 ps
CPU time 878.66 seconds
Started May 26 02:35:04 PM PDT 24
Finished May 26 02:49:44 PM PDT 24
Peak memory 212744 kb
Host smart-78751c2f-9afc-4752-b1ba-050dc681e29f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818535984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.1818535984
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1690494226
Short name T100
Test name
Test status
Simulation time 416069195092 ps
CPU time 327.6 seconds
Started May 26 02:34:56 PM PDT 24
Finished May 26 02:40:24 PM PDT 24
Peak memory 218224 kb
Host smart-4c0898d9-7ec4-41c5-b775-8d834c80ab66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690494226 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1690494226
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3304800644
Short name T701
Test name
Test status
Simulation time 504537319 ps
CPU time 1.2 seconds
Started May 26 02:35:10 PM PDT 24
Finished May 26 02:35:12 PM PDT 24
Peak memory 201456 kb
Host smart-a4cc9416-9e21-4547-afc3-de21ddd90069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304800644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3304800644
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3060172920
Short name T278
Test name
Test status
Simulation time 168800455650 ps
CPU time 232.3 seconds
Started May 26 02:35:04 PM PDT 24
Finished May 26 02:38:57 PM PDT 24
Peak memory 201844 kb
Host smart-ca340d4a-f5fc-4cf2-ac80-d03a790f379c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060172920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3060172920
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1780369977
Short name T160
Test name
Test status
Simulation time 330633236485 ps
CPU time 184.61 seconds
Started May 26 02:35:03 PM PDT 24
Finished May 26 02:38:09 PM PDT 24
Peak memory 201908 kb
Host smart-c58fa426-3b05-4e2b-93a4-09e3ee769406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780369977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1780369977
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.694769246
Short name T572
Test name
Test status
Simulation time 166332399506 ps
CPU time 75.01 seconds
Started May 26 02:35:02 PM PDT 24
Finished May 26 02:36:18 PM PDT 24
Peak memory 201812 kb
Host smart-a0572392-ef42-4ebb-9505-0f6aa01f3de6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=694769246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.694769246
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1514488940
Short name T184
Test name
Test status
Simulation time 491114499984 ps
CPU time 558.2 seconds
Started May 26 02:35:04 PM PDT 24
Finished May 26 02:44:23 PM PDT 24
Peak memory 201820 kb
Host smart-72804cce-badd-46b9-b8d7-44f9f37ec3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514488940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1514488940
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2177788864
Short name T565
Test name
Test status
Simulation time 170815763853 ps
CPU time 102.82 seconds
Started May 26 02:35:03 PM PDT 24
Finished May 26 02:36:47 PM PDT 24
Peak memory 201796 kb
Host smart-e06d2f1e-0a7e-43fa-bcb2-c1f0f60cefc0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177788864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2177788864
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2367871754
Short name T614
Test name
Test status
Simulation time 375117963263 ps
CPU time 874 seconds
Started May 26 02:35:03 PM PDT 24
Finished May 26 02:49:38 PM PDT 24
Peak memory 201888 kb
Host smart-68206b97-3696-433b-b6f3-0818af1ab6d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367871754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2367871754
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1826600018
Short name T429
Test name
Test status
Simulation time 202857977662 ps
CPU time 485.41 seconds
Started May 26 02:35:04 PM PDT 24
Finished May 26 02:43:10 PM PDT 24
Peak memory 201836 kb
Host smart-af345076-2b70-4ce8-90d1-9a8665182995
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826600018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1826600018
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.1500458432
Short name T405
Test name
Test status
Simulation time 90919167244 ps
CPU time 459.21 seconds
Started May 26 02:35:11 PM PDT 24
Finished May 26 02:42:50 PM PDT 24
Peak memory 202152 kb
Host smart-d24e2bde-6b08-467b-92eb-449efe55c779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500458432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1500458432
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2095455091
Short name T613
Test name
Test status
Simulation time 22989237454 ps
CPU time 50.97 seconds
Started May 26 02:35:04 PM PDT 24
Finished May 26 02:35:56 PM PDT 24
Peak memory 201664 kb
Host smart-1beef171-63bd-4c5f-afb0-45abb4b9f121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095455091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2095455091
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3460723260
Short name T371
Test name
Test status
Simulation time 4532046651 ps
CPU time 10.69 seconds
Started May 26 02:35:02 PM PDT 24
Finished May 26 02:35:14 PM PDT 24
Peak memory 201648 kb
Host smart-0df237d5-df76-4991-af30-dbd0c05400ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460723260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3460723260
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3468404595
Short name T105
Test name
Test status
Simulation time 5715194336 ps
CPU time 4.37 seconds
Started May 26 02:35:02 PM PDT 24
Finished May 26 02:35:06 PM PDT 24
Peak memory 201676 kb
Host smart-1fb2d276-ec63-49c5-b179-339b267222cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468404595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3468404595
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3192088002
Short name T281
Test name
Test status
Simulation time 665571086751 ps
CPU time 576.51 seconds
Started May 26 02:35:10 PM PDT 24
Finished May 26 02:44:47 PM PDT 24
Peak memory 201868 kb
Host smart-d05bc04e-f985-46ee-a293-618b43e31ba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192088002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3192088002
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2881435428
Short name T546
Test name
Test status
Simulation time 427064696 ps
CPU time 1.62 seconds
Started May 26 02:35:21 PM PDT 24
Finished May 26 02:35:24 PM PDT 24
Peak memory 201416 kb
Host smart-a6a750ec-cb43-41cc-8dc0-69de5ea8239c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881435428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2881435428
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3835237101
Short name T93
Test name
Test status
Simulation time 543301412869 ps
CPU time 50.95 seconds
Started May 26 02:35:19 PM PDT 24
Finished May 26 02:36:10 PM PDT 24
Peak memory 201848 kb
Host smart-b01689bc-9ee3-4008-919c-597dd6d643cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835237101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3835237101
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3787695919
Short name T770
Test name
Test status
Simulation time 165804836018 ps
CPU time 374.56 seconds
Started May 26 02:35:18 PM PDT 24
Finished May 26 02:41:34 PM PDT 24
Peak memory 201828 kb
Host smart-e7f53dfe-5de5-4fe9-9520-1311c2c5fc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787695919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3787695919
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3613144184
Short name T224
Test name
Test status
Simulation time 329714427361 ps
CPU time 849.07 seconds
Started May 26 02:35:14 PM PDT 24
Finished May 26 02:49:24 PM PDT 24
Peak memory 201932 kb
Host smart-a87ac0c9-982c-4873-9818-249273200064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613144184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3613144184
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1091195545
Short name T616
Test name
Test status
Simulation time 497645043705 ps
CPU time 621.91 seconds
Started May 26 02:35:10 PM PDT 24
Finished May 26 02:45:33 PM PDT 24
Peak memory 201844 kb
Host smart-ffc42c6a-1c06-422b-91de-6c6346c51817
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091195545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1091195545
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3788648325
Short name T720
Test name
Test status
Simulation time 322679660840 ps
CPU time 203.01 seconds
Started May 26 02:35:12 PM PDT 24
Finished May 26 02:38:35 PM PDT 24
Peak memory 201700 kb
Host smart-6db11cf0-5c12-4948-8e0c-79ba67457d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788648325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3788648325
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3259832504
Short name T633
Test name
Test status
Simulation time 159815619191 ps
CPU time 365.09 seconds
Started May 26 02:35:10 PM PDT 24
Finished May 26 02:41:15 PM PDT 24
Peak memory 201820 kb
Host smart-5d6a1bec-1df7-42eb-894e-218f7ec56d48
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259832504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3259832504
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2671535925
Short name T159
Test name
Test status
Simulation time 546845885951 ps
CPU time 190.61 seconds
Started May 26 02:35:18 PM PDT 24
Finished May 26 02:38:30 PM PDT 24
Peak memory 201880 kb
Host smart-96c81e12-1c1f-41a4-88b3-e965805760a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671535925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2671535925
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.164165014
Short name T454
Test name
Test status
Simulation time 406744349141 ps
CPU time 944.09 seconds
Started May 26 02:35:19 PM PDT 24
Finished May 26 02:51:04 PM PDT 24
Peak memory 201924 kb
Host smart-a5e7c071-afbf-4b7a-8506-ba55505e01ea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164165014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.164165014
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2134780001
Short name T101
Test name
Test status
Simulation time 107641220365 ps
CPU time 485.87 seconds
Started May 26 02:35:18 PM PDT 24
Finished May 26 02:43:25 PM PDT 24
Peak memory 202220 kb
Host smart-f1ec8924-9590-405e-bd1b-444b07d279b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134780001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2134780001
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3684002622
Short name T591
Test name
Test status
Simulation time 42827126973 ps
CPU time 50.33 seconds
Started May 26 02:35:18 PM PDT 24
Finished May 26 02:36:08 PM PDT 24
Peak memory 201672 kb
Host smart-e0e4e5ee-d6eb-4f27-a6ac-b3ecf8a74111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684002622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3684002622
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.4273814507
Short name T539
Test name
Test status
Simulation time 2959215965 ps
CPU time 1.77 seconds
Started May 26 02:35:19 PM PDT 24
Finished May 26 02:35:21 PM PDT 24
Peak memory 201584 kb
Host smart-65006df6-17c7-4f5a-9d8b-5d9c140894f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273814507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.4273814507
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3965383184
Short name T700
Test name
Test status
Simulation time 5879934969 ps
CPU time 13.63 seconds
Started May 26 02:35:10 PM PDT 24
Finished May 26 02:35:25 PM PDT 24
Peak memory 201668 kb
Host smart-bc69bfa1-7c4c-4fcb-bc49-50658ca3b1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965383184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3965383184
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1825607914
Short name T233
Test name
Test status
Simulation time 511753642372 ps
CPU time 1198.68 seconds
Started May 26 02:35:20 PM PDT 24
Finished May 26 02:55:20 PM PDT 24
Peak memory 201936 kb
Host smart-a74fc0e1-5020-4345-8e1c-cc678701504f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825607914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1825607914
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2269601493
Short name T23
Test name
Test status
Simulation time 670463159931 ps
CPU time 342.73 seconds
Started May 26 02:35:21 PM PDT 24
Finished May 26 02:41:04 PM PDT 24
Peak memory 218460 kb
Host smart-5286272a-9d03-4d55-ae5a-da4cfb35c2d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269601493 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2269601493
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1338424001
Short name T72
Test name
Test status
Simulation time 488668309 ps
CPU time 1.13 seconds
Started May 26 02:35:25 PM PDT 24
Finished May 26 02:35:27 PM PDT 24
Peak memory 201528 kb
Host smart-f636c60a-9906-4107-a464-0e066d48c3c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338424001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1338424001
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3882930077
Short name T675
Test name
Test status
Simulation time 383923454944 ps
CPU time 458.7 seconds
Started May 26 02:35:28 PM PDT 24
Finished May 26 02:43:07 PM PDT 24
Peak memory 201828 kb
Host smart-f756df9d-6d27-4c92-80a2-417abf67ffc2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882930077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3882930077
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.113107056
Short name T315
Test name
Test status
Simulation time 322128999930 ps
CPU time 201.78 seconds
Started May 26 02:35:20 PM PDT 24
Finished May 26 02:38:42 PM PDT 24
Peak memory 201848 kb
Host smart-d7b9c505-a79e-40c3-892d-321c8cbb5adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113107056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.113107056
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2115581717
Short name T455
Test name
Test status
Simulation time 162204040365 ps
CPU time 99.26 seconds
Started May 26 02:35:19 PM PDT 24
Finished May 26 02:36:59 PM PDT 24
Peak memory 201832 kb
Host smart-574ac46d-d465-49fc-a589-6e228ab633e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115581717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2115581717
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1591443091
Short name T797
Test name
Test status
Simulation time 161966277580 ps
CPU time 91.92 seconds
Started May 26 02:35:18 PM PDT 24
Finished May 26 02:36:50 PM PDT 24
Peak memory 201900 kb
Host smart-0cda1f50-db38-491c-892e-d9139881fe79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591443091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1591443091
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2073474889
Short name T684
Test name
Test status
Simulation time 491059155418 ps
CPU time 291.74 seconds
Started May 26 02:35:18 PM PDT 24
Finished May 26 02:40:11 PM PDT 24
Peak memory 201848 kb
Host smart-8fdc0de8-766a-49de-9173-4c3ca5496f3f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073474889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2073474889
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.258924775
Short name T220
Test name
Test status
Simulation time 529991785062 ps
CPU time 397.82 seconds
Started May 26 02:35:19 PM PDT 24
Finished May 26 02:41:58 PM PDT 24
Peak memory 201872 kb
Host smart-63c270d6-e5ce-4110-8da2-393debb62e6b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258924775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.258924775
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2252479994
Short name T691
Test name
Test status
Simulation time 194871022037 ps
CPU time 119.82 seconds
Started May 26 02:35:19 PM PDT 24
Finished May 26 02:37:20 PM PDT 24
Peak memory 201848 kb
Host smart-04e1638b-ef58-4972-9fea-e6b114aa08a5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252479994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2252479994
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1513757680
Short name T205
Test name
Test status
Simulation time 113633006441 ps
CPU time 532.86 seconds
Started May 26 02:35:25 PM PDT 24
Finished May 26 02:44:19 PM PDT 24
Peak memory 202060 kb
Host smart-812fba1e-41c3-44c8-83cc-31918137f4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513757680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1513757680
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.339899641
Short name T632
Test name
Test status
Simulation time 37825618945 ps
CPU time 21.67 seconds
Started May 26 02:35:25 PM PDT 24
Finished May 26 02:35:48 PM PDT 24
Peak memory 201692 kb
Host smart-7c244fbf-291f-4b79-917a-03a41c2da17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339899641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.339899641
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3274892517
Short name T387
Test name
Test status
Simulation time 4249224302 ps
CPU time 5.04 seconds
Started May 26 02:35:26 PM PDT 24
Finished May 26 02:35:32 PM PDT 24
Peak memory 201608 kb
Host smart-cac1231f-a2f5-4924-b7b7-f8b54fba91f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274892517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3274892517
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3656004676
Short name T745
Test name
Test status
Simulation time 5971300500 ps
CPU time 7.95 seconds
Started May 26 02:35:18 PM PDT 24
Finished May 26 02:35:27 PM PDT 24
Peak memory 201692 kb
Host smart-17c3e867-ef29-4c0c-b3f2-dbefd85f0864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656004676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3656004676
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.986656786
Short name T318
Test name
Test status
Simulation time 348288766252 ps
CPU time 201.1 seconds
Started May 26 02:35:25 PM PDT 24
Finished May 26 02:38:47 PM PDT 24
Peak memory 201992 kb
Host smart-f8639e14-787f-4e91-8cbb-fc14c4df9c47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986656786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
986656786
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2099383763
Short name T509
Test name
Test status
Simulation time 376978303 ps
CPU time 0.83 seconds
Started May 26 02:31:39 PM PDT 24
Finished May 26 02:31:41 PM PDT 24
Peak memory 201488 kb
Host smart-9cb09ea8-3e17-4023-9c58-d08751d3cd56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099383763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2099383763
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3434587265
Short name T731
Test name
Test status
Simulation time 498730697530 ps
CPU time 329.35 seconds
Started May 26 02:31:32 PM PDT 24
Finished May 26 02:37:02 PM PDT 24
Peak memory 201812 kb
Host smart-c948853b-bc0f-47fb-86f4-c3ae7596e839
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434587265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3434587265
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1684163295
Short name T222
Test name
Test status
Simulation time 491040273230 ps
CPU time 99.7 seconds
Started May 26 02:31:33 PM PDT 24
Finished May 26 02:33:14 PM PDT 24
Peak memory 201872 kb
Host smart-e2f49c9e-99c8-4733-bf6c-072045642239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684163295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1684163295
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.270988512
Short name T430
Test name
Test status
Simulation time 491188921774 ps
CPU time 301.2 seconds
Started May 26 02:31:46 PM PDT 24
Finished May 26 02:36:48 PM PDT 24
Peak memory 201304 kb
Host smart-1c01b3bd-3649-4590-8f99-b27faa348cc2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=270988512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt
_fixed.270988512
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1673349936
Short name T428
Test name
Test status
Simulation time 168458970989 ps
CPU time 56.17 seconds
Started May 26 02:31:33 PM PDT 24
Finished May 26 02:32:30 PM PDT 24
Peak memory 201840 kb
Host smart-d0dce653-d4a7-4f1e-9983-710cddad396f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673349936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1673349936
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2757344669
Short name T468
Test name
Test status
Simulation time 320861388513 ps
CPU time 717.41 seconds
Started May 26 02:31:35 PM PDT 24
Finished May 26 02:43:33 PM PDT 24
Peak memory 201856 kb
Host smart-f14e0a48-435c-46f5-a27a-3496d6efc49d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757344669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2757344669
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3438305617
Short name T217
Test name
Test status
Simulation time 201788263276 ps
CPU time 457.29 seconds
Started May 26 02:31:32 PM PDT 24
Finished May 26 02:39:10 PM PDT 24
Peak memory 201800 kb
Host smart-b4215e1a-8cbe-42ae-bd1e-56a3acf18f34
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438305617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3438305617
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1829778707
Short name T103
Test name
Test status
Simulation time 194027938857 ps
CPU time 115.29 seconds
Started May 26 02:31:35 PM PDT 24
Finished May 26 02:33:31 PM PDT 24
Peak memory 201856 kb
Host smart-54b3268c-160a-4b68-8374-015a858eb2c4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829778707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.1829778707
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1493724414
Short name T530
Test name
Test status
Simulation time 94899397681 ps
CPU time 354.28 seconds
Started May 26 02:31:39 PM PDT 24
Finished May 26 02:37:34 PM PDT 24
Peak memory 202152 kb
Host smart-6245924f-6c65-48e9-9730-66de4b1e035d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493724414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1493724414
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.3030830225
Short name T722
Test name
Test status
Simulation time 41679766838 ps
CPU time 91.29 seconds
Started May 26 02:31:40 PM PDT 24
Finished May 26 02:33:12 PM PDT 24
Peak memory 201828 kb
Host smart-2fb6b6d1-e1ff-49e6-acee-d252d2edf9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030830225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3030830225
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1367698288
Short name T98
Test name
Test status
Simulation time 5335802578 ps
CPU time 7.24 seconds
Started May 26 02:31:31 PM PDT 24
Finished May 26 02:31:39 PM PDT 24
Peak memory 201664 kb
Host smart-2ba5e252-6bf0-46da-9c0e-5cb97035ea62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367698288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1367698288
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.862929887
Short name T67
Test name
Test status
Simulation time 4151743590 ps
CPU time 5.22 seconds
Started May 26 02:31:39 PM PDT 24
Finished May 26 02:31:45 PM PDT 24
Peak memory 217224 kb
Host smart-a559d8c5-ff57-4f16-82da-0c745574fedd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862929887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.862929887
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2373452538
Short name T581
Test name
Test status
Simulation time 5623699083 ps
CPU time 13.33 seconds
Started May 26 02:31:32 PM PDT 24
Finished May 26 02:31:46 PM PDT 24
Peak memory 201692 kb
Host smart-90a60d96-8be5-4bfd-ae20-e174d3a17339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373452538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2373452538
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.4132159834
Short name T51
Test name
Test status
Simulation time 142470004474 ps
CPU time 579.6 seconds
Started May 26 02:31:40 PM PDT 24
Finished May 26 02:41:21 PM PDT 24
Peak memory 202196 kb
Host smart-12871c64-1d6c-4116-88d1-43df8db220d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132159834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
4132159834
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1611188818
Short name T456
Test name
Test status
Simulation time 357317291 ps
CPU time 1.5 seconds
Started May 26 02:35:33 PM PDT 24
Finished May 26 02:35:36 PM PDT 24
Peak memory 201576 kb
Host smart-ba7a14cb-4529-4ac9-9db3-73ad5a7bb369
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611188818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1611188818
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3400002478
Short name T289
Test name
Test status
Simulation time 353091214885 ps
CPU time 827.48 seconds
Started May 26 02:35:35 PM PDT 24
Finished May 26 02:49:24 PM PDT 24
Peak memory 201924 kb
Host smart-c52c5e95-11ac-4c21-8b7e-16ca807ab418
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400002478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3400002478
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.887756224
Short name T81
Test name
Test status
Simulation time 372713042244 ps
CPU time 137.61 seconds
Started May 26 02:35:32 PM PDT 24
Finished May 26 02:37:51 PM PDT 24
Peak memory 201860 kb
Host smart-bfde7dba-58b5-4a68-a0b1-603a3b9df3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887756224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.887756224
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1224965216
Short name T670
Test name
Test status
Simulation time 490313333295 ps
CPU time 591.9 seconds
Started May 26 02:35:30 PM PDT 24
Finished May 26 02:45:22 PM PDT 24
Peak memory 201848 kb
Host smart-71b53af7-fe86-44a2-9474-b6c7e4808293
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224965216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1224965216
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2616170601
Short name T683
Test name
Test status
Simulation time 329387990055 ps
CPU time 80.97 seconds
Started May 26 02:35:25 PM PDT 24
Finished May 26 02:36:47 PM PDT 24
Peak memory 201816 kb
Host smart-7898ff6b-0807-4568-8636-1d772e5440ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616170601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2616170601
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2817183927
Short name T172
Test name
Test status
Simulation time 495235921435 ps
CPU time 298.72 seconds
Started May 26 02:35:26 PM PDT 24
Finished May 26 02:40:25 PM PDT 24
Peak memory 201812 kb
Host smart-765a453d-3eaf-4a84-a446-1ee090e9ade7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817183927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2817183927
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.2904318534
Short name T305
Test name
Test status
Simulation time 187874490994 ps
CPU time 50.08 seconds
Started May 26 02:35:29 PM PDT 24
Finished May 26 02:36:20 PM PDT 24
Peak memory 201944 kb
Host smart-67b5e024-37c8-406d-99ad-0d82a8698a8d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904318534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.2904318534
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3201836973
Short name T762
Test name
Test status
Simulation time 213060194395 ps
CPU time 489.9 seconds
Started May 26 02:35:33 PM PDT 24
Finished May 26 02:43:45 PM PDT 24
Peak memory 201856 kb
Host smart-6921d5e5-c5e7-46b8-bea5-14b3d1375f99
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201836973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3201836973
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1391967338
Short name T52
Test name
Test status
Simulation time 130309973345 ps
CPU time 686.67 seconds
Started May 26 02:35:35 PM PDT 24
Finished May 26 02:47:04 PM PDT 24
Peak memory 202152 kb
Host smart-a45f93b7-1ad4-4573-a9c8-0899b57b3ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391967338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1391967338
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1324859934
Short name T773
Test name
Test status
Simulation time 30348643592 ps
CPU time 72.55 seconds
Started May 26 02:35:32 PM PDT 24
Finished May 26 02:36:46 PM PDT 24
Peak memory 201632 kb
Host smart-87b5668f-3667-491b-91b6-c51cf237467c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324859934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1324859934
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.694821148
Short name T680
Test name
Test status
Simulation time 5238228260 ps
CPU time 12.75 seconds
Started May 26 02:35:36 PM PDT 24
Finished May 26 02:35:50 PM PDT 24
Peak memory 201536 kb
Host smart-4635c092-fc3c-410a-b7c2-8795ffc868fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694821148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.694821148
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.894046343
Short name T535
Test name
Test status
Simulation time 5647177983 ps
CPU time 4.11 seconds
Started May 26 02:35:25 PM PDT 24
Finished May 26 02:35:30 PM PDT 24
Peak memory 201704 kb
Host smart-edb63867-7e05-4cd1-94d8-25147fc3a27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894046343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.894046343
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3648016583
Short name T49
Test name
Test status
Simulation time 46863441554 ps
CPU time 12.67 seconds
Started May 26 02:35:33 PM PDT 24
Finished May 26 02:35:47 PM PDT 24
Peak memory 201672 kb
Host smart-f969a20b-817f-4c87-8c96-4cf7976c50bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648016583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3648016583
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2027898282
Short name T492
Test name
Test status
Simulation time 31076130022 ps
CPU time 76.48 seconds
Started May 26 02:35:32 PM PDT 24
Finished May 26 02:36:49 PM PDT 24
Peak memory 201984 kb
Host smart-9309c564-6ffa-4e1e-8499-2444f01ffd06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027898282 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2027898282
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2657663303
Short name T582
Test name
Test status
Simulation time 343320307 ps
CPU time 1.3 seconds
Started May 26 02:35:48 PM PDT 24
Finished May 26 02:35:50 PM PDT 24
Peak memory 201536 kb
Host smart-74fdfbf4-123d-4227-b2b7-ddaf2eefe316
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657663303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2657663303
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1801897212
Short name T218
Test name
Test status
Simulation time 511061791384 ps
CPU time 485.98 seconds
Started May 26 02:35:42 PM PDT 24
Finished May 26 02:43:49 PM PDT 24
Peak memory 201928 kb
Host smart-15314598-0819-47e1-8151-81cf8971f765
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801897212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1801897212
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2933960229
Short name T328
Test name
Test status
Simulation time 497184038999 ps
CPU time 314.34 seconds
Started May 26 02:35:40 PM PDT 24
Finished May 26 02:40:56 PM PDT 24
Peak memory 201832 kb
Host smart-511cb260-8479-4a50-a0bb-c69b83bcdb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933960229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2933960229
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.4025007616
Short name T102
Test name
Test status
Simulation time 161815174455 ps
CPU time 102.02 seconds
Started May 26 02:35:41 PM PDT 24
Finished May 26 02:37:24 PM PDT 24
Peak memory 201868 kb
Host smart-46644fc0-6792-46e0-8472-b3bd9ae3a752
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025007616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.4025007616
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3849046710
Short name T297
Test name
Test status
Simulation time 161856061703 ps
CPU time 90.94 seconds
Started May 26 02:35:45 PM PDT 24
Finished May 26 02:37:17 PM PDT 24
Peak memory 201868 kb
Host smart-e8e600cf-2c5f-461b-be12-ede32c3e4e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849046710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3849046710
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.233149874
Short name T354
Test name
Test status
Simulation time 324951354857 ps
CPU time 794.79 seconds
Started May 26 02:35:41 PM PDT 24
Finished May 26 02:48:57 PM PDT 24
Peak memory 201856 kb
Host smart-2b49a94e-484c-4da3-848b-8c3247d903c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=233149874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixe
d.233149874
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3815762502
Short name T484
Test name
Test status
Simulation time 376655163627 ps
CPU time 544.58 seconds
Started May 26 02:35:40 PM PDT 24
Finished May 26 02:44:46 PM PDT 24
Peak memory 201908 kb
Host smart-b5a533f2-09b3-41c7-b0cc-baab03b5fd2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815762502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3815762502
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.935429855
Short name T577
Test name
Test status
Simulation time 199032837110 ps
CPU time 122.09 seconds
Started May 26 02:35:40 PM PDT 24
Finished May 26 02:37:44 PM PDT 24
Peak memory 201820 kb
Host smart-71bec090-5ae3-42ea-b4c3-e1e570924483
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935429855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.935429855
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1403693342
Short name T496
Test name
Test status
Simulation time 114468148782 ps
CPU time 472.26 seconds
Started May 26 02:35:40 PM PDT 24
Finished May 26 02:43:34 PM PDT 24
Peak memory 202128 kb
Host smart-500f1f5c-1390-4e9e-820e-182ec7273362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403693342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1403693342
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3146799728
Short name T449
Test name
Test status
Simulation time 33192085816 ps
CPU time 20.27 seconds
Started May 26 02:35:44 PM PDT 24
Finished May 26 02:36:05 PM PDT 24
Peak memory 201640 kb
Host smart-916036c7-b7b1-436c-9e95-77148810d004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146799728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3146799728
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2372636028
Short name T507
Test name
Test status
Simulation time 3597104678 ps
CPU time 4.91 seconds
Started May 26 02:35:42 PM PDT 24
Finished May 26 02:35:48 PM PDT 24
Peak memory 201592 kb
Host smart-96f19cec-8733-4fab-b151-bec1e401c8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372636028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2372636028
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1347900953
Short name T471
Test name
Test status
Simulation time 5689276469 ps
CPU time 13.21 seconds
Started May 26 02:35:35 PM PDT 24
Finished May 26 02:35:49 PM PDT 24
Peak memory 201688 kb
Host smart-d7fc8472-404e-45db-8138-4c7a3e0108a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347900953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1347900953
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2637885013
Short name T194
Test name
Test status
Simulation time 333901243371 ps
CPU time 392.69 seconds
Started May 26 02:35:41 PM PDT 24
Finished May 26 02:42:15 PM PDT 24
Peak memory 201840 kb
Host smart-1d0e2f89-60ce-4f38-9137-e2eb80ccb4be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637885013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2637885013
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3932604242
Short name T46
Test name
Test status
Simulation time 73373293395 ps
CPU time 154.77 seconds
Started May 26 02:35:40 PM PDT 24
Finished May 26 02:38:16 PM PDT 24
Peak memory 218636 kb
Host smart-af92b58c-2e68-4003-92dc-02e555ebbce0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932604242 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3932604242
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3008024398
Short name T766
Test name
Test status
Simulation time 447990864 ps
CPU time 1.27 seconds
Started May 26 02:35:47 PM PDT 24
Finished May 26 02:35:49 PM PDT 24
Peak memory 201540 kb
Host smart-ce0413dc-a84d-45b1-b1dd-747aff4926c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008024398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3008024398
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3936409615
Short name T265
Test name
Test status
Simulation time 169673436107 ps
CPU time 117.44 seconds
Started May 26 02:35:51 PM PDT 24
Finished May 26 02:37:49 PM PDT 24
Peak memory 201908 kb
Host smart-f754417d-9ca5-4f21-b009-442457c8d7c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936409615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3936409615
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2778810278
Short name T183
Test name
Test status
Simulation time 164457374616 ps
CPU time 88.28 seconds
Started May 26 02:35:50 PM PDT 24
Finished May 26 02:37:19 PM PDT 24
Peak memory 201756 kb
Host smart-e6fc4815-adda-4525-8b1d-ffa3e80d534b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778810278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2778810278
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2161936390
Short name T605
Test name
Test status
Simulation time 494743255956 ps
CPU time 596.65 seconds
Started May 26 02:35:47 PM PDT 24
Finished May 26 02:45:44 PM PDT 24
Peak memory 201796 kb
Host smart-4d72ab48-9df8-44a6-b70b-9a09bdf87c6d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161936390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2161936390
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2217973165
Short name T324
Test name
Test status
Simulation time 496112636775 ps
CPU time 1101.76 seconds
Started May 26 02:35:53 PM PDT 24
Finished May 26 02:54:16 PM PDT 24
Peak memory 201824 kb
Host smart-7859b788-2b5a-42e7-aee1-a465759f1dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217973165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2217973165
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2728391074
Short name T390
Test name
Test status
Simulation time 499064132001 ps
CPU time 82.96 seconds
Started May 26 02:35:49 PM PDT 24
Finished May 26 02:37:13 PM PDT 24
Peak memory 201824 kb
Host smart-2879d101-a660-4c0f-8e02-6161e14ebd44
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728391074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2728391074
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.742810103
Short name T319
Test name
Test status
Simulation time 179409576780 ps
CPU time 421.48 seconds
Started May 26 02:35:52 PM PDT 24
Finished May 26 02:42:54 PM PDT 24
Peak memory 201844 kb
Host smart-e7319810-b6fa-4062-bc3a-bc6a65a56b39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742810103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.742810103
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1752944943
Short name T441
Test name
Test status
Simulation time 197521506545 ps
CPU time 35.48 seconds
Started May 26 02:35:49 PM PDT 24
Finished May 26 02:36:26 PM PDT 24
Peak memory 201848 kb
Host smart-edd7c9fc-878d-432b-bc4c-fe758d34e9dc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752944943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1752944943
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.949473267
Short name T481
Test name
Test status
Simulation time 76664394568 ps
CPU time 342.36 seconds
Started May 26 02:35:48 PM PDT 24
Finished May 26 02:41:31 PM PDT 24
Peak memory 202192 kb
Host smart-d452cb06-a247-4ceb-bf77-bdd2d2e2da18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949473267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.949473267
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.725573695
Short name T45
Test name
Test status
Simulation time 42794667653 ps
CPU time 51.47 seconds
Started May 26 02:35:49 PM PDT 24
Finished May 26 02:36:41 PM PDT 24
Peak memory 201664 kb
Host smart-8b825197-b125-499e-bf2d-bcf5904e0a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725573695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.725573695
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1900269444
Short name T522
Test name
Test status
Simulation time 4226612998 ps
CPU time 10.82 seconds
Started May 26 02:35:49 PM PDT 24
Finished May 26 02:36:00 PM PDT 24
Peak memory 201620 kb
Host smart-e829256f-751a-4bde-a88f-b585fc5bc142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900269444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1900269444
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1744047850
Short name T401
Test name
Test status
Simulation time 5979062332 ps
CPU time 10.73 seconds
Started May 26 02:35:49 PM PDT 24
Finished May 26 02:36:01 PM PDT 24
Peak memory 201676 kb
Host smart-736118ae-22b2-4893-9997-c04fcf7c4f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744047850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1744047850
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1492992740
Short name T617
Test name
Test status
Simulation time 1115109859 ps
CPU time 1.31 seconds
Started May 26 02:35:51 PM PDT 24
Finished May 26 02:35:53 PM PDT 24
Peak memory 201460 kb
Host smart-1e25af26-10c9-4a3b-baf1-6ab73eb2feaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492992740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1492992740
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1403926021
Short name T792
Test name
Test status
Simulation time 62591552946 ps
CPU time 127.82 seconds
Started May 26 02:35:48 PM PDT 24
Finished May 26 02:37:57 PM PDT 24
Peak memory 210836 kb
Host smart-1341b169-f823-4a05-a5d1-f6ad0c13dfdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403926021 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1403926021
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3940109883
Short name T364
Test name
Test status
Simulation time 497093876 ps
CPU time 1.63 seconds
Started May 26 02:36:03 PM PDT 24
Finished May 26 02:36:06 PM PDT 24
Peak memory 201528 kb
Host smart-51fd82ee-eb27-47a6-bdf0-b85a84762475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940109883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3940109883
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1180452567
Short name T630
Test name
Test status
Simulation time 197915103646 ps
CPU time 67.86 seconds
Started May 26 02:36:03 PM PDT 24
Finished May 26 02:37:12 PM PDT 24
Peak memory 201716 kb
Host smart-c67f0e2c-4ebb-4528-990b-f083ef61702d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180452567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1180452567
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.871314515
Short name T606
Test name
Test status
Simulation time 162232963317 ps
CPU time 386.93 seconds
Started May 26 02:36:04 PM PDT 24
Finished May 26 02:42:32 PM PDT 24
Peak memory 201860 kb
Host smart-1bff66a9-0ef9-4c1a-bf85-7ccd547010c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871314515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.871314515
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3700328631
Short name T214
Test name
Test status
Simulation time 487168471088 ps
CPU time 418.33 seconds
Started May 26 02:35:54 PM PDT 24
Finished May 26 02:42:53 PM PDT 24
Peak memory 201836 kb
Host smart-b8dc9688-c226-4525-ab63-5fc9689837a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700328631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3700328631
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1820657410
Short name T431
Test name
Test status
Simulation time 321052079975 ps
CPU time 65.25 seconds
Started May 26 02:35:55 PM PDT 24
Finished May 26 02:37:00 PM PDT 24
Peak memory 201856 kb
Host smart-dfd4805c-f420-415a-a4b6-542dd17eb7df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820657410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1820657410
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3222259179
Short name T777
Test name
Test status
Simulation time 331848612208 ps
CPU time 228.99 seconds
Started May 26 02:35:57 PM PDT 24
Finished May 26 02:39:46 PM PDT 24
Peak memory 201816 kb
Host smart-396468f1-16fd-4f5b-ac3f-a37dc9fcecff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222259179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3222259179
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2530416671
Short name T550
Test name
Test status
Simulation time 495994112469 ps
CPU time 1128.71 seconds
Started May 26 02:35:53 PM PDT 24
Finished May 26 02:54:43 PM PDT 24
Peak memory 201808 kb
Host smart-fe29f482-ca15-430f-a45f-ce2c76d8100d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530416671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2530416671
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3169338880
Short name T543
Test name
Test status
Simulation time 561190271164 ps
CPU time 677.52 seconds
Started May 26 02:35:56 PM PDT 24
Finished May 26 02:47:14 PM PDT 24
Peak memory 201924 kb
Host smart-2dbd9855-2898-4af7-aa70-c23a9d0c3f2d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169338880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3169338880
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.745103717
Short name T790
Test name
Test status
Simulation time 403337857430 ps
CPU time 909.48 seconds
Started May 26 02:35:56 PM PDT 24
Finished May 26 02:51:06 PM PDT 24
Peak memory 201840 kb
Host smart-0d45a738-e807-430f-a2d1-b4d0940b7d9c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745103717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.745103717
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.930633182
Short name T637
Test name
Test status
Simulation time 78345977571 ps
CPU time 322.41 seconds
Started May 26 02:36:04 PM PDT 24
Finished May 26 02:41:27 PM PDT 24
Peak memory 202108 kb
Host smart-9ebd6f09-0952-4719-8fa3-a3de7ad18a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930633182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.930633182
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3537460334
Short name T384
Test name
Test status
Simulation time 44572479858 ps
CPU time 24.05 seconds
Started May 26 02:36:03 PM PDT 24
Finished May 26 02:36:28 PM PDT 24
Peak memory 201688 kb
Host smart-0913e444-a711-4db7-b195-87cdbcb351e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537460334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3537460334
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2416473511
Short name T450
Test name
Test status
Simulation time 3825607585 ps
CPU time 2.89 seconds
Started May 26 02:36:05 PM PDT 24
Finished May 26 02:36:09 PM PDT 24
Peak memory 201604 kb
Host smart-44d89037-9589-4c21-89af-fcff09313b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416473511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2416473511
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.772815288
Short name T585
Test name
Test status
Simulation time 6007152738 ps
CPU time 15.54 seconds
Started May 26 02:35:54 PM PDT 24
Finished May 26 02:36:10 PM PDT 24
Peak memory 201700 kb
Host smart-bf3fd55e-a0a8-4382-99de-0cdfa46c1cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772815288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.772815288
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.167518797
Short name T730
Test name
Test status
Simulation time 528041267 ps
CPU time 0.94 seconds
Started May 26 02:36:10 PM PDT 24
Finished May 26 02:36:13 PM PDT 24
Peak memory 201704 kb
Host smart-c34c2be5-72d7-425c-ae83-dfaae1ffc8fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167518797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.167518797
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2457148629
Short name T510
Test name
Test status
Simulation time 329321974294 ps
CPU time 761.21 seconds
Started May 26 02:36:11 PM PDT 24
Finished May 26 02:48:54 PM PDT 24
Peak memory 201936 kb
Host smart-a856b86e-9f4b-44e5-91a6-dab5f4e6ee18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457148629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2457148629
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.4198535575
Short name T336
Test name
Test status
Simulation time 160170818363 ps
CPU time 375.43 seconds
Started May 26 02:36:09 PM PDT 24
Finished May 26 02:42:25 PM PDT 24
Peak memory 201868 kb
Host smart-ae68f625-3698-432d-9f9a-a70e488814e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198535575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.4198535575
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2096410458
Short name T445
Test name
Test status
Simulation time 159981966959 ps
CPU time 366.1 seconds
Started May 26 02:36:13 PM PDT 24
Finished May 26 02:42:20 PM PDT 24
Peak memory 201852 kb
Host smart-c243e72c-dd17-4f9a-8661-248fe9b9f415
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096410458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2096410458
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3867571995
Short name T754
Test name
Test status
Simulation time 329665960263 ps
CPU time 708.12 seconds
Started May 26 02:36:05 PM PDT 24
Finished May 26 02:47:54 PM PDT 24
Peak memory 201748 kb
Host smart-2fe29089-b6c3-4ba7-ae53-aff9e997f350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867571995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3867571995
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3414379755
Short name T491
Test name
Test status
Simulation time 493242830644 ps
CPU time 274.14 seconds
Started May 26 02:36:10 PM PDT 24
Finished May 26 02:40:46 PM PDT 24
Peak memory 201800 kb
Host smart-526bd2eb-8f6c-4f31-8676-d19a6ad55486
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414379755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3414379755
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1177638069
Short name T624
Test name
Test status
Simulation time 595595506587 ps
CPU time 439.65 seconds
Started May 26 02:36:12 PM PDT 24
Finished May 26 02:43:33 PM PDT 24
Peak memory 201840 kb
Host smart-07dc7e1b-8b94-4167-8d99-ee07459f87d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177638069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1177638069
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1346133862
Short name T690
Test name
Test status
Simulation time 583542558528 ps
CPU time 1388.44 seconds
Started May 26 02:36:10 PM PDT 24
Finished May 26 02:59:20 PM PDT 24
Peak memory 201868 kb
Host smart-dedcf353-dc69-4af3-a28c-251382723786
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346133862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1346133862
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1603669867
Short name T204
Test name
Test status
Simulation time 135483935205 ps
CPU time 471.65 seconds
Started May 26 02:36:10 PM PDT 24
Finished May 26 02:44:03 PM PDT 24
Peak memory 202196 kb
Host smart-35d64546-d55b-4930-9c1d-e01da82c335b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603669867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1603669867
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3686418863
Short name T375
Test name
Test status
Simulation time 39130556488 ps
CPU time 24.16 seconds
Started May 26 02:36:09 PM PDT 24
Finished May 26 02:36:35 PM PDT 24
Peak memory 201628 kb
Host smart-b09309a5-aaec-4de3-b508-c3734e4db11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686418863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3686418863
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1371381155
Short name T794
Test name
Test status
Simulation time 2791865451 ps
CPU time 2.19 seconds
Started May 26 02:36:09 PM PDT 24
Finished May 26 02:36:13 PM PDT 24
Peak memory 201628 kb
Host smart-13e45061-f8ea-418f-b725-8dd004ee0254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371381155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1371381155
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.4230345679
Short name T672
Test name
Test status
Simulation time 5588521483 ps
CPU time 4.2 seconds
Started May 26 02:36:10 PM PDT 24
Finished May 26 02:36:15 PM PDT 24
Peak memory 201696 kb
Host smart-1da20e30-962f-45e4-b151-0bddd3fe35af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230345679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.4230345679
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1437212588
Short name T653
Test name
Test status
Simulation time 172838925316 ps
CPU time 586.65 seconds
Started May 26 02:36:09 PM PDT 24
Finished May 26 02:45:58 PM PDT 24
Peak memory 202172 kb
Host smart-c38a7140-9562-461e-9eb7-1805c20520b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437212588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1437212588
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.4125181639
Short name T417
Test name
Test status
Simulation time 409587842 ps
CPU time 1.07 seconds
Started May 26 02:36:31 PM PDT 24
Finished May 26 02:36:33 PM PDT 24
Peak memory 201564 kb
Host smart-071580ff-0534-40a5-b209-77ab7b65446d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125181639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.4125181639
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2437931326
Short name T711
Test name
Test status
Simulation time 199100222205 ps
CPU time 81.54 seconds
Started May 26 02:36:18 PM PDT 24
Finished May 26 02:37:40 PM PDT 24
Peak memory 201860 kb
Host smart-9ffbf2d2-a7ea-416f-80ec-b0b8c2c1b76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437931326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2437931326
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.180939862
Short name T761
Test name
Test status
Simulation time 321945593906 ps
CPU time 386.37 seconds
Started May 26 02:36:17 PM PDT 24
Finished May 26 02:42:45 PM PDT 24
Peak memory 201856 kb
Host smart-337d808a-69ab-44f1-b8db-eff7aba63265
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=180939862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrup
t_fixed.180939862
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1656637903
Short name T601
Test name
Test status
Simulation time 161416583575 ps
CPU time 98.86 seconds
Started May 26 02:36:10 PM PDT 24
Finished May 26 02:37:50 PM PDT 24
Peak memory 201816 kb
Host smart-0b168ffe-3c68-4346-8264-a1ee80a8b9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656637903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1656637903
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3980312737
Short name T771
Test name
Test status
Simulation time 326468762183 ps
CPU time 377.36 seconds
Started May 26 02:36:11 PM PDT 24
Finished May 26 02:42:30 PM PDT 24
Peak memory 201820 kb
Host smart-9c54f388-8d9f-4c96-90b1-7b0df1d3a365
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980312737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3980312737
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2037020956
Short name T275
Test name
Test status
Simulation time 193791229227 ps
CPU time 427.65 seconds
Started May 26 02:36:18 PM PDT 24
Finished May 26 02:43:27 PM PDT 24
Peak memory 201920 kb
Host smart-e8570a14-ed17-4417-9742-b729d086fefb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037020956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2037020956
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3916701687
Short name T433
Test name
Test status
Simulation time 611898468715 ps
CPU time 274.12 seconds
Started May 26 02:36:18 PM PDT 24
Finished May 26 02:40:53 PM PDT 24
Peak memory 201748 kb
Host smart-34c9fdbc-9135-487f-840e-3d25a3adec2d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916701687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3916701687
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2011836745
Short name T54
Test name
Test status
Simulation time 68360560135 ps
CPU time 271.52 seconds
Started May 26 02:36:28 PM PDT 24
Finished May 26 02:41:00 PM PDT 24
Peak memory 202192 kb
Host smart-e101b6be-d153-4612-901d-f6f86d3707b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011836745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2011836745
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2775997219
Short name T783
Test name
Test status
Simulation time 37566716078 ps
CPU time 47.14 seconds
Started May 26 02:36:29 PM PDT 24
Finished May 26 02:37:17 PM PDT 24
Peak memory 201676 kb
Host smart-2a8da8f3-f212-40df-aa22-373e05688055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775997219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2775997219
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3201508940
Short name T698
Test name
Test status
Simulation time 3749438163 ps
CPU time 9.49 seconds
Started May 26 02:36:18 PM PDT 24
Finished May 26 02:36:29 PM PDT 24
Peak memory 201600 kb
Host smart-12666235-23d9-4f21-910e-2bd15eb3cfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201508940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3201508940
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.4247554423
Short name T434
Test name
Test status
Simulation time 5956690180 ps
CPU time 14.91 seconds
Started May 26 02:36:10 PM PDT 24
Finished May 26 02:36:27 PM PDT 24
Peak memory 201652 kb
Host smart-8f17551f-a27c-4981-a6f0-aadf25066ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247554423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.4247554423
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2094062800
Short name T95
Test name
Test status
Simulation time 10953806138 ps
CPU time 31.68 seconds
Started May 26 02:36:29 PM PDT 24
Finished May 26 02:37:01 PM PDT 24
Peak memory 210460 kb
Host smart-c0234fca-f2a2-45ff-8172-0d6e950eabb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094062800 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2094062800
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3145077992
Short name T373
Test name
Test status
Simulation time 465944715 ps
CPU time 1.14 seconds
Started May 26 02:36:41 PM PDT 24
Finished May 26 02:36:43 PM PDT 24
Peak memory 201544 kb
Host smart-11750128-ef80-4e8b-810a-d3e0636f487b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145077992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3145077992
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3064410979
Short name T238
Test name
Test status
Simulation time 160371243836 ps
CPU time 361.34 seconds
Started May 26 02:36:28 PM PDT 24
Finished May 26 02:42:31 PM PDT 24
Peak memory 201860 kb
Host smart-74bb6d89-e3dc-4432-945f-db2c1906c841
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064410979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3064410979
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1762662396
Short name T519
Test name
Test status
Simulation time 162930752182 ps
CPU time 99.87 seconds
Started May 26 02:36:28 PM PDT 24
Finished May 26 02:38:09 PM PDT 24
Peak memory 201836 kb
Host smart-47d07874-b742-4825-a6b8-9741b0b14fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762662396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1762662396
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1118018183
Short name T168
Test name
Test status
Simulation time 325391751754 ps
CPU time 199.19 seconds
Started May 26 02:36:28 PM PDT 24
Finished May 26 02:39:48 PM PDT 24
Peak memory 201848 kb
Host smart-4cb1b857-c027-4fec-b9f4-480bf0c332ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118018183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1118018183
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2453647416
Short name T25
Test name
Test status
Simulation time 160131565610 ps
CPU time 365.03 seconds
Started May 26 02:36:29 PM PDT 24
Finished May 26 02:42:35 PM PDT 24
Peak memory 201808 kb
Host smart-7773abef-e90b-46bb-9332-650e72623859
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453647416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2453647416
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1603335705
Short name T48
Test name
Test status
Simulation time 481567173910 ps
CPU time 553.52 seconds
Started May 26 02:36:28 PM PDT 24
Finished May 26 02:45:43 PM PDT 24
Peak memory 201804 kb
Host smart-6218b821-95df-4958-acbd-667b65330245
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603335705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1603335705
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2884275846
Short name T99
Test name
Test status
Simulation time 596504354163 ps
CPU time 630.32 seconds
Started May 26 02:36:30 PM PDT 24
Finished May 26 02:47:01 PM PDT 24
Peak memory 201856 kb
Host smart-b687743c-7b01-489d-822b-828dd3ad0e27
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884275846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2884275846
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3182170709
Short name T518
Test name
Test status
Simulation time 87923229780 ps
CPU time 362.91 seconds
Started May 26 02:36:30 PM PDT 24
Finished May 26 02:42:34 PM PDT 24
Peak memory 202144 kb
Host smart-9452e02c-e5ac-4f65-b045-2f3b822e1c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182170709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3182170709
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.468220798
Short name T652
Test name
Test status
Simulation time 37354481419 ps
CPU time 23.82 seconds
Started May 26 02:36:28 PM PDT 24
Finished May 26 02:36:53 PM PDT 24
Peak memory 201616 kb
Host smart-7109bd92-e82f-41cc-90d4-8a182853f5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468220798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.468220798
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2005413533
Short name T391
Test name
Test status
Simulation time 5491117206 ps
CPU time 13.57 seconds
Started May 26 02:36:28 PM PDT 24
Finished May 26 02:36:43 PM PDT 24
Peak memory 201664 kb
Host smart-053a9c4d-1277-47fe-8fa4-b1f00358e89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005413533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2005413533
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2126968618
Short name T759
Test name
Test status
Simulation time 5719561833 ps
CPU time 3.98 seconds
Started May 26 02:36:27 PM PDT 24
Finished May 26 02:36:32 PM PDT 24
Peak memory 201700 kb
Host smart-7d88c47f-fe5f-4f0e-809e-cfe300029131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126968618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2126968618
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.329241679
Short name T352
Test name
Test status
Simulation time 171765529859 ps
CPU time 393.77 seconds
Started May 26 02:36:37 PM PDT 24
Finished May 26 02:43:12 PM PDT 24
Peak memory 217972 kb
Host smart-d66cf04a-89a3-4c82-bb95-e1fb3747f8db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329241679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
329241679
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.1357923711
Short name T699
Test name
Test status
Simulation time 318790728 ps
CPU time 1.36 seconds
Started May 26 02:36:45 PM PDT 24
Finished May 26 02:36:47 PM PDT 24
Peak memory 201556 kb
Host smart-97980285-68a8-497b-acd6-6333688f4ef7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357923711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.1357923711
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2070404640
Short name T307
Test name
Test status
Simulation time 602368568889 ps
CPU time 136.63 seconds
Started May 26 02:36:36 PM PDT 24
Finished May 26 02:38:53 PM PDT 24
Peak memory 201860 kb
Host smart-fc3bf096-6b1b-43bf-a267-53397201cd87
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070404640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2070404640
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.681424444
Short name T137
Test name
Test status
Simulation time 502142974870 ps
CPU time 1197.53 seconds
Started May 26 02:36:40 PM PDT 24
Finished May 26 02:56:39 PM PDT 24
Peak memory 201928 kb
Host smart-ce9ec163-61b1-4c72-9723-56748845ec0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681424444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.681424444
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3678372867
Short name T312
Test name
Test status
Simulation time 159807298306 ps
CPU time 82.97 seconds
Started May 26 02:36:35 PM PDT 24
Finished May 26 02:37:59 PM PDT 24
Peak memory 201892 kb
Host smart-cf554b69-7ef5-43c0-935d-35eff2fced3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678372867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3678372867
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1483004570
Short name T779
Test name
Test status
Simulation time 493452833950 ps
CPU time 209.55 seconds
Started May 26 02:36:36 PM PDT 24
Finished May 26 02:40:07 PM PDT 24
Peak memory 201800 kb
Host smart-9ce470bb-dca8-4591-8f3f-a46dc6cfaea2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483004570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1483004570
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.445329766
Short name T751
Test name
Test status
Simulation time 486383417012 ps
CPU time 1155.34 seconds
Started May 26 02:36:36 PM PDT 24
Finished May 26 02:55:53 PM PDT 24
Peak memory 201916 kb
Host smart-c4057d4c-dec9-45b4-8756-a290c1ae9d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445329766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.445329766
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.3350836770
Short name T43
Test name
Test status
Simulation time 331369232677 ps
CPU time 348.21 seconds
Started May 26 02:36:35 PM PDT 24
Finished May 26 02:42:24 PM PDT 24
Peak memory 201812 kb
Host smart-a35ea126-3d2a-4fcd-80bb-d484c122fe89
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350836770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.3350836770
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3220675306
Short name T465
Test name
Test status
Simulation time 254044046162 ps
CPU time 545.42 seconds
Started May 26 02:36:41 PM PDT 24
Finished May 26 02:45:47 PM PDT 24
Peak memory 201852 kb
Host smart-401415e6-2572-4bbd-935f-44fbc3e2abe8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220675306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3220675306
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1510383376
Short name T399
Test name
Test status
Simulation time 404258606125 ps
CPU time 224.15 seconds
Started May 26 02:36:35 PM PDT 24
Finished May 26 02:40:20 PM PDT 24
Peak memory 201856 kb
Host smart-803810bd-b3b6-4e32-aa3f-6b1dd478a4dd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510383376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1510383376
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.20154844
Short name T206
Test name
Test status
Simulation time 128131170645 ps
CPU time 763.93 seconds
Started May 26 02:36:35 PM PDT 24
Finished May 26 02:49:19 PM PDT 24
Peak memory 202144 kb
Host smart-8b5edde2-aa81-4b79-8c8c-15c3c2b9985e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20154844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.20154844
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2072414713
Short name T362
Test name
Test status
Simulation time 26089550419 ps
CPU time 33.81 seconds
Started May 26 02:36:35 PM PDT 24
Finished May 26 02:37:10 PM PDT 24
Peak memory 201664 kb
Host smart-e1d359c3-ae01-4f28-a1ef-3f90020403bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072414713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2072414713
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1064033788
Short name T631
Test name
Test status
Simulation time 4807628984 ps
CPU time 11.76 seconds
Started May 26 02:36:35 PM PDT 24
Finished May 26 02:36:48 PM PDT 24
Peak memory 201540 kb
Host smart-a4617c60-908a-47fc-8a2e-0ed59ac25916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064033788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1064033788
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2563628517
Short name T681
Test name
Test status
Simulation time 5796062561 ps
CPU time 13.21 seconds
Started May 26 02:36:37 PM PDT 24
Finished May 26 02:36:51 PM PDT 24
Peak memory 201676 kb
Host smart-136988ca-7e6a-4016-a80d-8ea56cd63034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563628517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2563628517
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1296290116
Short name T685
Test name
Test status
Simulation time 371690104278 ps
CPU time 850.38 seconds
Started May 26 02:36:48 PM PDT 24
Finished May 26 02:50:59 PM PDT 24
Peak memory 201924 kb
Host smart-637034e9-588e-493c-b7f8-2347ae3bf2bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296290116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1296290116
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2457909109
Short name T772
Test name
Test status
Simulation time 133549330583 ps
CPU time 89.01 seconds
Started May 26 02:36:50 PM PDT 24
Finished May 26 02:38:20 PM PDT 24
Peak memory 210540 kb
Host smart-8548cd07-7ea6-4481-ae79-62e78679b171
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457909109 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2457909109
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.4137806989
Short name T464
Test name
Test status
Simulation time 382697456 ps
CPU time 0.79 seconds
Started May 26 02:36:51 PM PDT 24
Finished May 26 02:36:52 PM PDT 24
Peak memory 201548 kb
Host smart-08de589f-1ef6-40d1-b09a-506cd6e175e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137806989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.4137806989
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3009160199
Short name T576
Test name
Test status
Simulation time 553671978791 ps
CPU time 235.76 seconds
Started May 26 02:36:51 PM PDT 24
Finished May 26 02:40:48 PM PDT 24
Peak memory 201908 kb
Host smart-a4cf840a-5341-48c8-96a6-523836bca350
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009160199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3009160199
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.3695034125
Short name T292
Test name
Test status
Simulation time 163260409606 ps
CPU time 360.03 seconds
Started May 26 02:36:51 PM PDT 24
Finished May 26 02:42:52 PM PDT 24
Peak memory 201848 kb
Host smart-7ea0c024-e8c3-4cf2-9500-b50c4185259f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695034125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3695034125
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.78396330
Short name T302
Test name
Test status
Simulation time 493683511927 ps
CPU time 1105.22 seconds
Started May 26 02:36:44 PM PDT 24
Finished May 26 02:55:10 PM PDT 24
Peak memory 201912 kb
Host smart-49b9a819-fad6-4210-ab35-acc73f0da7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78396330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.78396330
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2804630159
Short name T588
Test name
Test status
Simulation time 496339720260 ps
CPU time 1184.63 seconds
Started May 26 02:36:43 PM PDT 24
Finished May 26 02:56:29 PM PDT 24
Peak memory 201820 kb
Host smart-5276529a-2f6e-476c-835b-07150773a03a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804630159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.2804630159
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2233248561
Short name T526
Test name
Test status
Simulation time 332878558617 ps
CPU time 333.55 seconds
Started May 26 02:36:42 PM PDT 24
Finished May 26 02:42:17 PM PDT 24
Peak memory 201864 kb
Host smart-d8a81e4a-c5eb-4a6b-89c4-7369edb4e1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233248561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2233248561
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3718231281
Short name T386
Test name
Test status
Simulation time 334710423457 ps
CPU time 782.12 seconds
Started May 26 02:36:43 PM PDT 24
Finished May 26 02:49:47 PM PDT 24
Peak memory 201812 kb
Host smart-58cd910a-d4d5-4ee2-ba4e-a9335c15e6cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718231281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3718231281
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.381568353
Short name T612
Test name
Test status
Simulation time 174752348400 ps
CPU time 427.46 seconds
Started May 26 02:36:46 PM PDT 24
Finished May 26 02:43:55 PM PDT 24
Peak memory 201872 kb
Host smart-054acb76-ac89-463f-86c0-df71ee3e75aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381568353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.381568353
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.910967749
Short name T560
Test name
Test status
Simulation time 409110756744 ps
CPU time 129.53 seconds
Started May 26 02:36:44 PM PDT 24
Finished May 26 02:38:54 PM PDT 24
Peak memory 201856 kb
Host smart-2c03b710-1f09-410a-a469-b46f13452b26
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910967749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.910967749
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.178314127
Short name T689
Test name
Test status
Simulation time 39072224647 ps
CPU time 90.67 seconds
Started May 26 02:36:54 PM PDT 24
Finished May 26 02:38:25 PM PDT 24
Peak memory 201644 kb
Host smart-43c318f6-2f3a-4f4f-8efd-07be687a1745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178314127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.178314127
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.496154703
Short name T459
Test name
Test status
Simulation time 3821146085 ps
CPU time 3.4 seconds
Started May 26 02:36:51 PM PDT 24
Finished May 26 02:36:56 PM PDT 24
Peak memory 201596 kb
Host smart-22472f31-0883-4af8-be56-df6843c4df07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496154703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.496154703
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.839712343
Short name T418
Test name
Test status
Simulation time 5683344303 ps
CPU time 2.06 seconds
Started May 26 02:36:44 PM PDT 24
Finished May 26 02:36:47 PM PDT 24
Peak memory 201700 kb
Host smart-6b0948d6-6121-401a-b331-8eddc2cbd488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839712343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.839712343
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.4290031117
Short name T225
Test name
Test status
Simulation time 91889744407 ps
CPU time 184.93 seconds
Started May 26 02:36:52 PM PDT 24
Finished May 26 02:39:57 PM PDT 24
Peak memory 212856 kb
Host smart-cb683e65-8b1c-44cf-8151-75a845a1cca9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290031117 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.4290031117
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1069021526
Short name T514
Test name
Test status
Simulation time 483104326 ps
CPU time 1.82 seconds
Started May 26 02:36:58 PM PDT 24
Finished May 26 02:37:00 PM PDT 24
Peak memory 201540 kb
Host smart-cfb283d7-6dad-47fc-b478-260353f96dcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069021526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1069021526
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3625768750
Short name T795
Test name
Test status
Simulation time 344114007019 ps
CPU time 433.73 seconds
Started May 26 02:37:03 PM PDT 24
Finished May 26 02:44:17 PM PDT 24
Peak memory 202016 kb
Host smart-c5faa638-2c40-4b46-9a96-7adf0934e37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625768750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3625768750
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3206259617
Short name T182
Test name
Test status
Simulation time 330347847432 ps
CPU time 397.37 seconds
Started May 26 02:36:50 PM PDT 24
Finished May 26 02:43:28 PM PDT 24
Peak memory 202024 kb
Host smart-64e7a929-37f7-4328-bd6e-3367d7075450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206259617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3206259617
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.4059339320
Short name T505
Test name
Test status
Simulation time 490487344042 ps
CPU time 504.48 seconds
Started May 26 02:36:51 PM PDT 24
Finished May 26 02:45:16 PM PDT 24
Peak memory 201860 kb
Host smart-3222161c-fbdf-40f2-baed-9642a69a0afd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059339320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.4059339320
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2397372474
Short name T368
Test name
Test status
Simulation time 167323688863 ps
CPU time 23.72 seconds
Started May 26 02:36:54 PM PDT 24
Finished May 26 02:37:18 PM PDT 24
Peak memory 201800 kb
Host smart-38ef69d7-4365-40e2-873e-0a05f3fcb017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397372474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2397372474
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1651661105
Short name T573
Test name
Test status
Simulation time 483659653284 ps
CPU time 368.27 seconds
Started May 26 02:36:54 PM PDT 24
Finished May 26 02:43:02 PM PDT 24
Peak memory 201772 kb
Host smart-08eeece6-9b95-4159-baa8-5c39fd26f8d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651661105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1651661105
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3890136124
Short name T769
Test name
Test status
Simulation time 570201170180 ps
CPU time 252.65 seconds
Started May 26 02:36:51 PM PDT 24
Finished May 26 02:41:04 PM PDT 24
Peak memory 201880 kb
Host smart-169257f8-6256-49ba-9d0c-fc002d219f50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890136124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3890136124
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1619570322
Short name T590
Test name
Test status
Simulation time 394440040027 ps
CPU time 228.99 seconds
Started May 26 02:36:50 PM PDT 24
Finished May 26 02:40:40 PM PDT 24
Peak memory 201828 kb
Host smart-e79a3631-4f3d-43f5-aabe-2152fb81feee
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619570322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1619570322
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.84768208
Short name T412
Test name
Test status
Simulation time 39322267244 ps
CPU time 48.64 seconds
Started May 26 02:36:58 PM PDT 24
Finished May 26 02:37:47 PM PDT 24
Peak memory 201660 kb
Host smart-644ebdb6-74ff-4ea2-8146-773b91419305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84768208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.84768208
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2391941531
Short name T639
Test name
Test status
Simulation time 4308751178 ps
CPU time 3.83 seconds
Started May 26 02:36:59 PM PDT 24
Finished May 26 02:37:04 PM PDT 24
Peak memory 201680 kb
Host smart-281a21b5-cab1-4650-8213-19e5d70d99ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391941531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2391941531
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.661430034
Short name T641
Test name
Test status
Simulation time 6089493815 ps
CPU time 15.22 seconds
Started May 26 02:36:51 PM PDT 24
Finished May 26 02:37:07 PM PDT 24
Peak memory 201696 kb
Host smart-cae8599b-1162-44a7-a0b5-809411d817ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661430034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.661430034
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.321027136
Short name T488
Test name
Test status
Simulation time 201851679128 ps
CPU time 123.9 seconds
Started May 26 02:36:57 PM PDT 24
Finished May 26 02:39:01 PM PDT 24
Peak memory 201804 kb
Host smart-3715fc14-f377-450d-8431-a1ad8209d5d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321027136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
321027136
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.173970394
Short name T513
Test name
Test status
Simulation time 410712787 ps
CPU time 0.83 seconds
Started May 26 02:31:40 PM PDT 24
Finished May 26 02:31:42 PM PDT 24
Peak memory 201532 kb
Host smart-c5a2c30a-f1b7-4fa9-b0c6-d6ff958b239c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173970394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.173970394
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2909321142
Short name T253
Test name
Test status
Simulation time 172005829272 ps
CPU time 81.31 seconds
Started May 26 02:31:39 PM PDT 24
Finished May 26 02:33:01 PM PDT 24
Peak memory 201876 kb
Host smart-3a343855-fc75-4985-9aad-add608f35fbd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909321142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2909321142
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3553703419
Short name T158
Test name
Test status
Simulation time 328653336525 ps
CPU time 210.55 seconds
Started May 26 02:31:38 PM PDT 24
Finished May 26 02:35:10 PM PDT 24
Peak memory 201860 kb
Host smart-64fb64a5-d26f-4198-a58b-b6b0769cd2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553703419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3553703419
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2804000473
Short name T635
Test name
Test status
Simulation time 327394216430 ps
CPU time 801.24 seconds
Started May 26 02:31:40 PM PDT 24
Finished May 26 02:45:03 PM PDT 24
Peak memory 201916 kb
Host smart-de330802-6921-4cd6-8e0f-1b08f83cbbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804000473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2804000473
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3505717223
Short name T660
Test name
Test status
Simulation time 171882678820 ps
CPU time 399.4 seconds
Started May 26 02:31:47 PM PDT 24
Finished May 26 02:38:27 PM PDT 24
Peak memory 201848 kb
Host smart-67e15815-f911-4db9-829f-73e7fe36a91d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505717223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3505717223
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3120101155
Short name T135
Test name
Test status
Simulation time 491430813790 ps
CPU time 363.75 seconds
Started May 26 02:31:41 PM PDT 24
Finished May 26 02:37:46 PM PDT 24
Peak memory 201880 kb
Host smart-58c526f9-7825-45f8-958d-8fb3c24c41cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120101155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3120101155
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2182780797
Short name T638
Test name
Test status
Simulation time 494713808741 ps
CPU time 1029.67 seconds
Started May 26 02:31:43 PM PDT 24
Finished May 26 02:48:53 PM PDT 24
Peak memory 201824 kb
Host smart-2fd96e26-84a8-4bf6-8ede-8089416b434f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182780797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2182780797
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1671247681
Short name T628
Test name
Test status
Simulation time 196751137708 ps
CPU time 462.23 seconds
Started May 26 02:31:43 PM PDT 24
Finished May 26 02:39:26 PM PDT 24
Peak memory 201896 kb
Host smart-b6931b0d-d8a6-4e95-9e99-efea85034499
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671247681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1671247681
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.4048726401
Short name T743
Test name
Test status
Simulation time 203031905698 ps
CPU time 205.99 seconds
Started May 26 02:31:41 PM PDT 24
Finished May 26 02:35:08 PM PDT 24
Peak memory 201852 kb
Host smart-887e40cf-b4bf-4b97-b7a5-47bb5fcc0cdc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048726401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.4048726401
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.561812654
Short name T477
Test name
Test status
Simulation time 90505130780 ps
CPU time 478.16 seconds
Started May 26 02:31:40 PM PDT 24
Finished May 26 02:39:39 PM PDT 24
Peak memory 202168 kb
Host smart-6d24ef47-8222-46b1-9848-398bad4ad833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561812654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.561812654
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3630106334
Short name T437
Test name
Test status
Simulation time 25225646805 ps
CPU time 57.67 seconds
Started May 26 02:31:38 PM PDT 24
Finished May 26 02:32:36 PM PDT 24
Peak memory 201656 kb
Host smart-c39ae140-7eb8-4ed7-9716-e44444dcc6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630106334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3630106334
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.969928826
Short name T466
Test name
Test status
Simulation time 4324700460 ps
CPU time 3.23 seconds
Started May 26 02:31:40 PM PDT 24
Finished May 26 02:31:44 PM PDT 24
Peak memory 201688 kb
Host smart-a43d8d0b-a5db-4439-af4a-e9d92bf6cef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969928826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.969928826
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1365664705
Short name T562
Test name
Test status
Simulation time 6088139805 ps
CPU time 4.18 seconds
Started May 26 02:31:43 PM PDT 24
Finished May 26 02:31:48 PM PDT 24
Peak memory 201652 kb
Host smart-8b5f2e32-d496-46b1-80a1-640dbb692a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365664705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1365664705
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1053478397
Short name T763
Test name
Test status
Simulation time 194424164525 ps
CPU time 463.01 seconds
Started May 26 02:31:40 PM PDT 24
Finished May 26 02:39:24 PM PDT 24
Peak memory 201844 kb
Host smart-4fa5aadc-b0bc-480b-abbb-ac1eb27915c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053478397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1053478397
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.733518370
Short name T350
Test name
Test status
Simulation time 139801231037 ps
CPU time 169.71 seconds
Started May 26 02:31:40 PM PDT 24
Finished May 26 02:34:31 PM PDT 24
Peak memory 210480 kb
Host smart-173303ab-8882-4985-a1e9-6e38de97cc11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733518370 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.733518370
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1700692442
Short name T504
Test name
Test status
Simulation time 532934073 ps
CPU time 1.48 seconds
Started May 26 02:31:39 PM PDT 24
Finished May 26 02:31:42 PM PDT 24
Peak memory 201548 kb
Host smart-12aae17f-95cb-4c44-ad16-17a1c9f48547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700692442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1700692442
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.4193392850
Short name T235
Test name
Test status
Simulation time 167059263536 ps
CPU time 93.23 seconds
Started May 26 02:31:40 PM PDT 24
Finished May 26 02:33:14 PM PDT 24
Peak memory 201920 kb
Host smart-d901f3d5-b7e9-42c9-92c0-d14a76905e15
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193392850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.4193392850
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.83907619
Short name T542
Test name
Test status
Simulation time 164749159458 ps
CPU time 101.73 seconds
Started May 26 02:31:47 PM PDT 24
Finished May 26 02:33:30 PM PDT 24
Peak memory 201856 kb
Host smart-682136c0-981e-4557-a2e7-8ca9f6095c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83907619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.83907619
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1841312168
Short name T404
Test name
Test status
Simulation time 165822826638 ps
CPU time 360.48 seconds
Started May 26 02:31:39 PM PDT 24
Finished May 26 02:37:40 PM PDT 24
Peak memory 201848 kb
Host smart-9b446032-7438-4a30-bccf-850df127394f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841312168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1841312168
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.302708929
Short name T533
Test name
Test status
Simulation time 335187295019 ps
CPU time 179.98 seconds
Started May 26 02:31:40 PM PDT 24
Finished May 26 02:34:41 PM PDT 24
Peak memory 201920 kb
Host smart-a63397cc-856e-428c-865d-7ac000461c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302708929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.302708929
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3260959088
Short name T385
Test name
Test status
Simulation time 325126312947 ps
CPU time 721.36 seconds
Started May 26 02:31:42 PM PDT 24
Finished May 26 02:43:44 PM PDT 24
Peak memory 201836 kb
Host smart-94c40a44-9483-473e-8a6a-7fce8fe7ceff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260959088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3260959088
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3255072763
Short name T192
Test name
Test status
Simulation time 617157153625 ps
CPU time 368.43 seconds
Started May 26 02:31:40 PM PDT 24
Finished May 26 02:37:50 PM PDT 24
Peak memory 201736 kb
Host smart-560731b7-cda8-4d66-9c4d-94141404c801
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255072763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3255072763
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3098836635
Short name T186
Test name
Test status
Simulation time 197869900527 ps
CPU time 415.29 seconds
Started May 26 02:31:40 PM PDT 24
Finished May 26 02:38:36 PM PDT 24
Peak memory 201828 kb
Host smart-ffed3541-8e91-46dc-a59d-be64306172d6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098836635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3098836635
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3760337017
Short name T207
Test name
Test status
Simulation time 82748012356 ps
CPU time 390.93 seconds
Started May 26 02:31:53 PM PDT 24
Finished May 26 02:38:24 PM PDT 24
Peak memory 202180 kb
Host smart-ee12f513-35ed-4042-9264-a9b6c0c1cae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760337017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3760337017
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2785151525
Short name T651
Test name
Test status
Simulation time 24521047036 ps
CPU time 51.97 seconds
Started May 26 02:31:40 PM PDT 24
Finished May 26 02:32:33 PM PDT 24
Peak memory 201660 kb
Host smart-fdac6687-e199-4d4f-b126-28fd7d6f36a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785151525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2785151525
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.750076463
Short name T528
Test name
Test status
Simulation time 3765139403 ps
CPU time 2.67 seconds
Started May 26 02:31:39 PM PDT 24
Finished May 26 02:31:42 PM PDT 24
Peak memory 201632 kb
Host smart-3d86754b-3609-4ce6-a961-8661c4a8a2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750076463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.750076463
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1419846461
Short name T170
Test name
Test status
Simulation time 5495384175 ps
CPU time 7.11 seconds
Started May 26 02:31:39 PM PDT 24
Finished May 26 02:31:47 PM PDT 24
Peak memory 201664 kb
Host smart-81ccda8c-dd1d-42b6-92b5-62bb15d68bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419846461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1419846461
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.366880309
Short name T694
Test name
Test status
Simulation time 254059783978 ps
CPU time 384.05 seconds
Started May 26 02:31:39 PM PDT 24
Finished May 26 02:38:04 PM PDT 24
Peak memory 202108 kb
Host smart-cf5e14c3-e7cd-449d-92c5-49644a3010a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366880309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.366880309
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.1482912193
Short name T22
Test name
Test status
Simulation time 26052945266 ps
CPU time 33.28 seconds
Started May 26 02:31:40 PM PDT 24
Finished May 26 02:32:15 PM PDT 24
Peak memory 210468 kb
Host smart-d22f5871-6fcd-4945-a0bc-aceeb2bce764
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482912193 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.1482912193
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3029432294
Short name T750
Test name
Test status
Simulation time 344434581 ps
CPU time 0.83 seconds
Started May 26 02:31:49 PM PDT 24
Finished May 26 02:31:51 PM PDT 24
Peak memory 201528 kb
Host smart-ae1797ef-f522-42bf-9b3e-8342c9464f71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029432294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3029432294
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3575034152
Short name T260
Test name
Test status
Simulation time 328049048536 ps
CPU time 663.63 seconds
Started May 26 02:31:55 PM PDT 24
Finished May 26 02:42:59 PM PDT 24
Peak memory 201876 kb
Host smart-1eebe882-80c1-4b87-b3fd-1a855ad7e079
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575034152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3575034152
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2932174685
Short name T744
Test name
Test status
Simulation time 507799437535 ps
CPU time 320.95 seconds
Started May 26 02:31:49 PM PDT 24
Finished May 26 02:37:10 PM PDT 24
Peak memory 201836 kb
Host smart-8696a676-ccb0-46eb-9bf1-66524e01c11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932174685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2932174685
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1825346358
Short name T764
Test name
Test status
Simulation time 320929366319 ps
CPU time 402.4 seconds
Started May 26 02:31:51 PM PDT 24
Finished May 26 02:38:34 PM PDT 24
Peak memory 201892 kb
Host smart-9a22b105-1932-4b12-942e-960bb3d3b8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825346358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1825346358
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.520708057
Short name T664
Test name
Test status
Simulation time 166987783922 ps
CPU time 382.05 seconds
Started May 26 02:31:47 PM PDT 24
Finished May 26 02:38:10 PM PDT 24
Peak memory 201976 kb
Host smart-5632497d-169e-4053-a9cd-cd5fcfd43b27
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=520708057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.520708057
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1192625746
Short name T151
Test name
Test status
Simulation time 330440982916 ps
CPU time 111.58 seconds
Started May 26 02:31:51 PM PDT 24
Finished May 26 02:33:43 PM PDT 24
Peak memory 201804 kb
Host smart-de224443-8136-40f4-9214-9e6cb90b7a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192625746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1192625746
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.340235826
Short name T143
Test name
Test status
Simulation time 169227003736 ps
CPU time 49.87 seconds
Started May 26 02:31:49 PM PDT 24
Finished May 26 02:32:39 PM PDT 24
Peak memory 201908 kb
Host smart-e4a0a7d2-e66c-47b4-8a92-b1ce61bb522b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=340235826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.340235826
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2215681945
Short name T724
Test name
Test status
Simulation time 174110146442 ps
CPU time 383.37 seconds
Started May 26 02:31:51 PM PDT 24
Finished May 26 02:38:15 PM PDT 24
Peak memory 201880 kb
Host smart-602b71f9-0a00-4e2b-a12a-3de140b2ef8d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215681945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2215681945
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1560736839
Short name T620
Test name
Test status
Simulation time 202245407670 ps
CPU time 216.18 seconds
Started May 26 02:31:50 PM PDT 24
Finished May 26 02:35:27 PM PDT 24
Peak memory 201832 kb
Host smart-622afff5-f7e0-44f9-ba5c-6e5646ff7227
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560736839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1560736839
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.782368571
Short name T209
Test name
Test status
Simulation time 107885058772 ps
CPU time 464.68 seconds
Started May 26 02:31:48 PM PDT 24
Finished May 26 02:39:33 PM PDT 24
Peak memory 202176 kb
Host smart-5a8ce03d-a158-48ff-a4a4-8fcd1ccb6410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782368571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.782368571
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3157465737
Short name T569
Test name
Test status
Simulation time 26913101347 ps
CPU time 9.89 seconds
Started May 26 02:31:49 PM PDT 24
Finished May 26 02:32:00 PM PDT 24
Peak memory 201692 kb
Host smart-7ab0f04c-0109-4c4f-9131-0718c54e6ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157465737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3157465737
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.526148618
Short name T776
Test name
Test status
Simulation time 2947374645 ps
CPU time 7.6 seconds
Started May 26 02:31:50 PM PDT 24
Finished May 26 02:31:58 PM PDT 24
Peak memory 201540 kb
Host smart-bde44994-f93e-4d65-9967-9dbcb7b27cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526148618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.526148618
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.108276127
Short name T457
Test name
Test status
Simulation time 5703682332 ps
CPU time 7.21 seconds
Started May 26 02:31:39 PM PDT 24
Finished May 26 02:31:47 PM PDT 24
Peak memory 201636 kb
Host smart-c1782c90-4c70-436e-9216-707bccb69001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108276127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.108276127
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.752946373
Short name T242
Test name
Test status
Simulation time 109225611908 ps
CPU time 152.75 seconds
Started May 26 02:31:49 PM PDT 24
Finished May 26 02:34:22 PM PDT 24
Peak memory 210436 kb
Host smart-f6435b6c-0daa-46a2-b5e0-418c54e5c5f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752946373 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.752946373
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1596043088
Short name T407
Test name
Test status
Simulation time 524852276 ps
CPU time 1.74 seconds
Started May 26 02:31:48 PM PDT 24
Finished May 26 02:31:50 PM PDT 24
Peak memory 201520 kb
Host smart-26e2a4ba-aa37-4651-b07a-d68c36756309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596043088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1596043088
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2293265511
Short name T277
Test name
Test status
Simulation time 330410666797 ps
CPU time 84.18 seconds
Started May 26 02:31:50 PM PDT 24
Finished May 26 02:33:15 PM PDT 24
Peak memory 201848 kb
Host smart-c1d106da-2260-4e31-9ba8-1b32faec0b14
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293265511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2293265511
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2341936627
Short name T149
Test name
Test status
Simulation time 489679726137 ps
CPU time 268.12 seconds
Started May 26 02:31:53 PM PDT 24
Finished May 26 02:36:22 PM PDT 24
Peak memory 201872 kb
Host smart-34301475-4d5f-40db-b1f2-c484bc6d8c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341936627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2341936627
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.249132156
Short name T787
Test name
Test status
Simulation time 169372295696 ps
CPU time 421.64 seconds
Started May 26 02:32:00 PM PDT 24
Finished May 26 02:39:03 PM PDT 24
Peak memory 201852 kb
Host smart-a306082e-6658-4490-890b-b8c930b8bbf2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=249132156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.249132156
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1209091241
Short name T178
Test name
Test status
Simulation time 489086101358 ps
CPU time 291.78 seconds
Started May 26 02:31:49 PM PDT 24
Finished May 26 02:36:41 PM PDT 24
Peak memory 201840 kb
Host smart-fa2e0f84-494d-40cd-8e5c-4da4310ccf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209091241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1209091241
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.190168835
Short name T594
Test name
Test status
Simulation time 331208455285 ps
CPU time 330.47 seconds
Started May 26 02:31:49 PM PDT 24
Finished May 26 02:37:20 PM PDT 24
Peak memory 201900 kb
Host smart-4305de18-e626-4cc1-af99-58b147532846
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=190168835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.190168835
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.591019236
Short name T234
Test name
Test status
Simulation time 198288204441 ps
CPU time 455.37 seconds
Started May 26 02:31:48 PM PDT 24
Finished May 26 02:39:24 PM PDT 24
Peak memory 201876 kb
Host smart-44d92a6e-8c4e-459c-b44c-d776d6d1fba8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591019236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.591019236
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1948193679
Short name T382
Test name
Test status
Simulation time 400092912525 ps
CPU time 64.17 seconds
Started May 26 02:31:51 PM PDT 24
Finished May 26 02:32:56 PM PDT 24
Peak memory 201876 kb
Host smart-ee970d6f-23b8-4dfc-aa8a-18b58e9c1dcc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948193679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1948193679
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1820285786
Short name T697
Test name
Test status
Simulation time 123901329991 ps
CPU time 443.19 seconds
Started May 26 02:31:51 PM PDT 24
Finished May 26 02:39:15 PM PDT 24
Peak memory 202228 kb
Host smart-375224a2-df04-45c4-b06e-7c429c85b3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820285786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1820285786
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1138282364
Short name T586
Test name
Test status
Simulation time 44220974157 ps
CPU time 99.67 seconds
Started May 26 02:31:53 PM PDT 24
Finished May 26 02:33:33 PM PDT 24
Peak memory 201640 kb
Host smart-c49c78c1-2b04-46ef-a216-763490c6add4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138282364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1138282364
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2763024326
Short name T444
Test name
Test status
Simulation time 4806159022 ps
CPU time 12.06 seconds
Started May 26 02:31:51 PM PDT 24
Finished May 26 02:32:04 PM PDT 24
Peak memory 201680 kb
Host smart-9cc11b65-3c29-4ad1-8178-e001115fc7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763024326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2763024326
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2723254250
Short name T667
Test name
Test status
Simulation time 6139232248 ps
CPU time 4.77 seconds
Started May 26 02:31:47 PM PDT 24
Finished May 26 02:31:53 PM PDT 24
Peak memory 201656 kb
Host smart-f7bc93ac-6b62-4685-a8dc-90bd04db9469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723254250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2723254250
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3654326698
Short name T286
Test name
Test status
Simulation time 503202512281 ps
CPU time 1600.13 seconds
Started May 26 02:32:02 PM PDT 24
Finished May 26 02:58:43 PM PDT 24
Peak memory 210388 kb
Host smart-f563b6ab-f6f5-4a08-aab3-ae4d94454f43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654326698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3654326698
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.127400399
Short name T24
Test name
Test status
Simulation time 12824051522 ps
CPU time 30.82 seconds
Started May 26 02:31:56 PM PDT 24
Finished May 26 02:32:27 PM PDT 24
Peak memory 210564 kb
Host smart-374537c9-94ae-4dde-b64b-41d581d67dc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127400399 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.127400399
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2332269337
Short name T71
Test name
Test status
Simulation time 542107426 ps
CPU time 0.73 seconds
Started May 26 02:31:57 PM PDT 24
Finished May 26 02:31:59 PM PDT 24
Peak memory 201552 kb
Host smart-d246be5d-adab-4119-830f-d1fea00174c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332269337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2332269337
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.115742098
Short name T545
Test name
Test status
Simulation time 210363908938 ps
CPU time 123.26 seconds
Started May 26 02:31:49 PM PDT 24
Finished May 26 02:33:53 PM PDT 24
Peak memory 201916 kb
Host smart-73d531c3-0253-41ac-ab06-fbcb0a088592
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115742098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.115742098
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1309209269
Short name T335
Test name
Test status
Simulation time 163875485588 ps
CPU time 199.66 seconds
Started May 26 02:31:57 PM PDT 24
Finished May 26 02:35:17 PM PDT 24
Peak memory 201848 kb
Host smart-4750fcb5-2b33-4e02-9608-f5fa3a3a2a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309209269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1309209269
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3594117837
Short name T181
Test name
Test status
Simulation time 496096767401 ps
CPU time 476.03 seconds
Started May 26 02:31:47 PM PDT 24
Finished May 26 02:39:44 PM PDT 24
Peak memory 201848 kb
Host smart-61ee8232-2b35-46cc-a0a3-18c84fc5c844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594117837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3594117837
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2085552062
Short name T474
Test name
Test status
Simulation time 329827581679 ps
CPU time 811.15 seconds
Started May 26 02:31:52 PM PDT 24
Finished May 26 02:45:24 PM PDT 24
Peak memory 201860 kb
Host smart-2c0b864f-227c-4697-b9e6-20e6ca0e7c73
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085552062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2085552062
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2748543987
Short name T177
Test name
Test status
Simulation time 499793631812 ps
CPU time 312.51 seconds
Started May 26 02:31:54 PM PDT 24
Finished May 26 02:37:07 PM PDT 24
Peak memory 201852 kb
Host smart-123af99c-e92d-4661-9399-574fbb6ef711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748543987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2748543987
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.208874908
Short name T187
Test name
Test status
Simulation time 333782881770 ps
CPU time 389.16 seconds
Started May 26 02:31:51 PM PDT 24
Finished May 26 02:38:21 PM PDT 24
Peak memory 201824 kb
Host smart-2646735c-db3a-4e35-a318-7abfca1d673b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=208874908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.208874908
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1064984448
Short name T180
Test name
Test status
Simulation time 568285690077 ps
CPU time 279.7 seconds
Started May 26 02:31:50 PM PDT 24
Finished May 26 02:36:30 PM PDT 24
Peak memory 201940 kb
Host smart-2dcbd5eb-9e33-4843-90e8-da9e90a8e970
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064984448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1064984448
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1849831501
Short name T485
Test name
Test status
Simulation time 582749253130 ps
CPU time 667.03 seconds
Started May 26 02:31:47 PM PDT 24
Finished May 26 02:42:55 PM PDT 24
Peak memory 201852 kb
Host smart-3981b31c-2280-4ee1-ac56-0e23dbcc92a2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849831501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1849831501
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.785134909
Short name T53
Test name
Test status
Simulation time 105963506817 ps
CPU time 395.41 seconds
Started May 26 02:32:05 PM PDT 24
Finished May 26 02:38:42 PM PDT 24
Peak memory 202168 kb
Host smart-87bee5a3-f154-4e6b-95ab-b2b4db33e950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785134909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.785134909
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3139096334
Short name T626
Test name
Test status
Simulation time 31555212064 ps
CPU time 70.6 seconds
Started May 26 02:32:00 PM PDT 24
Finished May 26 02:33:12 PM PDT 24
Peak memory 201684 kb
Host smart-098d963d-31fd-4068-be7a-adefa3b92dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139096334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3139096334
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3627639485
Short name T379
Test name
Test status
Simulation time 4692642278 ps
CPU time 3.74 seconds
Started May 26 02:32:00 PM PDT 24
Finished May 26 02:32:05 PM PDT 24
Peak memory 201624 kb
Host smart-267d363a-60e6-4d8f-9bc5-032987ab21aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627639485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3627639485
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1404965929
Short name T357
Test name
Test status
Simulation time 6206293329 ps
CPU time 8.53 seconds
Started May 26 02:31:50 PM PDT 24
Finished May 26 02:31:59 PM PDT 24
Peak memory 201620 kb
Host smart-2f9e6fd5-976e-4120-b66d-020b54ecaa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404965929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1404965929
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1576898352
Short name T210
Test name
Test status
Simulation time 4086068453559 ps
CPU time 4144.6 seconds
Started May 26 02:31:57 PM PDT 24
Finished May 26 03:41:04 PM PDT 24
Peak memory 213084 kb
Host smart-502ebb34-2a40-4b85-9bac-8fdcec36bbdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576898352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1576898352
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.4074294170
Short name T96
Test name
Test status
Simulation time 36511926968 ps
CPU time 103.75 seconds
Started May 26 02:31:57 PM PDT 24
Finished May 26 02:33:42 PM PDT 24
Peak memory 210628 kb
Host smart-b8397a57-33b3-42a0-ae6a-2e66ed6de414
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074294170 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.4074294170
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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