Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7594	1			T3	51		T11	48		T54	8
testmodes[AdcCtrlTestmodeNormal]	5878	1			T2	1		T3	40		T4	2
testmodes[AdcCtrlTestmodeLowpower]	6321	1			T1	15		T3	54		T6	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	4051	1			T3	18		T11	17		T54	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1905	1			T3	11		T11	20		T54	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1533	1			T3	22		T11	11		T57	17
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1890	1			T3	9		T11	18		T54	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2122	1			T3	14		T4	1		T5	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1521	1			T3	16		T11	12		T57	15
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1541	1			T3	24		T11	13		T57	19
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1497	1			T3	14		T11	11		T57	13
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	3034	1			T1	14		T3	16		T8	1