Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28307

1

T1

15

T2

1

T3

145

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24772

1

T1

15

T2

1

T3

145

auto[ADC_CTRL_FILTER_COND_OUT]

3535

1

T4

1

T5

3

T12

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21839

1

T1

15

T3

145

T4

1

auto[1]

6468

1

T2

1

T4

1

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24199

1

T1

15

T2

1

T3

145

auto[1]

4108

1

T7

3

T11

20

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	9	1			T203	9		-	-		-	-
values[0]	70	1			T204	15		T171	14		T205	13
values[1]	758	1			T2	1		T4	1		T11	29
values[2]	3000	1			T7	4		T8	24		T10	10
values[3]	626	1			T45	9		T91	8		T38	4
values[4]	609	1			T55	1		T36	6		T41	1
values[5]	716	1			T52	17		T84	15		T87	3
values[6]	679	1			T5	1		T91	15		T130	21
values[7]	962	1			T41	1		T48	1		T84	23
values[8]	833	1			T48	1		T89	10		T136	14
values[9]	1220	1			T4	1		T5	2		T6	10
minimum	18825	1			T1	15		T3	145		T9	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	887	1			T2	1		T4	1		T11	29
values[1]	3116	1			T7	4		T8	24		T10	10
values[2]	585	1			T55	1		T36	6		T41	1
values[3]	671	1			T84	15		T140	7		T39	13
values[4]	733	1			T5	1		T52	17		T87	3
values[5]	748	1			T91	15		T37	9		T130	21
values[6]	883	1			T41	1		T48	1		T84	23
values[7]	730	1			T52	16		T48	1		T89	10
values[8]	937	1			T4	1		T5	2		T6	10
values[9]	192	1			T36	7		T206	27		T163	1
minimum	18825	1			T1	15		T3	145		T9	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

4406

1

T6

9

T8

22

T10

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T2	1		T11	9		T46	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T4	1		T131	23		T207	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1762	1			T7	1		T8	24		T10	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T91	1		T145	1		T140	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T55	1		T36	3		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T45	9		T87	1		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T84	7		T140	7		T141	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T39	8		T149	1		T208	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T52	17		T87	1		T132	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T5	1		T26	12		T209	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T91	1		T130	2		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T37	6		T140	11		T132	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T48	1		T84	12		T141	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T41	1		T24	1		T210	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T89	3		T136	15		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T52	16		T48	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T4	1		T6	10		T52	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T5	2		T12	2		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T36	4		T163	1		T211	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T206	13		T212	7		T213	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18691	1			T1	15		T3	145		T9	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	20		T46	11		T132	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T131	30		T207	13		T16	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T7	3		T137	33		T146	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T91	7		T50	7		T109	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T36	3		T142	6		T134	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T87	10		T38	2		T138	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T84	8		T141	10		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T39	5		T149	1		T214	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T87	2		T132	7		T190	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T26	12		T209	14		T215	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T91	14		T130	19		T14	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T37	3		T132	10		T155	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T84	11		T141	11		T155	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T216	8		T217	2		T218	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T89	7		T130	8		T138	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T40	3		T16	1		T219	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T84	7		T141	5		T154	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	4		T38	11		T188	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T36	3		T211	2		T100	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T206	14		T212	2		T213	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	1		T37	1		T39	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T203	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T205	9		T220	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T204	15		T171	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	1		T11	9		T46	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T4	1		T131	23		T207	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1719	1			T7	1		T8	24		T10	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T87	1		T145	1		T140	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T221	1		T142	10		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T45	9		T91	1		T38	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T55	1		T36	3		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T138	2		T39	8		T15	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T52	17		T84	7		T87	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T149	1		T26	12		T214	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T91	1		T130	2		T190	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	1		T140	11		T132	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T48	1		T84	12		T141	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T41	1		T37	6		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T89	3		T130	1		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T48	1		T136	14		T143	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T4	1		T6	10		T52	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T5	2		T12	2		T52	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18691	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T203	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T205	4		T220	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T171	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	20		T46	11		T132	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T131	30		T207	13		T16	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T7	3		T137	33		T146	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T87	10		T109	13		T222	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T142	6		T202	9		T164	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T91	7		T38	2		T14	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T36	3		T141	10		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T138	11		T39	5		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T84	8		T87	2		T132	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T149	1		T26	12		T214	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T91	14		T130	19		T190	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T132	10		T155	8		T215	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T84	11		T141	11		T155	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T37	3		T40	1		T211	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T89	7		T130	8		T138	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T16	1		T219	18		T212	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T36	3		T84	7		T131	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T12	4		T38	11		T40	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	1		T37	1		T39	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	1		T11	21		T46	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T4	1		T131	32		T207	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T7	4		T8	2		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T91	8		T145	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T55	1		T36	5		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T45	1		T87	11		T38	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T84	9		T140	1		T141	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T39	10		T149	2		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T52	1		T87	3		T132	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	1		T26	13		T209	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T91	15		T130	21		T14	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T37	6		T140	1		T132	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T48	1		T84	12		T141	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T41	1		T24	1		T210	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T89	8		T136	1		T130	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T52	1		T48	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T4	1		T6	1		T52	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T5	2		T12	5		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T36	6		T163	1		T211	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T206	15		T212	3		T213	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18825	1			T1	15		T3	145		T9	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	8		T46	14		T132	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T131	21		T188	9		T16	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1414	1			T8	22		T10	9		T53	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T140	12		T50	6		T223	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T36	1		T142	9		T134	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T45	8		T14	1		T15	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T84	6		T140	6		T141	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T39	3		T208	10		T214	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T52	16		T132	8		T190	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T26	11		T215	10		T224	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T134	10		T225	9		T188	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T37	3		T140	10		T132	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T84	11		T141	13		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T215	8		T216	8		T217	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T89	2		T136	14		T131	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T52	15		T136	13		T40	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T6	9		T52	9		T84	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	1		T38	3		T143	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T36	1		T226	13		T227	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T206	12		T212	6		T203	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T203	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T205	5		T220	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T204	1		T171	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	1		T11	21		T46	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	1		T131	32		T207	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T7	4		T8	2		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T87	11		T145	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T221	1		T142	7		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T45	1		T91	8		T38	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T55	1		T36	5		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T138	13		T39	10		T15	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T52	1		T84	9		T87	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T149	2		T26	13		T214	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T91	15		T130	21		T190	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T5	1		T140	1		T132	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T48	1		T84	12		T141	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T41	1		T37	6		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T89	8		T130	9		T138	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T48	1		T136	1		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T4	1		T6	1		T52	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T5	2		T12	5		T52	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18825	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T203	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T205	8		T220	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T204	14		T171	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	8		T46	14		T132	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T131	21		T188	9		T16	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1373	1			T8	22		T10	9		T53	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T140	12		T223	4		T222	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T142	9		T225	12		T164	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T45	8		T14	1		T228	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T36	1		T141	10		T208	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T39	3		T15	2		T208	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T52	16		T84	6		T140	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T26	11		T214	11		T224	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T190	7		T225	9		T188	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T140	10		T132	11		T215	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T84	11		T141	13		T26	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T37	3		T40	1		T215	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T89	2		T149	11		T229	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T136	13		T143	6		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T6	9		T52	9		T36	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T12	1		T52	15		T38	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

auto[0]

4406

1

T6

9

T8

22

T10

9

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28307

1

T1

15

T2

1

T3

145

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

25026

1

T1

15

T2

1

T3

145

auto[ADC_CTRL_FILTER_COND_OUT]

3281

1

T4

2

T5

2

T11

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22000

1

T1

15

T3

145

T5

1

auto[1]

6307

1

T2

1

T4

2

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24199

1

T1

15

T2

1

T3

145

auto[1]

4108

1

T7

3

T11

20

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T34	1		-	-		-	-
values[0]	146	1			T36	7		T230	18		T165	15
values[1]	616	1			T5	1		T145	1		T138	9
values[2]	687	1			T5	1		T6	10		T36	6
values[3]	771	1			T52	16		T84	23		T145	1
values[4]	804	1			T12	6		T41	1		T45	9
values[5]	3084	1			T4	1		T8	24		T10	10
values[6]	674	1			T11	29		T52	10		T41	1
values[7]	553	1			T132	16		T139	1		T221	1
values[8]	735	1			T5	1		T55	1		T38	5
values[9]	1411	1			T2	1		T4	1		T7	4
minimum	18825	1			T1	15		T3	145		T9	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	988	1			T5	1		T36	13		T145	2
values[1]	708	1			T5	1		T6	10		T84	23
values[2]	875	1			T52	16		T145	1		T38	16
values[3]	3044	1			T8	24		T10	10		T12	6
values[4]	659	1			T4	1		T11	29		T52	17
values[5]	592	1			T52	10		T41	1		T37	9
values[6]	566	1			T5	1		T55	1		T130	11
values[7]	892	1			T2	1		T87	3		T91	15
values[8]	902	1			T4	1		T7	4		T48	1
values[9]	241	1			T91	8		T140	7		T132	27
minimum	18840	1			T1	15		T3	145		T9	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

4406

1

T6

9

T8

22

T10

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T36	3		T145	1		T131	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	1		T36	4		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	1		T6	10		T138	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T84	12		T136	15		T231	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T145	1		T38	5		T141	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T52	16		T135	1		T214	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1717	1			T8	24		T10	10		T12	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T41	1		T140	11		T134	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T130	1		T142	18		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	1		T11	9		T52	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T41	1		T37	6		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T52	10		T221	1		T24	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T55	1		T221	1		T210	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	1		T130	1		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T2	1		T87	1		T91	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T136	14		T225	10		T188	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T7	1		T84	7		T26	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	1		T48	1		T84	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T91	1		T208	11		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T140	7		T132	13		T232	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18705	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T170	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T36	3		T131	18		T142	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T36	3		T130	9		T155	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T138	8		T141	10		T14	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T84	11		T218	2		T233	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T38	11		T141	11		T209	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T214	13		T207	13		T211	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T12	4		T89	7		T137	33
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T134	10		T214	4		T107	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T130	8		T142	14		T107	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T11	20		T46	11		T87	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T37	3		T155	8		T234	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T26	12		T209	16		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T235	8		T144	13		T150	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T130	10		T38	2		T132	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T87	2		T91	14		T131	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T156	12		T236	13		T237	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T7	3		T84	8		T26	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T84	7		T138	11		T131	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T91	7		T100	11		T170	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T132	14		T238	9		T239	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	1		T37	1		T39	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T34	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T230	11		T160	16		T35	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T36	4		T165	15		T240	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T138	1		T142	10		T15	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T5	1		T145	1		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	1		T6	10		T36	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T130	1		T14	6		T231	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T145	1		T38	2		T141	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T52	16		T84	12		T136	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T12	2		T45	9		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T41	1		T140	11		T207	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1757	1			T8	24		T10	10		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	1		T52	17		T46	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T41	1		T37	6		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	9		T52	10		T87	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T139	1		T221	1		T40	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T132	9		T24	1		T108	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T55	1		T131	9		T132	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	1		T38	3		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	403	1			T2	1		T7	1		T84	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T4	1		T48	1		T84	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18691	1			T1	15		T3	145		T9	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T230	7		T160	14		T35	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T36	3		T240	4		T241	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T138	8		T142	6		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T155	10		T211	2		T242	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T36	3		T131	18		T206	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T130	9		T14	7		T206	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T38	2		T141	10		T14	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T84	11		T214	13		T243	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	4		T89	7		T38	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T207	13		T211	2		T16	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T137	33		T130	8		T146	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T46	11		T134	10		T214	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T37	3		T155	8		T234	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	20		T87	10		T130	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T40	3		T187	2		T188	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T132	7		T144	11		T244	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T131	8		T132	10		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T38	2		T138	11		T156	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	380	1			T7	3		T84	8		T87	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T84	7		T131	12		T132	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	1		T37	1		T39	3