Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28307

1

T1

15

T2

1

T3

145

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24778

1

T1

15

T2

1

T3

145

auto[ADC_CTRL_FILTER_COND_OUT]

3529

1

T4

1

T5

1

T6

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21369

1

T1

15

T3

143

T4

2

auto[1]

6938

1

T2

1

T3

2

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24199

1

T1

15

T2

1

T3

145

auto[1]

4108

1

T7

3

T11

20

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	922	1			T3	2		T5	1		T11	1
values[0]	34	1			T155	9		T257	1		T261	15
values[1]	720	1			T4	1		T52	33		T130	11
values[2]	2973	1			T6	10		T8	24		T10	10
values[3]	719	1			T4	1		T12	6		T36	7
values[4]	753	1			T87	11		T37	9		T132	49
values[5]	655	1			T2	1		T5	1		T145	1
values[6]	763	1			T55	1		T89	10		T38	4
values[7]	665	1			T36	6		T48	1		T145	2
values[8]	634	1			T5	1		T7	4		T11	29
values[9]	1191	1			T52	10		T41	2		T45	9
minimum	18278	1			T1	15		T3	143		T9	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	638	1			T4	1		T6	10		T52	17
values[1]	2950	1			T8	24		T10	10		T13	1
values[2]	811	1			T4	1		T12	6		T36	7
values[3]	804	1			T2	1		T5	1		T87	11
values[4]	604	1			T145	1		T132	16		T135	1
values[5]	754	1			T55	1		T36	6		T48	1
values[6]	587	1			T145	1		T140	13		T139	1
values[7]	800	1			T5	1		T7	4		T11	29
values[8]	1079	1			T52	10		T41	1		T45	9
values[9]	211	1			T5	1		T24	1		T156	10
minimum	19069	1			T1	15		T3	145		T9	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

4406

1

T6

9

T8

22

T10

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T4	1		T52	17		T141	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	10		T221	1		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1673	1			T8	24		T10	10		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T46	15		T138	1		T140	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T36	4		T91	1		T136	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T4	1		T12	2		T84	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	1		T132	12		T141	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T5	1		T87	1		T37	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T145	1		T132	9		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T230	11		T156	1		T164	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T89	3		T38	2		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T55	1		T36	3		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T145	1		T139	1		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T140	13		T15	3		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	1		T11	9		T41	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T7	1		T48	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T41	1		T84	7		T91	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T52	10		T45	9		T87	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T5	1		T156	1		T50	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T24	1		T17	1		T243	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18773	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T139	1		T15	5		T257	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T141	10		T211	2		T16	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T155	8		T26	12		T214	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T84	11		T137	33		T146	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T46	11		T138	8		T14	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T36	3		T91	7		T14	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	4		T84	7		T206	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T132	10		T141	11		T206	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T87	10		T37	3		T132	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T132	7		T234	10		T211	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T230	7		T156	12		T164	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T89	7		T38	2		T138	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T36	3		T154	12		T235	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T155	10		T190	7		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T15	1		T229	4		T224	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	20		T141	5		T26	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	3		T38	2		T131	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T84	8		T91	14		T130	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T87	2		T130	8		T38	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T156	9		T50	7		T219	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T243	7		T259	20		T158	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T55	1		T37	1		T130	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T151	5		T279	12		T222	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	672	1			T3	2		T5	1		T11	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T87	1		T130	1		T237	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T261	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T155	1		T257	1		T179	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T4	1		T52	33		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T139	1		T221	1		T15	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1682	1			T8	24		T10	10		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	10		T46	15		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T36	4		T91	1		T136	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	1		T12	2		T84	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T132	12		T208	10		T206	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T87	1		T37	6		T132	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	1		T145	1		T141	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T5	1		T148	1		T230	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T89	3		T38	2		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T55	1		T149	12		T208	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T145	1		T155	1		T190	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T36	3		T48	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	1		T11	9		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T7	1		T38	3		T131	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T41	2		T91	1		T39	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T52	10		T45	9		T48	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18144	1			T1	15		T3	143		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T84	8		T130	9		T142	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T87	2		T130	8		T237	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T155	8		T179	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T130	10		T131	12		T141	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T214	4		T187	7		T151	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T84	11		T137	33		T146	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T46	11		T138	8		T26	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T36	3		T91	7		T14	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	4		T84	7		T14	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T132	10		T206	14		T209	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T87	10		T37	3		T132	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T141	11		T211	2		T107	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T230	7		T156	12		T164	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T89	7		T38	2		T138	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T235	8		T216	8		T152	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T155	10		T190	7		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T36	3		T154	12		T229	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T11	20		T141	5		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T7	3		T38	2		T131	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T91	14		T39	5		T26	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T38	9		T202	9		T207	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	1		T37	1		T39	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T4	1		T52	1		T141	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	1		T221	1		T155	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T8	2		T10	1		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T46	12		T138	9		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T36	6		T91	8		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T4	1		T12	5		T84	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	1		T132	11		T141	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T5	1		T87	11		T37	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T145	1		T132	8		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T230	8		T156	13		T164	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T89	8		T38	4		T138	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T55	1		T36	5		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T145	1		T139	1		T155	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T140	1		T15	3		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	1		T11	21		T41	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	4		T48	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T41	1		T84	9		T91	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T52	1		T45	1		T87	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T5	1		T156	10		T50	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T24	1		T17	1		T243	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18886	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T139	1		T15	4		T257	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T52	16		T141	10		T16	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	9		T26	11		T214	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T8	22		T10	9		T53	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T46	14		T140	6		T14	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T36	1		T136	13		T134	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	1		T84	4		T206	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T132	11		T141	13		T208	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T37	3		T132	12		T215	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T132	8		T234	9		T264	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T230	10		T164	4		T216	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T89	2		T140	10		T142	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T36	1		T154	6		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T190	7		T208	10		T106	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T140	12		T15	1		T229	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	8		T141	5		T26	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T38	2		T131	8		T225	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T84	6		T39	3		T142	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T52	9		T45	8		T136	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T50	6		T223	4		T219	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T243	13		T259	15		T158	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T52	15		T131	7		T230	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T15	1		T151	4		T222	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	692	1			T3	2		T5	1		T11	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T87	3		T130	9		T237	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T261	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T155	9		T257	1		T179	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	1		T52	2		T130	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T139	1		T221	1		T15	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T8	2		T10	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T6	1		T46	12		T138	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T36	6		T91	8		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	1		T12	5		T84	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T132	11		T208	1		T206	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T87	11		T37	6		T132	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T2	1		T145	1		T141	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	1		T148	1		T230	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T89	8		T38	4		T138	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T55	1		T149	1		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T145	1		T155	11		T190	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T36	5		T48	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	1		T11	21		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T7	4		T38	3		T131	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T41	2		T91	15		T39	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T52	1		T45	1		T48	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18278	1			T1	15		T3	143		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T84	6		T142	17		T296	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T237	7		T297	10		T298	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T261	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T52	31		T131	7		T141	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T15	1		T214	11		T187	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T8	22		T10	9		T53	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T6	9		T46	14		T26	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T36	1		T136	13		T134	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	1		T84	4		T140	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T132	11		T208	9		T206	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T37	3		T132	12		T143	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T141	13		T230	3		T264	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T230	10		T164	4		T17	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T89	2		T140	10		T132	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T149	11		T208	11		T216	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T190	7		T208	10		T106	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T36	1		T140	12		T154	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T11	8		T141	5		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T38	2		T131	8		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T39	3		T26	15		T134	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T52	9		T45	8		T136	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

auto[0]

4406

1

T6

9

T8

22

T10

9