Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28307

1

T1

15

T2

1

T3

145

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24446

1

T1

15

T3

145

T5

2

auto[ADC_CTRL_FILTER_COND_OUT]

3861

1

T2

1

T4

2

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22114

1

T1

15

T3

145

T5

1

auto[1]

6193

1

T2

1

T4

2

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24199

1

T1

15

T2

1

T3

145

auto[1]

4108

1

T7

3

T11

20

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	296	1			T7	4		T52	17		T45	9
values[0]	28	1			T41	1		T245	13		T161	13
values[1]	866	1			T4	1		T36	7		T41	1
values[2]	718	1			T5	1		T48	1		T145	1
values[3]	623	1			T4	1		T131	33		T132	27
values[4]	3019	1			T8	24		T10	10		T13	1
values[5]	721	1			T5	1		T11	29		T12	6
values[6]	815	1			T2	1		T5	1		T52	16
values[7]	728	1			T6	10		T91	15		T37	9
values[8]	710	1			T46	26		T84	15		T138	21
values[9]	958	1			T48	1		T140	7		T132	16
minimum	18825	1			T1	15		T3	145		T9	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	727	1			T41	1		T84	23		T136	14
values[1]	912	1			T5	1		T48	1		T145	1
values[2]	487	1			T4	1		T87	11		T14	13
values[3]	3101	1			T8	24		T10	10		T11	29
values[4]	606	1			T5	1		T12	6		T89	10
values[5]	801	1			T2	1		T5	1		T52	16
values[6]	765	1			T6	10		T84	15		T37	9
values[7]	770	1			T46	26		T138	12		T140	24
values[8]	967	1			T7	4		T52	17		T48	1
values[9]	68	1			T45	9		T202	10		T230	18
minimum	19103	1			T1	15		T3	145		T4	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

4406

1

T6

9

T8

22

T10

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T39	8		T132	12		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T41	1		T84	12		T136	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T48	1		T145	1		T131	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	1		T38	3		T132	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T16	3		T280	3		T279	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T4	1		T87	1		T14	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1724	1			T8	24		T10	10		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	9		T55	1		T52	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	1		T12	2		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T89	3		T187	19		T188	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T5	1		T91	1		T141	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	1		T52	16		T36	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T6	10		T145	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T84	7		T37	6		T136	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T46	15		T138	1		T140	24
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T162	1		T24	1		T134	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T7	1		T38	2		T135	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T52	17		T48	1		T140	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T45	9		T202	1		T230	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T16	1		T99	1		T283	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18734	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T4	1		T36	4		T41	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T39	5		T132	10		T149	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T84	11		T155	10		T206	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T131	18		T154	12		T40	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T38	2		T132	14		T207	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T16	1		T279	6		T299	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T87	10		T14	7		T50	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T84	7		T137	33		T38	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T11	20		T91	7		T130	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T12	4		T130	9		T209	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T89	7		T187	7		T216	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T91	14		T141	10		T142	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T36	3		T14	9		T26	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T138	8		T141	5		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T84	8		T37	3		T130	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T46	11		T138	11		T131	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T134	20		T156	11		T300	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	3		T38	2		T214	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T132	7		T141	11		T155	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T202	9		T230	7		T301	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T283	14		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T55	1		T87	2		T37	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T36	3		T50	3		T216	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T7	1		T45	9		T38	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T52	17		T164	12		T110	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T245	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T41	1		T161	1		T295	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T87	1		T39	8		T132	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T4	1		T36	4		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T48	1		T145	1		T24	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	1		T38	3		T208	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T131	15		T154	7		T230	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T4	1		T132	13		T24	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1662	1			T8	24		T10	10		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T55	1		T52	10		T87	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T5	1		T12	2		T84	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T11	9		T89	3		T225	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	1		T130	1		T141	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T2	1		T52	16		T36	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	10		T91	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T37	6		T136	15		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T46	15		T138	2		T140	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T84	7		T190	8		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T135	2		T208	12		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T48	1		T140	7		T132	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18691	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T7	3		T38	2		T202	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T164	8		T285	8		T212	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T161	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T87	2		T39	5		T132	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T36	3		T84	11		T155	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T40	4		T188	14		T164	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T38	2		T209	30		T164	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T131	18		T154	12		T235	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T132	14		T207	13		T224	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	950	1			T137	33		T38	9		T146	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T87	10		T91	7		T130	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	4		T84	7		T209	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	20		T89	7		T187	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T130	9		T141	10		T142	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T36	3		T14	9		T26	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T91	14		T141	5		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T37	3		T130	10		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T46	11		T138	19		T131	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T84	8		T190	7		T134	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T214	13		T211	2		T230	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T132	7		T141	11		T155	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	1		T37	1		T39	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T39	10		T132	11		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T41	1		T84	12		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T48	1		T145	1		T131	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T5	1		T38	3		T132	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T16	3		T280	1		T279	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T4	1		T87	11		T14	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1344	1			T8	2		T10	1		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	21		T55	1		T52	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	1		T12	5		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T89	8		T187	8		T188	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	1		T91	15		T141	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T2	1		T52	1		T36	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	1		T145	1		T138	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T84	9		T37	6		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T46	12		T138	12		T140	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T162	1		T24	1		T134	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T7	4		T38	4		T135	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T52	1		T48	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T45	1		T202	10		T230	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T16	1		T99	1		T283	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18872	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T4	1		T36	6		T41	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T39	3		T132	11		T245	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T84	11		T136	13		T206	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T131	14		T154	6		T40	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T38	2		T132	12		T208	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T16	1		T280	2		T279	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T14	1		T50	6		T255	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T8	22		T10	9		T53	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T11	8		T52	9		T131	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T12	1		T225	9		T187	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T89	2		T187	18		T188	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T141	10		T149	11		T142	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T52	15		T36	1		T26	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	9		T141	5		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T84	6		T37	3		T136	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T46	14		T140	22		T131	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T134	14		T15	1		T208	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T208	11		T214	11		T215	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T52	16		T140	6		T132	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T45	8		T230	10		T223	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T283	7		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T143	17		T108	4		T302	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T36	1		T206	6		T50	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T7	4		T45	1		T38	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T52	1		T164	9		T110	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T245	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T41	1		T161	13		T295	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T87	3		T39	10		T132	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T4	1		T36	6		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T48	1		T145	1		T24	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	1		T38	3		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T131	19		T154	13		T230	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T4	1		T132	15		T24	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T8	2		T10	1		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T55	1		T52	1		T87	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	1		T12	5		T84	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	21		T89	8		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	1		T130	10		T141	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T2	1		T52	1		T36	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	1		T91	15		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T37	6		T136	1		T130	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T46	12		T138	21		T140	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T84	9		T190	8		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T135	2		T208	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T48	1		T140	1		T132	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18825	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T45	8		T215	10		T223	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T52	16		T164	11		T285	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T245	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T39	3		T132	11		T143	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T36	1		T84	11		T136	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T40	3		T188	12		T226	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T38	2		T208	9		T164	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T131	14		T154	6		T230	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T132	12		T224	10		T50	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T8	22		T10	9		T53	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T52	9		T131	7		T14	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	1		T84	4		T225	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	8		T89	2		T225	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T141	10		T149	11		T142	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T52	15		T36	1		T26	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	9		T141	5		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T37	3		T136	14		T214	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T46	14		T140	22		T131	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T84	6		T190	7		T134	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T208	11		T214	11		T230	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T140	6		T132	8		T141	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

auto[0]

4406

1

T6

9

T8

22

T10

9