Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28307

1

T1

15

T2

1

T3

145

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24447

1

T1

15

T3

145

T5

2

auto[ADC_CTRL_FILTER_COND_OUT]

3860

1

T2

1

T4

2

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22128

1

T1

15

T3

145

T5

1

auto[1]

6179

1

T2

1

T4

2

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24199

1

T1

15

T2

1

T3

145

auto[1]

4108

1

T7

3

T11

20

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	21	1			T303	15		T304	3		T22	3
values[0]	96	1			T50	14		T17	1		T237	9
values[1]	790	1			T4	1		T36	7		T41	2
values[2]	740	1			T5	1		T48	1		T145	1
values[3]	675	1			T4	1		T131	33		T132	27
values[4]	2980	1			T8	24		T10	10		T13	1
values[5]	722	1			T11	29		T12	6		T84	12
values[6]	806	1			T2	1		T5	2		T52	16
values[7]	666	1			T91	15		T37	9		T145	1
values[8]	724	1			T6	10		T46	26		T84	15
values[9]	1262	1			T7	4		T52	17		T45	9
minimum	18825	1			T1	15		T3	145		T9	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	987	1			T4	1		T36	7		T41	1
values[1]	895	1			T5	1		T48	1		T145	1
values[2]	527	1			T4	1		T87	11		T14	13
values[3]	3068	1			T8	24		T10	10		T11	29
values[4]	661	1			T5	1		T12	6		T84	12
values[5]	770	1			T2	1		T5	1		T36	6
values[6]	742	1			T6	10		T52	16		T37	9
values[7]	778	1			T46	26		T84	15		T140	31
values[8]	908	1			T7	4		T52	17		T48	1
values[9]	131	1			T45	9		T202	10		T16	1
minimum	18840	1			T1	15		T3	145		T9	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

4406

1

T6

9

T8

22

T10

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T87	1		T39	8		T132	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T4	1		T36	4		T41	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T48	1		T145	1		T131	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T5	1		T38	3		T132	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T231	1		T16	3		T280	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	1		T87	1		T14	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1723	1			T8	24		T10	10		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	9		T55	1		T52	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	1		T12	2		T84	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T89	3		T187	19		T215	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T5	1		T91	1		T141	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T2	1		T36	3		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	10		T145	1		T138	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T52	16		T37	6		T136	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T46	15		T140	24		T210	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T84	7		T140	7		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T7	1		T38	2		T135	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T52	17		T48	1		T132	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T45	9		T202	1		T16	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T110	1		T268	7		T303	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18698	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T41	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T87	2		T39	5		T132	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T36	3		T84	11		T155	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T131	18		T154	12		T40	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T38	2		T132	14		T207	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T16	1		T279	6		T299	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T87	10		T14	7		T50	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	986	1			T137	33		T38	9		T146	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	20		T91	7		T130	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T12	4		T84	7		T130	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T89	7		T187	7		T156	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T91	14		T141	10		T142	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T36	3		T130	10		T14	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T138	19		T131	8		T141	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T37	3		T190	7		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T46	11		T206	14		T246	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T84	8		T134	20		T300	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	3		T38	2		T214	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T132	7		T141	11		T155	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T202	9		T304	2		T297	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T268	13		T303	12		T305	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T55	1		T37	1		T39	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T304	1		T22	2		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T303	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T17	1		T237	1		T245	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T50	11		T165	16		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T87	1		T39	8		T132	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T4	1		T36	4		T41	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T48	1		T145	1		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	1		T38	3		T208	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T131	15		T154	7		T230	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T4	1		T132	13		T24	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1666	1			T8	24		T10	10		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T55	1		T52	10		T87	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T12	2		T84	5		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	9		T89	3		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	2		T130	1		T141	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T2	1		T52	16		T36	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T91	1		T145	1		T141	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T37	6		T136	15		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T6	10		T46	15		T138	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T84	7		T140	7		T190	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	386	1			T7	1		T45	9		T38	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T52	17		T48	1		T132	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18691	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T304	2		T22	1		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T303	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T237	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T50	3		T161	12		T220	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T87	2		T39	5		T132	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T36	3		T84	11		T155	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T149	1		T40	4		T188	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T38	2		T206	2		T209	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T131	18		T154	12		T235	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T132	14		T207	13		T224	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	957	1			T137	33		T38	9		T146	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T87	10		T91	7		T130	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	4		T84	7		T215	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	20		T89	7		T187	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T130	9		T141	10		T142	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T36	3		T14	9		T26	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T91	14		T141	5		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T37	3		T130	10		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T46	11		T138	19		T131	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T84	8		T190	7		T134	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T7	3		T38	2		T202	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T132	7		T141	11		T155	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	1		T37	1		T39	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T87	3		T39	10		T132	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T4	1		T36	6		T41	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T48	1		T145	1		T131	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T5	1		T38	3		T132	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T231	1		T16	3		T280	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T4	1		T87	11		T14	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T8	2		T10	1		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	21		T55	1		T52	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	1		T12	5		T84	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T89	8		T187	8		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	1		T91	15		T141	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T2	1		T36	5		T130	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	1		T145	1		T138	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T52	1		T37	6		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T46	12		T140	2		T210	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T84	9		T140	1		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T7	4		T38	4		T135	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T52	1		T48	1		T132	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T45	1		T202	10		T16	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T110	1		T268	14		T303	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18835	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T41	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T39	3		T132	11		T143	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T36	1		T84	11		T136	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T131	14		T154	6		T40	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T38	2		T132	12		T208	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T16	1		T280	2		T279	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T14	1		T50	6		T255	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T8	22		T10	9		T53	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T11	8		T52	9		T131	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T12	1		T84	4		T225	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T89	2		T187	18		T215	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T141	10		T149	11		T142	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T36	1		T26	11		T143	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T6	9		T131	8		T141	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T52	15		T37	3		T136	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T46	14		T140	22		T206	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T84	6		T140	6		T134	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T208	11		T214	11		T230	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T52	16		T132	8		T141	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T45	8		T223	1		T297	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T268	6		T303	2		T305	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T108	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T304	3		T22	2		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T303	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T17	1		T237	9		T245	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T50	7		T165	1		T161	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T87	3		T39	10		T132	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T4	1		T36	6		T41	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T48	1		T145	1		T149	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	1		T38	3		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T131	19		T154	13		T230	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	1		T132	15		T24	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1293	1			T8	2		T10	1		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T55	1		T52	1		T87	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	5		T84	8		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T11	21		T89	8		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	2		T130	10		T141	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T2	1		T52	1		T36	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T91	15		T145	1		T141	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T37	6		T136	1		T130	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	1		T46	12		T138	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T84	9		T140	1		T190	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T7	4		T45	1		T38	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T52	1		T48	1		T132	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18825	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T22	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T303	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T245	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T50	7		T165	15		T220	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T39	3		T132	11		T143	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T36	1		T84	11		T136	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T40	3		T188	12		T226	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T38	2		T208	9		T206	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T131	14		T154	6		T230	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T132	12		T224	10		T50	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T8	22		T10	9		T53	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T52	9		T131	7		T14	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	1		T84	4		T225	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T11	8		T89	2		T225	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T141	10		T149	11		T142	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T52	15		T36	1		T26	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T141	5		T15	1		T214	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T37	3		T136	14		T214	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	9		T46	14		T140	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T84	6		T140	6		T190	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T45	8		T208	11		T214	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T52	16		T132	8		T141	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

auto[0]

4406

1

T6

9

T8

22

T10

9