Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28307

1

T1

15

T2

1

T3

145

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22214

1

T1

15

T2

1

T3

145

auto[ADC_CTRL_FILTER_COND_OUT]

6093

1

T8

24

T10

10

T12

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21980

1

T1

15

T3

145

T4

2

auto[1]

6327

1

T2

1

T5

1

T6

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24199

1

T1

15

T2

1

T3

145

auto[1]

4108

1

T7

3

T11

20

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	388	1			T4	1		T139	2		T154	19
values[0]	36	1			T209	17		T151	10		T270	9
values[1]	789	1			T4	1		T6	10		T7	4
values[2]	463	1			T5	1		T41	1		T145	1
values[3]	678	1			T84	15		T37	9		T38	4
values[4]	695	1			T52	16		T84	12		T89	10
values[5]	904	1			T5	1		T55	1		T52	17
values[6]	828	1			T2	1		T48	1		T91	15
values[7]	559	1			T52	10		T36	6		T41	1
values[8]	639	1			T11	29		T36	7		T45	9
values[9]	3503	1			T5	1		T8	24		T10	10
minimum	18825	1			T1	15		T3	145		T9	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	690	1			T4	1		T6	10		T7	4
values[1]	2880	1			T5	1		T8	24		T10	10
values[2]	647	1			T84	15		T89	10		T37	9
values[3]	841	1			T52	16		T84	12		T87	11
values[4]	832	1			T2	1		T5	1		T55	1
values[5]	800	1			T48	1		T91	15		T145	1
values[6]	497	1			T52	10		T36	6		T41	1
values[7]	716	1			T11	29		T36	7		T45	9
values[8]	1157	1			T5	1		T12	6		T87	3
values[9]	132	1			T4	1		T141	21		T154	19
minimum	19115	1			T1	15		T3	145		T9	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

4406

1

T6

9

T8

22

T10

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T4	1		T6	10		T7	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T136	14		T130	1		T141	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	1		T135	1		T307	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1670	1			T8	24		T10	10		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T84	7		T131	15		T40	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T89	3		T37	6		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T84	5		T87	1		T131	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T52	16		T208	11		T206	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	1		T5	1		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T46	15		T145	1		T38	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T145	1		T206	3		T235	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T48	1		T91	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T36	3		T41	1		T24	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T52	10		T135	1		T234	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T11	9		T36	4		T45	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T48	1		T130	1		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T5	1		T87	1		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T12	2		T138	1		T140	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T4	1		T17	3		T264	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T141	11		T154	7		T257	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18776	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T224	7		T255	14		T144	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	3		T149	1		T142	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T130	9		T141	11		T14	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T50	3		T144	13		T308	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	980	1			T137	33		T146	23		T132	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T84	8		T131	18		T40	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T89	7		T37	3		T38	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T84	7		T87	10		T131	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T187	7		T235	8		T156	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T130	8		T164	2		T216	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T46	11		T38	9		T209	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T206	2		T235	5		T216	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T91	14		T138	8		T131	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T36	3		T265	10		T160	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T234	10		T236	15		T293	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	20		T36	3		T84	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T130	10		T14	9		T26	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T87	2		T138	11		T134	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T12	4		T155	18		T230	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T17	3		T242	5		T305	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T141	10		T154	12		T309	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T55	1		T91	7		T37	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T224	2		T144	11		T151	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T4	1		T139	2		T250	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T154	7		T155	1		T16	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T209	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T151	5		T270	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T4	1		T6	10		T7	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T136	14		T141	14		T14	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T145	1		T142	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T41	1		T136	15		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T84	7		T131	15		T40	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T37	6		T38	2		T132	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T84	5		T131	8		T132	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T52	16		T89	3		T190	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	1		T55	1		T52	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T46	15		T38	3		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	1		T145	1		T206	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T48	1		T91	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T36	3		T41	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T52	10		T210	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	9		T36	4		T45	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T48	1		T130	1		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	369	1			T5	1		T87	1		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1842	1			T8	24		T10	10		T12	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18691	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T250	2		T244	2		T248	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T154	12		T155	10		T16	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T209	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T151	5		T270	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	3		T91	7		T149	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T141	11		T14	7		T214	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T142	6		T214	13		T50	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T130	9		T206	14		T188	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T84	8		T131	18		T40	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T37	3		T38	2		T132	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T84	7		T131	12		T132	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T89	7		T190	7		T187	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T87	10		T130	8		T164	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T46	11		T38	9		T209	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T206	2		T216	8		T18	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T91	14		T138	8		T131	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T36	3		T235	5		T218	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T15	1		T236	15		T293	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T11	20		T36	3		T84	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T130	10		T14	9		T26	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T87	2		T138	11		T134	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1065	1			T12	4		T137	33		T146	23
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	1		T37	1		T39	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T4	1		T6	1		T7	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T136	1		T130	10		T141	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T5	1		T135	1		T307	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1323	1			T8	2		T10	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T84	9		T131	19		T40	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T89	8		T37	6		T38	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T84	8		T87	11		T131	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T52	1		T208	1		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	1		T5	1		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T46	12		T145	1		T38	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T145	1		T206	3		T235	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T48	1		T91	15		T138	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T36	5		T41	1		T24	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T52	1		T135	1		T234	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	21		T36	6		T45	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T48	1		T130	11		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T5	1		T87	3		T138	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T12	5		T138	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T4	1		T17	4		T264	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T141	11		T154	13		T257	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18892	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T224	3		T255	1		T144	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	9		T142	9		T225	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T136	13		T141	13		T14	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T226	13		T50	7		T223	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1327	1			T8	22		T10	9		T53	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T84	6		T131	14		T40	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T89	2		T37	3		T190	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T84	4		T131	7		T132	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T52	15		T208	10		T206	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T52	16		T188	9		T164	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T46	14		T38	1		T143	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T206	2		T235	6		T216	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T131	8		T39	3		T142	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T36	1		T265	18		T160	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T52	9		T234	9		T236	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	8		T36	1		T45	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T26	11		T224	10		T106	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T140	10		T134	14		T208	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T12	1		T140	12		T230	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T17	2		T242	5		T305	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T141	10		T154	6		T309	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T158	3		T310	2		T168	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T224	6		T255	13		T151	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T4	1		T139	2		T250	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T154	13		T155	11		T16	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T209	17		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T151	6		T270	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T4	1		T6	1		T7	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T136	1		T141	12		T14	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T5	1		T145	1		T142	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T41	1		T136	1		T130	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T84	9		T131	19		T40	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T37	6		T38	4		T132	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T84	8		T131	13		T132	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T52	1		T89	8		T190	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	1		T55	1		T52	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T46	12		T38	11		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T2	1		T145	1		T206	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T48	1		T91	15		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T36	5		T41	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T52	1		T210	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	21		T36	6		T45	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T48	1		T130	11		T14	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T5	1		T87	3		T138	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1438	1			T8	2		T10	1		T12	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18825	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T250	2		T244	4		T248	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T154	6		T16	1		T17	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T151	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T6	9		T214	11		T164	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T136	13		T141	13		T14	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T142	9		T225	12		T214	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T136	14		T206	12		T188	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T84	6		T131	14		T40	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T37	3		T132	12		T208	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T84	4		T131	7		T132	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T52	15		T89	2		T190	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T52	16		T15	1		T188	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T46	14		T38	1		T208	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T206	2		T216	9		T223	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T131	8		T39	3		T142	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T36	1		T235	6		T222	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T52	9		T15	1		T236	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	8		T36	1		T45	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T26	11		T234	9		T224	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T140	16		T134	14		T208	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1469	1			T8	22		T10	9		T12	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

auto[0]

4406

1

T6

9

T8

22

T10

9