Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28307

1

T1

15

T2

1

T3

145

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22212

1

T1

15

T2

1

T3

145

auto[ADC_CTRL_FILTER_COND_OUT]

6095

1

T8

24

T10

10

T12

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21924

1

T1

15

T3

145

T4

2

auto[1]

6383

1

T2

1

T5

1

T6

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24199

1

T1

15

T2

1

T3

145

auto[1]

4108

1

T7

3

T11

20

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	43	1			T140	13		T274	13		T21	1
values[0]	42	1			T16	1		T151	10		T270	9
values[1]	767	1			T7	4		T91	8		T136	14
values[2]	490	1			T4	1		T5	1		T6	10
values[3]	704	1			T84	15		T37	9		T38	4
values[4]	676	1			T52	16		T84	12		T89	10
values[5]	891	1			T5	1		T52	17		T46	26
values[6]	793	1			T2	1		T55	1		T36	6
values[7]	571	1			T52	10		T41	1		T48	1
values[8]	616	1			T11	29		T36	7		T45	9
values[9]	3889	1			T4	1		T5	1		T8	24
minimum	18825	1			T1	15		T3	145		T9	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	893	1			T4	1		T6	10		T7	4
values[1]	2877	1			T5	1		T8	24		T10	10
values[2]	643	1			T84	15		T89	10		T37	9
values[3]	808	1			T52	16		T84	12		T87	11
values[4]	860	1			T2	1		T5	1		T55	1
values[5]	760	1			T52	10		T48	1		T91	15
values[6]	528	1			T36	6		T41	1		T24	1
values[7]	720	1			T11	29		T36	7		T45	9
values[8]	1125	1			T5	1		T87	3		T138	1
values[9]	187	1			T4	1		T12	6		T138	12
minimum	18906	1			T1	15		T3	145		T9	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

4406

1

T6

9

T8

22

T10

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T4	1		T6	10		T7	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T41	1		T136	14		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	1		T135	1		T225	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1681	1			T8	24		T10	10		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T84	7		T131	15		T40	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T89	3		T37	6		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T84	5		T87	1		T131	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T52	16		T208	11		T206	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T2	1		T5	1		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T46	15		T145	1		T231	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T145	1		T15	3		T206	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T52	10		T48	1		T91	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T36	3		T41	1		T24	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T135	1		T234	10		T272	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T11	9		T36	4		T45	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T48	1		T130	1		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T5	1		T87	1		T140	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T138	1		T140	13		T155	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T4	1		T138	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T12	2		T141	11		T154	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18725	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T286	1		T289	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	3		T91	7		T149	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T130	9		T141	11		T14	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T308	14		T311	2		T312	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	992	1			T137	33		T146	23		T132	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T84	8		T131	18		T40	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T89	7		T37	3		T38	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T84	7		T87	10		T131	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T235	8		T156	12		T107	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T130	8		T132	7		T188	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T46	11		T209	1		T187	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	1		T206	2		T235	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T91	14		T38	9		T138	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T36	3		T18	1		T160	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T234	10		T236	15		T219	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T11	20		T36	3		T84	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T130	10		T14	9		T26	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T87	2		T132	10		T134	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T155	18		T16	1		T164	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T138	11		T17	3		T242	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T12	4		T141	10		T154	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T55	1		T37	1		T39	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T286	16		T289	4		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T21	1		T311	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T140	13		T274	1		T309	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T268	7		T313	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T16	1		T151	5		T270	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T7	1		T91	1		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T136	14		T141	14		T14	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T4	1		T5	1		T6	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T41	1		T136	15		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T84	7		T131	15		T40	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T37	6		T38	2		T132	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T84	5		T131	8		T132	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T52	16		T89	3		T190	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	1		T52	17		T87	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T46	15		T38	3		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T2	1		T55	1		T36	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T91	1		T145	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T41	1		T24	1		T15	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T52	10		T48	1		T210	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	9		T36	4		T45	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T48	1		T14	1		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	444	1			T4	1		T5	1		T87	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1952	1			T8	24		T10	10		T12	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18691	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T311	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T274	12		T309	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T268	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T151	5		T270	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	3		T91	7		T149	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T141	11		T14	7		T214	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T142	6		T50	3		T259	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T130	9		T206	14		T188	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T84	8		T131	18		T40	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T37	3		T38	2		T132	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T84	7		T131	12		T132	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T89	7		T190	7		T187	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T87	10		T130	8		T164	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T46	11		T38	9		T209	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T36	3		T206	2		T188	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T91	14		T138	8		T131	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T235	5		T218	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T236	15		T219	18		T293	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T11	20		T36	3		T84	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	9		T26	12		T234	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T87	2		T138	11		T134	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1203	1			T12	4		T137	33		T130	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	1		T37	1		T39	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T4	1		T6	1		T7	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T41	1		T136	1		T130	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T5	1		T135	1		T225	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1335	1			T8	2		T10	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T84	9		T131	19		T40	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T89	8		T37	6		T38	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T84	8		T87	11		T131	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T52	1		T208	1		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	1		T5	1		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T46	12		T145	1		T231	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T145	1		T15	3		T206	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T52	1		T48	1		T91	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T36	5		T41	1		T24	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T135	1		T234	11		T272	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	21		T36	6		T45	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T48	1		T130	11		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T5	1		T87	3		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T138	1		T140	1		T155	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T4	1		T138	12		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T12	5		T141	11		T154	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18851	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T286	17		T289	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T6	9		T142	9		T214	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T136	13		T141	13		T14	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T225	12		T226	13		T223	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1338	1			T8	22		T10	9		T53	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T84	6		T131	14		T40	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T89	2		T37	3		T190	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T84	4		T131	7		T141	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T52	15		T208	10		T206	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T52	16		T132	8		T188	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T46	14		T143	6		T187	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	1		T206	2		T235	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T52	9		T38	1		T131	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T36	1		T160	14		T249	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T234	9		T236	3		T219	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T11	8		T36	1		T45	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T26	11		T224	10		T106	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T140	10		T132	11		T134	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T140	12		T16	1		T164	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T17	2		T242	5		T277	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T12	1		T141	10		T154	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T259	7		T314	2		T315	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T289	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T21	1		T311	3		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T140	1		T274	13		T309	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T268	14		T313	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T16	1		T151	6		T270	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	4		T91	8		T149	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T136	1		T141	12		T14	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T4	1		T5	1		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T41	1		T136	1		T130	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T84	9		T131	19		T40	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T37	6		T38	4		T132	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T84	8		T131	13		T132	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T52	1		T89	8		T190	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	1		T52	1		T87	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T46	12		T38	11		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	1		T55	1		T36	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T91	15		T145	1		T138	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T41	1		T24	1		T15	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T52	1		T48	1		T210	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	21		T36	6		T45	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T48	1		T14	10		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	374	1			T4	1		T5	1		T87	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1596	1			T8	2		T10	1		T12	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18825	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T140	12		T309	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T268	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T151	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T214	22		T164	2		T50	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T136	13		T141	13		T14	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T6	9		T142	9		T225	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T136	14		T206	12		T188	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T84	6		T131	14		T40	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T37	3		T132	12		T208	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T84	4		T131	7		T132	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T52	15		T89	2		T190	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T52	16		T15	1		T188	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T46	14		T38	1		T208	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T36	1		T206	2		T188	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T131	8		T39	3		T142	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T15	1		T235	6		T277	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T52	9		T236	3		T219	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	8		T36	1		T45	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T26	11		T234	9		T224	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T140	16		T134	14		T208	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1559	1			T8	22		T10	9		T12	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

auto[0]

4406

1

T6

9

T8

22

T10

9