Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28307

1

T1

15

T2

1

T3

145

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

25036

1

T1

15

T2

1

T3

145

auto[ADC_CTRL_FILTER_COND_OUT]

3271

1

T4

2

T5

2

T11

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22000

1

T1

15

T3

145

T5

1

auto[1]

6307

1

T2

1

T4

2

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24199

1

T1

15

T2

1

T3

145

auto[1]

4108

1

T7

3

T11

20

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	231	1			T7	4		T140	7		T190	15
values[0]	68	1			T160	30		T21	1		T316	6
values[1]	708	1			T5	1		T36	7		T145	1
values[2]	688	1			T5	1		T6	10		T36	6
values[3]	784	1			T52	16		T84	23		T145	1
values[4]	768	1			T12	6		T41	1		T45	9
values[5]	3096	1			T4	1		T8	24		T10	10
values[6]	657	1			T11	29		T52	10		T41	1
values[7]	570	1			T130	11		T132	16		T221	1
values[8]	732	1			T5	1		T55	1		T38	5
values[9]	1180	1			T2	1		T4	1		T48	1
minimum	18825	1			T1	15		T3	145		T9	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	771	1			T36	13		T145	2		T130	10
values[1]	744	1			T5	1		T6	10		T84	23
values[2]	814	1			T52	16		T145	1		T38	16
values[3]	3140	1			T8	24		T10	10		T12	6
values[4]	558	1			T4	1		T52	17		T46	26
values[5]	704	1			T11	29		T52	10		T41	1
values[6]	593	1			T55	1		T130	11		T38	5
values[7]	824	1			T2	1		T5	1		T87	3
values[8]	1000	1			T4	1		T7	4		T48	1
values[9]	153	1			T132	27		T134	15		T208	11
minimum	19006	1			T1	15		T3	145		T5	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

4406

1

T6

9

T8

22

T10

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T36	3		T145	1		T142	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T36	4		T145	1		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	1		T6	10		T138	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T84	12		T136	15		T231	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T52	16		T145	1		T38	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T135	1		T214	12		T207	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1745	1			T8	24		T10	10		T12	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T41	1		T140	11		T134	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T130	1		T142	18		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T4	1		T52	17		T46	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T41	1		T37	6		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	9		T52	10		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T55	1		T221	1		T210	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T130	1		T38	3		T132	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T2	1		T87	1		T91	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	1		T136	14		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T7	1		T84	7		T91	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T4	1		T48	1		T84	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T134	5		T208	11		T189	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T132	13		T232	10		T281	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18747	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T5	1		T211	1		T110	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T36	3		T142	6		T15	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T36	3		T130	9		T155	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T138	8		T131	18		T141	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T84	11		T218	2		T233	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T38	11		T141	11		T187	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T214	13		T207	13		T211	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1056	1			T12	4		T89	7		T137	33
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T134	10		T214	4		T107	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T130	8		T142	14		T233	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T46	11		T87	10		T224	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T37	3		T155	8		T234	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	20		T26	12		T209	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T187	2		T235	8		T17	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T130	10		T38	2		T132	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T87	2		T91	14		T131	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T138	11		T216	8		T236	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T7	3		T84	8		T91	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T84	7		T131	12		T190	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T134	10		T252	4		T317	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T132	14		T239	10		T318	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T55	1		T37	1		T39	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T211	2		T285	4		T212	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T7	1		T208	11		T147	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T140	7		T190	8		T208	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T160	16		T21	1		T316	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T241	5		T319	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T138	1		T142	10		T15	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	1		T36	4		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T6	10		T36	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T136	15		T130	1		T14	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T52	16		T145	1		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T84	12		T135	1		T214	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T12	2		T45	9		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T41	1		T140	11		T143	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1759	1			T8	24		T10	10		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T4	1		T52	17		T46	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T41	1		T37	6		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	9		T52	10		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T221	1		T40	4		T187	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T130	1		T132	9		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T55	1		T131	9		T132	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T5	1		T38	3		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T2	1		T84	7		T87	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T4	1		T48	1		T84	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18691	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T7	3		T224	2		T236	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T190	7		T230	6		T215	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T160	14		T316	1		T320	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T241	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T138	8		T142	6		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T36	3		T155	10		T211	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T36	3		T131	18		T206	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T130	9		T14	7		T206	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T38	2		T141	10		T14	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T84	11		T214	13		T207	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	4		T89	7		T38	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T211	2		T16	11		T107	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T137	33		T130	8		T146	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T46	11		T87	10		T134	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T37	3		T155	8		T234	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T11	20		T26	12		T209	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T40	3		T187	2		T188	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T130	10		T132	7		T144	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T131	8		T132	10		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T38	2		T138	11		T156	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T84	8		T87	2		T91	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T84	7		T131	12		T132	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	1		T37	1		T39	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T36	5		T145	1		T142	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T36	6		T145	1		T130	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	1		T6	1		T138	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T84	12		T136	1		T231	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T52	1		T145	1		T38	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T135	1		T214	14		T207	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1409	1			T8	2		T10	1		T12	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T41	1		T140	1		T134	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T130	9		T142	15		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T4	1		T52	1		T46	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T41	1		T37	6		T155	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T11	21		T52	1		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T55	1		T221	1		T210	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T130	11		T38	3		T132	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T2	1		T87	3		T91	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	1		T136	1		T138	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T7	4		T84	9		T91	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T4	1		T48	1		T84	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T134	11		T208	1		T189	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T132	15		T232	1		T281	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18900	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T5	1		T211	3		T110	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T36	1		T142	9		T15	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T36	1		T14	1		T206	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T6	9		T131	14		T141	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T84	11		T136	14		T206	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T52	15		T38	1		T141	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T214	11		T16	15		T243	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T8	22		T10	9		T12	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T140	10		T134	10		T214	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T142	17		T208	9		T228	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T52	16		T46	14		T140	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T37	3		T234	9		T40	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	8		T52	9		T26	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T187	4		T17	2		T150	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T38	2		T132	8		T108	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T131	8		T39	3		T132	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T136	13		T225	9		T188	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T84	6		T154	6		T26	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T84	4		T140	6		T131	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T134	4		T208	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T132	12		T232	9		T281	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T235	6		T106	12		T263	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T285	4		T212	6		T321	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T7	4		T208	1		T147	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T140	1		T190	8		T208	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T160	15		T21	1		T316	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T241	13		T319	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T138	9		T142	7		T15	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T5	1		T36	6		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	1		T6	1		T36	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T136	1		T130	10		T14	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T52	1		T145	1		T38	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T84	12		T135	1		T214	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	5		T45	1		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T41	1		T140	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T8	2		T10	1		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	1		T52	1		T46	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T41	1		T37	6		T155	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	21		T52	1		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T221	1		T40	5		T187	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T130	11		T132	8		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T55	1		T131	9		T132	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	1		T38	3		T138	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	429	1			T2	1		T84	9		T87	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T4	1		T48	1		T84	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18825	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T208	10		T143	6		T224	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T140	6		T190	7		T208	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T160	15		T316	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T241	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T142	9		T15	1		T230	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T36	1		T230	3		T165	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T6	9		T36	1		T131	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T136	14		T14	1		T206	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T52	15		T141	10		T246	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T84	11		T214	11		T243	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	1		T45	8		T89	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T140	10		T143	17		T229	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1406	1			T8	22		T10	9		T53	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T52	16		T46	14		T140	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T37	3		T234	9		T208	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	8		T52	9		T26	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T40	2		T187	4		T188	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T132	8		T108	12		T223	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T131	8		T132	11		T225	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T38	2		T225	9		T188	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T84	6		T39	3		T141	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T84	4		T136	13		T131	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

auto[0]

4406

1

T6

9

T8

22

T10

9