Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T36	5		T145	1		T131	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	1		T36	6		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	1		T6	1		T138	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T84	12		T136	1		T231	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T145	1		T38	15		T141	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T52	1		T135	1		T214	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T8	2		T10	1		T12	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T41	1		T140	1		T134	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T130	9		T142	15		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T4	1		T11	21		T52	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T41	1		T37	6		T155	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T52	1		T221	1		T24	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T55	1		T221	1		T210	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	1		T130	11		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T2	1		T87	3		T91	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T136	1		T225	1		T188	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T7	4		T84	9		T26	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T4	1		T48	1		T84	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T91	8		T208	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T140	1		T132	15		T232	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18826	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T170	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T36	1		T131	14		T142	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T36	1		T14	1		T206	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	9		T141	10		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T84	11		T136	14		T206	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T38	1		T141	13		T187	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T52	15		T214	11		T229	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1373	1			T8	22		T10	9		T12	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T140	10		T134	10		T214	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T142	17		T208	9		T228	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	8		T52	16		T46	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T37	3		T234	9		T40	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T52	9		T26	11		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T150	10		T222	14		T168	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T38	2		T132	8		T108	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T131	8		T39	3		T132	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T136	13		T225	9		T188	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T84	6		T26	15		T134	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T84	4		T131	7		T190	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T208	10		T100	8		T170	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T140	6		T132	12		T232	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T226	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T34	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T230	8		T160	15		T35	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T36	6		T165	1		T240	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T138	9		T142	7		T15	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T5	1		T145	1		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	1		T6	1		T36	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T130	10		T14	12		T231	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T145	1		T38	4		T141	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T52	1		T84	12		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	5		T45	1		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T41	1		T140	1		T207	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T8	2		T10	1		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T4	1		T52	1		T46	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T41	1		T37	6		T155	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	21		T52	1		T87	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T139	1		T221	1		T40	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T132	8		T24	1		T108	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T55	1		T131	9		T132	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	1		T38	3		T138	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	472	1			T2	1		T7	4		T84	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	357	1			T4	1		T48	1		T84	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18825	1			T1	15		T3	145		T9	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T230	10		T160	15		T35	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T36	1		T165	14		T240	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T142	9		T15	1		T235	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T230	3		T245	12		T242	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T6	9		T36	1		T131	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	1		T206	18		T244	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T141	10		T246	12		T164	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T52	15		T84	11		T136	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	1		T45	8		T89	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T140	10		T143	17		T229	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1408	1			T8	22		T10	9		T53	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T52	16		T46	14		T140	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T37	3		T234	9		T208	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	8		T52	9		T26	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T40	2		T187	4		T188	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T132	8		T108	12		T223	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T131	8		T132	11		T225	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T38	2		T15	1		T225	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T84	6		T39	3		T141	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T84	4		T136	13		T140	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

auto[0]

4406

1

T6

9

T8

22

T10

9