Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28307

1

T1

15

T2

1

T3

145

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24486

1

T1

15

T2

1

T3

145

auto[ADC_CTRL_FILTER_COND_OUT]

3821

1

T4

2

T5

2

T52

33

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22201

1

T1

15

T2

1

T3

145

auto[1]

6106

1

T5

1

T8

24

T10

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24199

1

T1

15

T2

1

T3

145

auto[1]

4108

1

T7

3

T11

20

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	372	1			T52	10		T84	12		T89	10
values[0]	2	1			T157	1		T247	1		-	-
values[1]	747	1			T6	10		T48	1		T37	9
values[2]	671	1			T4	1		T5	1		T7	4
values[3]	744	1			T2	1		T41	1		T46	26
values[4]	636	1			T52	17		T36	7		T48	1
values[5]	3178	1			T8	24		T10	10		T11	29
values[6]	786	1			T12	6		T36	6		T87	3
values[7]	557	1			T5	1		T41	1		T45	9
values[8]	783	1			T4	1		T84	23		T87	11
values[9]	1006	1			T5	1		T130	20		T38	12
minimum	18825	1			T1	15		T3	145		T9	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	807	1			T48	1		T37	9		T136	14
values[1]	624	1			T4	1		T5	1		T7	4
values[2]	715	1			T2	1		T41	1		T46	26
values[3]	3199	1			T8	24		T10	10		T13	1
values[4]	716	1			T11	29		T12	6		T55	1
values[5]	664	1			T41	1		T87	3		T91	8
values[6]	612	1			T5	1		T45	9		T145	1
values[7]	822	1			T4	1		T84	23		T87	11
values[8]	1036	1			T5	1		T84	12		T89	10
values[9]	164	1			T52	10		T138	12		T214	16
minimum	18948	1			T1	15		T3	145		T6	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

4406

1

T6

9

T8

22

T10

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T48	1		T37	6		T38	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T136	14		T140	7		T141	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	1		T138	1		T39	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T4	1		T5	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T2	1		T84	7		T15	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T41	1		T46	15		T132	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1727	1			T8	24		T10	10		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T52	17		T48	1		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T11	9		T12	2		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T52	16		T36	3		T140	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T87	1		T91	1		T136	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T41	1		T145	1		T131	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	1		T132	13		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T45	9		T145	1		T149	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T145	1		T14	6		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T4	1		T84	12		T87	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T89	3		T130	1		T141	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T5	1		T84	5		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T52	10		T138	1		T187	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T214	12		T248	5		T249	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18747	1			T1	15		T3	145		T6	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T157	1		T33	1		T247	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T37	3		T38	2		T142	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T141	11		T142	6		T214	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	3		T39	5		T190	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T130	9		T215	9		T144	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T84	8		T15	1		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T46	11		T132	10		T211	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1050	1			T36	3		T91	14		T137	33
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T138	8		T141	10		T234	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	20		T12	4		T155	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T36	3		T250	2		T237	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T87	2		T91	7		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T131	8		T132	7		T154	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T132	14		T14	9		T134	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T155	10		T209	16		T244	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	7		T209	14		T187	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T84	11		T87	10		T131	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T89	7		T130	8		T141	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T84	7		T130	10		T38	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T138	11		T187	2		T152	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T214	4		T248	15		T249	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T55	1		T37	1		T39	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T251	4		T252	14		T253	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T52	10		T89	3		T221	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T84	5		T214	12		T16	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T157	1		T247	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	10		T48	1		T37	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T140	7		T141	14		T142	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	1		T138	1		T39	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T4	1		T5	1		T136	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	1		T84	7		T15	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T41	1		T46	15		T132	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T36	4		T91	1		T131	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T52	17		T48	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1731	1			T8	24		T10	10		T11	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T52	16		T140	13		T234	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	2		T87	1		T91	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T36	3		T145	1		T131	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	1		T132	13		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T41	1		T45	9		T132	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T145	1		T14	1		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T4	1		T84	12		T87	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T130	1		T138	1		T141	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T5	1		T130	1		T38	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18691	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T89	7		T206	2		T209	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T84	7		T214	4		T16	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T37	3		T38	2		T229	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T141	11		T142	6		T214	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	3		T39	5		T190	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T130	9		T215	9		T144	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T84	8		T15	1		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T46	11		T132	10		T211	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T36	3		T91	14		T131	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T138	8		T141	10		T109	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T11	20		T137	33		T146	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T234	10		T246	4		T150	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	4		T87	2		T91	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T36	3		T131	8		T156	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T132	14		T134	10		T106	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T132	7		T154	12		T155	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	9		T209	14		T187	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T84	11		T87	10		T131	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T130	8		T138	11		T141	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T130	10		T38	9		T149	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	1		T37	1		T39	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T48	1		T37	6		T38	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T136	1		T140	1		T141	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	4		T138	1		T39	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T4	1		T5	1		T130	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T2	1		T84	9		T15	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T41	1		T46	12		T132	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1403	1			T8	2		T10	1		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T52	1		T48	1		T138	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	21		T12	5		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T52	1		T36	5		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T87	3		T91	8		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T41	1		T145	1		T131	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	1		T132	15		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T45	1		T145	1		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T145	1		T14	12		T209	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T4	1		T84	12		T87	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T89	8		T130	9		T141	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T5	1		T84	8		T130	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T52	1		T138	12		T187	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T214	5		T248	19		T249	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18867	1			T1	15		T3	145		T6	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T157	1		T33	1		T247	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T37	3		T38	2		T142	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T136	13		T140	6		T141	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T39	3		T190	7		T134	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T140	10		T143	6		T254	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T84	6		T15	1		T244	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T46	14		T132	11		T255	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T8	22		T10	9		T53	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T52	16		T141	10		T234	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	8		T12	1		T206	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T52	15		T36	1		T140	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T136	14		T188	11		T215	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T131	8		T132	8		T154	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T132	12		T134	10		T208	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T45	8		T149	11		T244	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	1		T187	18		T17	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T84	11		T131	14		T26	26
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T89	2		T141	5		T208	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T84	4		T38	1		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T52	9		T187	4		T35	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T214	11		T248	1		T249	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T6	9		T188	9		T215	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T256	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T52	1		T89	8		T221	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T84	8		T214	5		T16	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T157	1		T247	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	1		T48	1		T37	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T140	1		T141	12		T142	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T7	4		T138	1		T39	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T4	1		T5	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	1		T84	9		T15	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T41	1		T46	12		T132	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T36	6		T91	15		T131	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T52	1		T48	1		T138	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T8	2		T10	1		T11	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T52	1		T140	1		T234	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	5		T87	3		T91	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T36	5		T145	1		T131	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	1		T132	15		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T41	1		T45	1		T132	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T145	1		T14	10		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T4	1		T84	12		T87	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T130	9		T138	12		T141	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T5	1		T130	11		T38	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18825	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T52	9		T89	2		T206	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T84	4		T214	11		T16	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T6	9		T37	3		T38	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T140	6		T141	13		T142	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T39	3		T190	7		T142	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T136	13		T140	10		T143	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T84	6		T15	1		T244	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T46	14		T132	11		T255	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T36	1		T131	7		T208	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T52	16		T141	10		T243	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T8	22		T10	9		T11	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T52	15		T140	12		T234	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	1		T136	14		T188	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T36	1		T131	8		T250	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T132	12		T134	10		T208	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T45	8		T132	8		T154	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T143	17		T187	18		T223	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T84	11		T131	14		T26	26
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T141	5		T14	1		T208	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T38	1		T40	1		T206	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

auto[0]

4406

1

T6

9

T8

22

T10

9