Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28307

1

T1

15

T2

1

T3

145

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24595

1

T1

15

T2

1

T3

145

auto[ADC_CTRL_FILTER_COND_OUT]

3712

1

T4

2

T5

1

T6

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21476

1

T1

15

T3

143

T4

2

auto[1]

6831

1

T2

1

T3

2

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24199

1

T1

15

T2

1

T3

145

auto[1]

4108

1

T7

3

T11

20

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	583	1			T3	2		T11	1		T57	1
values[0]	62	1			T130	11		T155	9		T257	1
values[1]	724	1			T52	33		T131	20		T141	21
values[2]	2946	1			T4	1		T6	10		T8	24
values[3]	747	1			T4	1		T12	6		T36	7
values[4]	733	1			T37	9		T132	49		T206	27
values[5]	649	1			T2	1		T5	1		T145	1
values[6]	757	1			T55	1		T36	6		T89	10
values[7]	638	1			T48	1		T145	2		T140	13
values[8]	700	1			T7	4		T11	29		T38	5
values[9]	1490	1			T5	2		T52	10		T41	2
minimum	18278	1			T1	15		T3	143		T9	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	833	1			T4	1		T6	10		T52	33
values[1]	2902	1			T8	24		T10	10		T13	1
values[2]	852	1			T12	6		T36	7		T84	12
values[3]	781	1			T2	1		T4	1		T5	1
values[4]	644	1			T145	1		T132	16		T142	16
values[5]	722	1			T55	1		T36	6		T89	10
values[6]	638	1			T48	1		T145	1		T139	1
values[7]	827	1			T7	4		T11	29		T41	2
values[8]	947	1			T5	1		T45	9		T84	15
values[9]	312	1			T5	1		T52	10		T87	3
minimum	18849	1			T1	15		T3	145		T9	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

4406

1

T6

9

T8

22

T10

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T52	33		T131	8		T141	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T4	1		T6	10		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1688	1			T8	24		T10	10		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T140	7		T14	6		T26	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	2		T36	4		T91	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T84	5		T131	15		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	1		T132	13		T141	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T4	1		T5	1		T87	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T145	1		T142	10		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T132	9		T234	10		T211	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T36	3		T89	3		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T55	1		T154	7		T208	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T155	1		T190	8		T210	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T48	1		T145	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	1		T11	9		T41	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T48	1		T145	1		T38	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T5	1		T84	7		T136	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T45	9		T91	1		T130	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T5	1		T156	1		T50	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T52	10		T87	1		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18703	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T245	11		T258	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T131	12		T141	10		T155	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T130	10		T187	7		T211	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1013	1			T46	11		T84	11		T137	33
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T14	7		T26	12		T40	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	4		T36	3		T91	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T84	7		T131	18		T188	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T132	14		T141	11		T206	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T87	10		T37	3		T132	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T142	6		T156	12		T107	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T132	7		T234	10		T211	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T36	3		T89	7		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T154	12		T16	11		T254	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T155	10		T190	7		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T15	1		T229	4		T224	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	3		T11	20		T141	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T38	2		T131	8		T26	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T84	8		T39	5		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T91	14		T130	17		T38	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T156	9		T50	7		T259	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T87	2		T243	7		T219	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	1		T37	1		T39	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	560	1			T3	2		T11	1		T57	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T155	1		T257	1		T260	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T130	1		T245	11		T261	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T52	33		T131	8		T141	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T139	1		T187	19		T211	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1687	1			T8	24		T10	10		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T4	1		T6	10		T131	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	2		T36	4		T91	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	1		T84	5		T87	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T132	13		T225	13		T17	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T37	6		T132	12		T206	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T2	1		T145	1		T141	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	1		T132	9		T211	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T36	3		T89	3		T38	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T55	1		T234	10		T208	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T140	13		T149	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T48	1		T145	2		T154	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	1		T11	9		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T38	3		T131	9		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	364	1			T5	2		T41	2		T84	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	469	1			T52	10		T45	9		T48	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18144	1			T1	15		T3	143		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T96	11		T262	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T155	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T130	10		T263	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T131	12		T141	10		T214	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T187	7		T211	2		T230	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T46	11		T84	11		T137	33
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T131	18		T26	12		T40	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	4		T36	3		T91	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T84	7		T87	10		T14	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T132	14		T17	20		T237	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T37	3		T132	10		T206	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T141	11		T156	12		T107	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T132	7		T211	2		T230	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T36	3		T89	7		T38	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T234	10		T16	11		T216	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T149	1		T155	10		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T154	12		T229	4		T224	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T7	3		T11	20		T141	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T38	2		T131	8		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T84	8		T39	5		T142	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	380	1			T87	2		T91	14		T130	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	1		T37	1		T39	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T52	2		T131	13		T141	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T4	1		T6	1		T130	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T8	2		T10	1		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T140	1		T14	12		T26	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T12	5		T36	6		T91	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T84	8		T131	19		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	1		T132	15		T141	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T4	1		T5	1		T87	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T145	1		T142	7		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T132	8		T234	11		T211	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T36	5		T89	8		T38	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T55	1		T154	13		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T155	11		T190	8		T210	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T48	1		T145	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	4		T11	21		T41	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T48	1		T145	1		T38	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T5	1		T84	9		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T45	1		T91	15		T130	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T5	1		T156	10		T50	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T52	1		T87	3		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18826	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T245	1		T258	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T52	31		T131	7		T141	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	9		T187	18		T230	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T8	22		T10	9		T53	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T140	6		T14	1		T26	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	1		T36	1		T136	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T84	4		T131	14		T208	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T132	12		T141	13		T206	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T37	3		T132	11		T206	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T142	9		T264	6		T265	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T132	8		T234	9		T230	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T36	1		T89	2		T140	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T154	6		T208	11		T206	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T190	7		T208	10		T106	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T15	1		T229	3		T224	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T11	8		T140	12		T141	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T38	2		T131	8		T26	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T84	6		T136	14		T39	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T45	8		T38	1		T134	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T50	6		T223	4		T259	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T52	9		T243	13		T165	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T266	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T245	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	572	1			T3	2		T11	1		T57	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T155	9		T257	1		T260	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T130	11		T245	1		T261	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T52	2		T131	13		T141	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T139	1		T187	8		T211	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1334	1			T8	2		T10	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T4	1		T6	1		T131	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T12	5		T36	6		T91	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T4	1		T84	8		T87	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T132	15		T225	1		T17	25
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T37	6		T132	11		T206	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T2	1		T145	1		T141	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	1		T132	8		T211	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T36	5		T89	8		T38	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T55	1		T234	11		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T140	1		T149	2		T155	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T48	1		T145	2		T154	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	4		T11	21		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T38	3		T131	9		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T5	2		T41	2		T84	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	469	1			T52	1		T45	1		T48	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18278	1			T1	15		T3	143		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T262	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T245	10		T261	14		T263	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T52	31		T131	7		T141	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T187	18		T230	2		T246	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T8	22		T10	9		T53	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T6	9		T131	14		T26	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	1		T36	1		T136	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T84	4		T140	6		T14	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T132	12		T225	12		T17	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T37	3		T132	11		T206	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T141	13		T230	3		T264	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T132	8		T230	10		T164	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T36	1		T89	2		T140	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T234	9		T208	11		T16	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T140	12		T208	10		T267	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T154	6		T206	6		T229	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	8		T141	5		T106	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T38	2		T131	8		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T84	6		T136	14		T39	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	380	1			T52	9		T45	8		T38	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

auto[0]

4406

1

T6

9

T8

22

T10

9