Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28307

1

T1

15

T2

1

T3

145

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24706

1

T1

15

T3

145

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3601

1

T2

1

T4

1

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21865

1

T1

15

T2

1

T3

145

auto[1]

6442

1

T5

3

T8

24

T10

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24199

1

T1

15

T2

1

T3

145

auto[1]

4108

1

T7

3

T11

20

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	275	1			T4	1		T5	1		T130	11
values[0]	15	1			T255	1		T268	14		-	-
values[1]	824	1			T36	6		T45	9		T84	12
values[2]	660	1			T55	1		T87	3		T141	21
values[3]	747	1			T52	27		T41	1		T145	1
values[4]	691	1			T36	7		T41	1		T38	12
values[5]	396	1			T4	1		T5	1		T52	16
values[6]	698	1			T5	1		T131	17		T221	1
values[7]	903	1			T136	14		T38	4		T155	11
values[8]	711	1			T11	29		T12	6		T130	9
values[9]	3562	1			T2	1		T6	10		T7	4
minimum	18825	1			T1	15		T3	145		T9	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	827	1			T55	1		T36	6		T45	9
values[1]	637	1			T41	1		T87	3		T136	15
values[2]	754	1			T52	27		T41	1		T145	1
values[3]	630	1			T36	7		T48	1		T145	1
values[4]	477	1			T4	1		T5	1		T52	16
values[5]	779	1			T5	1		T136	14		T38	4
values[6]	3290	1			T8	24		T10	10		T13	1
values[7]	757	1			T11	29		T12	6		T39	13
values[8]	999	1			T2	1		T5	1		T6	10
values[9]	157	1			T4	1		T84	15		T91	8
minimum	19000	1			T1	15		T3	145		T9	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

4406

1

T6

9

T8

22

T10

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T55	1		T36	3		T45	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T149	12		T234	10		T231	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T87	1		T136	15		T140	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T41	1		T149	1		T15	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T52	17		T41	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T52	10		T140	7		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T48	1		T38	3		T231	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T36	4		T145	1		T14	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T4	1		T5	1		T52	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T221	1		T187	19		T237	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T136	14		T38	2		T131	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	1		T206	13		T209	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1841	1			T8	24		T10	10		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T188	10		T16	4		T156	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	2		T39	8		T132	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T11	9		T141	6		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T6	10		T130	1		T38	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T2	1		T5	1		T7	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T91	1		T243	14		T254	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T4	1		T84	7		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18729	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T14	1		T40	4		T17	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T36	3		T84	7		T91	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T234	10		T40	1		T269	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T87	2		T141	10		T142	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T149	1		T215	12		T109	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T130	9		T229	4		T16	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T202	9		T209	1		T230	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T38	9		T207	13		T270	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T36	3		T14	7		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T230	6		T219	18		T267	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T187	7		T237	10		T248	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T38	2		T131	8		T134	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T206	14		T209	14		T215	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T137	33		T146	23		T271	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T16	1		T156	21		T164	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T12	4		T39	5		T132	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	20		T141	5		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T130	8		T38	2		T138	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	3		T46	11		T84	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T91	7		T243	7		T254	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T84	8		T138	11		T249	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T55	1		T87	10		T37	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T14	9		T40	3		T17	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T38	3		T272	1		T51	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T4	1		T5	1		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T255	1		T268	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T36	3		T45	9		T84	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T14	1		T234	10		T231	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T55	1		T87	1		T141	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T149	13		T15	5		T208	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T52	17		T145	1		T136	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T52	10		T41	1		T140	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T41	1		T38	3		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T36	4		T15	3		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T4	1		T5	1		T52	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T145	1		T14	6		T187	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T131	9		T134	5		T210	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T5	1		T221	1		T215	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T136	14		T38	2		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T206	13		T209	1		T16	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	2		T130	1		T39	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T11	9		T141	6		T142	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1884	1			T6	10		T8	24		T10	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T2	1		T7	1		T46	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18691	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T38	2		T273	1		T254	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T130	10		T246	4		T20	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T268	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T36	3		T84	7		T87	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	9		T234	10		T40	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T87	2		T141	10		T142	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T149	1		T215	12		T156	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T130	9		T229	4		T16	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T202	9		T209	1		T224	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T38	9		T207	13		T264	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T36	3		T15	1		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T230	6		T274	9		T179	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T14	7		T187	7		T237	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T131	8		T134	10		T211	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T215	9		T259	10		T275	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T38	2		T155	10		T26	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T206	14		T209	14		T156	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T12	4		T130	8		T39	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	20		T141	5		T142	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1157	1			T91	7		T137	33		T138	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T7	3		T46	11		T84	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	1		T37	1		T39	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T55	1		T36	5		T45	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T149	1		T234	11		T231	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T87	3		T136	1		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T41	1		T149	2		T15	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T52	1		T41	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T52	1		T140	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T48	1		T38	11		T231	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T36	6		T145	1		T14	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T4	1		T5	1		T52	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T221	1		T187	8		T237	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T136	1		T38	4		T131	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	1		T206	15		T209	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1402	1			T8	2		T10	1		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T188	1		T16	4		T156	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	5		T39	10		T132	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T11	21		T141	6		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T6	1		T130	9		T38	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T2	1		T5	1		T7	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T91	8		T243	8		T254	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T4	1		T84	9		T138	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18867	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T14	10		T40	5		T17	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T36	1		T45	8		T84	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T149	11		T234	9		T40	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T136	14		T140	10		T141	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T15	1		T208	10		T229	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T52	16		T229	3		T16	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T52	9		T140	6		T230	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T38	1		T245	10		T274	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T36	1		T14	1		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T52	15		T208	11		T230	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T187	18		T237	7		T248	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T136	13		T131	8		T134	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T206	12		T224	10		T223	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1480	1			T8	22		T10	9		T53	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T188	9		T16	1		T164	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	1		T39	3		T132	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T11	8		T141	5		T142	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T6	9		T38	2		T140	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T46	14		T84	11		T89	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T243	13		T254	4		T276	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T84	6		T255	13		T249	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T26	11		T164	4		T232	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T40	2		T17	2		T268	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T38	3		T272	1		T51	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T4	1		T5	1		T130	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T255	1		T268	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T36	5		T45	1		T84	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T14	10		T234	11		T231	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T55	1		T87	3		T141	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T149	3		T15	4		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T52	1		T145	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T52	1		T41	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T41	1		T38	11		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T36	6		T15	3		T40	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T4	1		T5	1		T52	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T145	1		T14	12		T187	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T131	9		T134	11		T210	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	1		T221	1		T215	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T136	1		T38	4		T155	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T206	15		T209	15		T16	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	5		T130	9		T39	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T11	21		T141	6		T142	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1527	1			T6	1		T8	2		T10	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T2	1		T7	4		T46	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18825	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T38	2		T254	4		T276	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T246	12		T255	13		T20	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T268	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T36	1		T45	8		T84	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T234	9		T40	3		T17	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T141	10		T142	9		T214	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T149	11		T15	1		T208	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T52	16		T136	14		T140	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T52	9		T140	6		T229	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T38	1		T264	6		T245	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T36	1		T15	1		T225	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T52	15		T230	2		T215	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T14	1		T187	18		T237	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T131	8		T134	4		T208	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T223	9		T259	7		T275	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T136	13		T26	15		T134	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T206	12		T224	10		T164	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T12	1		T39	3		T132	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	8		T141	5		T142	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1514	1			T6	9		T8	22		T10	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T46	14		T84	17		T89	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

auto[0]

4406

1

T6

9

T8

22

T10

9