Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28307

1

T1

15

T2

1

T3

145

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24762

1

T1

15

T2

1

T3

145

auto[ADC_CTRL_FILTER_COND_OUT]

3545

1

T4

1

T5

3

T12

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21830

1

T1

15

T3

145

T4

1

auto[1]

6477

1

T2

1

T4

1

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24199

1

T1

15

T2

1

T3

145

auto[1]

4108

1

T7

3

T11

20

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	217	1			T5	1		T6	10		T154	19
values[0]	29	1			T204	15		T171	14		-	-
values[1]	788	1			T2	1		T4	1		T11	29
values[2]	3001	1			T7	4		T8	24		T10	10
values[3]	626	1			T45	9		T91	8		T38	4
values[4]	613	1			T55	1		T36	6		T41	1
values[5]	687	1			T52	17		T84	15		T87	3
values[6]	733	1			T5	1		T91	15		T130	21
values[7]	918	1			T41	1		T84	23		T37	9
values[8]	837	1			T48	2		T89	10		T136	14
values[9]	1033	1			T4	1		T5	1		T12	6
minimum	18825	1			T1	15		T3	145		T9	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	616	1			T2	1		T11	29		T131	53
values[1]	3147	1			T7	4		T8	24		T10	10
values[2]	531	1			T55	1		T36	6		T41	1
values[3]	647	1			T140	7		T39	13		T141	21
values[4]	738	1			T5	1		T52	17		T84	15
values[5]	690	1			T37	9		T130	21		T140	11
values[6]	973	1			T41	1		T48	1		T84	23
values[7]	721	1			T52	16		T48	1		T89	10
values[8]	951	1			T4	1		T5	2		T6	10
values[9]	170	1			T142	32		T206	27		T163	1
minimum	19123	1			T1	15		T3	145		T4	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

4406

1

T6

9

T8

22

T10

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T2	1		T11	9		T132	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T131	23		T207	1		T188	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1762	1			T7	1		T8	24		T10	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T145	1		T140	13		T257	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T55	1		T36	3		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T45	9		T87	1		T91	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T140	7		T141	11		T24	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T39	8		T149	1		T26	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T52	17		T84	7		T87	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T5	1		T214	12		T209	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T130	2		T14	1		T134	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T37	6		T140	11		T132	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T48	1		T84	12		T141	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T41	1		T24	1		T210	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T89	3		T130	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T52	16		T48	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T4	1		T6	10		T52	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T5	2		T12	2		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T142	18		T163	1		T211	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T206	13		T277	5		T212	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18788	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T4	1		T108	13		T223	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T11	20		T132	14		T206	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T131	30		T207	13		T16	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1037	1			T7	3		T137	33		T146	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T50	7		T109	13		T278	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T36	3		T142	6		T134	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T87	10		T91	7		T38	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T141	10		T40	1		T187	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T39	5		T149	1		T26	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T84	8		T87	2		T91	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T214	4		T209	14		T215	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T130	19		T14	9		T134	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T37	3		T132	10		T155	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T84	11		T141	11		T155	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T216	8		T279	12		T248	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T89	7		T130	8		T138	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T40	3		T16	1		T219	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T36	3		T84	7		T141	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	4		T38	11		T188	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T142	14		T211	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T206	14		T277	8		T212	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T55	1		T46	11		T37	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T18	1		T160	14		T268	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T6	10		T154	7		T142	18
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T5	1		T144	1		T277	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T204	15		T171	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T2	1		T11	9		T46	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T4	1		T131	23		T207	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1709	1			T7	1		T8	24		T10	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T87	1		T145	1		T140	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T221	1		T142	10		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T45	9		T91	1		T38	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T55	1		T36	3		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T138	1		T39	8		T15	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T52	17		T84	7		T87	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T149	1		T26	12		T214	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T91	1		T130	2		T190	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	1		T140	11		T132	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T84	12		T141	14		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T41	1		T37	6		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T48	1		T89	3		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T48	1		T136	14		T143	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T4	1		T52	10		T36	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T5	1		T12	2		T52	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18691	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T154	12		T142	14		T107	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T144	13		T277	8		T212	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T171	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	20		T46	11		T132	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T131	30		T207	13		T16	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T7	3		T137	33		T146	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T87	10		T109	13		T278	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T142	6		T202	9		T164	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T91	7		T38	2		T14	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T36	3		T141	10		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T138	11		T39	5		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T84	8		T87	2		T132	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T149	1		T26	12		T214	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T91	14		T130	19		T190	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T132	10		T155	8		T215	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T84	11		T141	11		T155	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T37	3		T40	1		T211	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T89	7		T130	8		T138	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T16	1		T219	18		T212	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T36	3		T84	7		T131	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	4		T38	11		T40	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	1		T37	1		T39	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	1		T11	21		T132	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T131	32		T207	14		T188	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T7	4		T8	2		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T145	1		T140	1		T257	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T55	1		T36	5		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T45	1		T87	11		T91	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T140	1		T141	11		T24	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T39	10		T149	2		T26	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T52	1		T84	9		T87	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	1		T214	5		T209	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T130	21		T14	10		T134	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T37	6		T140	1		T132	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T48	1		T84	12		T141	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T41	1		T24	1		T210	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T89	8		T130	9		T138	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T52	1		T48	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T4	1		T6	1		T52	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T5	2		T12	5		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T142	15		T163	1		T211	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T206	15		T277	9		T212	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18886	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T4	1		T108	1		T223	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	8		T132	12		T208	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T131	21		T188	9		T16	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1415	1			T8	22		T10	9		T53	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T140	12		T50	6		T223	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T36	1		T142	9		T134	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T45	8		T14	1		T15	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T140	6		T141	10		T208	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T39	3		T26	11		T208	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T52	16		T84	6		T132	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T214	11		T215	10		T50	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T134	10		T225	9		T188	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T37	3		T140	10		T132	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T84	11		T141	13		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T215	8		T216	8		T248	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T89	2		T131	8		T230	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T52	15		T136	13		T40	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	9		T52	9		T36	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	1		T38	3		T143	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T142	17		T226	13		T165	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T206	12		T277	4		T212	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T46	14		T229	8		T280	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T108	12		T223	9		T160	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T6	1		T154	13		T142	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T5	1		T144	14		T277	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T204	1		T171	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T2	1		T11	21		T46	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	1		T131	32		T207	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T7	4		T8	2		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T87	11		T145	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T221	1		T142	7		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T45	1		T91	8		T38	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T55	1		T36	5		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T138	12		T39	10		T15	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T52	1		T84	9		T87	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T149	2		T26	13		T214	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T91	15		T130	21		T190	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	1		T140	1		T132	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T84	12		T141	12		T155	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T41	1		T37	6		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T48	1		T89	8		T130	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T48	1		T136	1		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T4	1		T52	1		T36	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T5	1		T12	5		T52	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18825	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T6	9		T154	6		T142	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T277	4		T212	6		T281	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T204	14		T171	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T11	8		T46	14		T132	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T131	21		T188	9		T16	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T8	22		T10	9		T53	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T140	12		T282	10		T222	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T142	9		T225	12		T164	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T45	8		T14	1		T228	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T36	1		T141	10		T208	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T39	3		T15	2		T208	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T52	16		T84	6		T140	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T26	11		T214	11		T223	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T190	7		T225	9		T188	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T140	10		T132	11		T215	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T84	11		T141	13		T26	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T37	3		T40	1		T215	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T89	2		T149	11		T229	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T136	13		T143	6		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T52	9		T36	1		T84	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T12	1		T52	15		T38	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

auto[0]

4406

1

T6

9

T8

22

T10

9