Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28307

1

T1

15

T2

1

T3

145

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24756

1

T1

15

T2

1

T3

145

auto[ADC_CTRL_FILTER_COND_OUT]

3551

1

T4

1

T5

1

T6

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21860

1

T1

15

T3

145

T4

1

auto[1]

6447

1

T2

1

T4

1

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24199

1

T1

15

T2

1

T3

145

auto[1]

4108

1

T7

3

T11

20

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	26	1			T133	1		T283	25		-	-
values[0]	102	1			T130	19		T243	21		T165	7
values[1]	849	1			T7	4		T145	1		T131	20
values[2]	824	1			T12	6		T52	10		T36	7
values[3]	649	1			T4	1		T45	9		T48	1
values[4]	756	1			T41	1		T89	10		T37	9
values[5]	745	1			T11	29		T140	7		T221	1
values[6]	705	1			T2	1		T36	6		T84	15
values[7]	743	1			T5	1		T55	1		T52	33
values[8]	3208	1			T4	1		T5	1		T8	24
values[9]	875	1			T5	1		T6	10		T91	8
minimum	18825	1			T1	15		T3	145		T9	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1075	1			T7	4		T145	1		T130	19
values[1]	696	1			T4	1		T12	6		T52	10
values[2]	802	1			T45	9		T48	1		T87	11
values[3]	703	1			T41	1		T89	10		T37	9
values[4]	742	1			T11	29		T36	6		T140	7
values[5]	796	1			T2	1		T55	1		T52	33
values[6]	3207	1			T5	1		T8	24		T10	10
values[7]	622	1			T4	1		T5	1		T6	10
values[8]	569	1			T145	1		T138	9		T133	1
values[9]	225	1			T5	1		T134	21		T40	3
minimum	18870	1			T1	15		T3	145		T9	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

4406

1

T6

9

T8

22

T10

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T7	1		T145	1		T131	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T130	2		T138	1		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T4	1		T12	2		T52	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T91	1		T130	1		T132	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T48	1		T131	9		T208	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T45	9		T87	1		T26	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T89	3		T37	6		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T41	1		T131	15		T132	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T36	3		T140	7		T154	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T11	9		T14	6		T234	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T2	1		T55	1		T52	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T52	17		T48	1		T140	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1729	1			T8	24		T10	10		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T5	1		T41	1		T84	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	1		T84	12		T91	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	1		T6	10		T46	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T145	1		T133	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T138	1		T231	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T5	1		T224	11		T107	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T134	11		T40	2		T163	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18696	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T142	18		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	3		T131	12		T39	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T130	17		T138	11		T14	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	4		T36	3		T26	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T91	14		T130	10		T132	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T131	8		T214	4		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T87	10		T26	12		T214	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T89	7		T37	3		T141	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T131	18		T132	14		T229	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T36	3		T154	12		T206	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	20		T14	7		T234	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T84	8		T38	2		T132	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T40	1		T107	15		T284	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1024	1			T137	33		T38	2		T146	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T84	7		T87	2		T141	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T84	11		T91	7		T38	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T46	11		T141	10		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T230	6		T264	7		T278	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T138	8		T188	12		T216	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T224	13		T107	10		T212	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T134	10		T40	1		T164	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T55	1		T37	1		T39	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T142	14		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T133	1		T283	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T165	7		T285	6		T286	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T130	2		T243	14		T151	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	1		T145	1		T131	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T132	12		T14	1		T142	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T12	2		T52	10		T36	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T91	1		T130	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T4	1		T48	1		T131	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T45	9		T87	1		T26	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T89	3		T37	6		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T41	1		T131	15		T132	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T140	7		T221	1		T206	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T11	9		T24	1		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T2	1		T36	3		T84	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T140	11		T162	1		T14	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T55	1		T52	16		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	1		T52	17		T41	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1745	1			T5	1		T8	24		T10	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	1		T46	15		T141	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T5	1		T91	1		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T6	10		T138	1		T134	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18691	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T283	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T286	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T130	17		T243	7		T151	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	3		T131	12		T39	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T132	10		T14	9		T142	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	4		T36	3		T190	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T91	14		T130	10		T138	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T131	8		T156	9		T106	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T87	10		T26	12		T214	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T89	7		T37	3		T141	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T131	18		T132	14		T156	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T206	14		T16	11		T215	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	20		T229	4		T254	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T36	3		T84	8		T38	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T14	7		T234	10		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T38	2		T40	3		T207	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T84	7		T87	2		T141	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T84	11		T137	33		T38	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T46	11		T141	10		T202	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T91	7		T230	6		T224	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T138	8		T134	10		T40	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	1		T37	1		T39	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T7	4		T145	1		T131	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	381	1			T130	19		T138	12		T14	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	1		T12	5		T52	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T91	15		T130	11		T132	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T48	1		T131	9		T208	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T45	1		T87	11		T26	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T89	8		T37	6		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T41	1		T131	19		T132	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T36	5		T140	1		T154	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T11	21		T14	12		T234	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T2	1		T55	1		T52	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T52	1		T48	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T8	2		T10	1		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T5	1		T41	1		T84	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T5	1		T84	12		T91	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T4	1		T6	1		T46	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T145	1		T133	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T138	9		T231	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T5	1		T224	14		T107	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T134	11		T40	2		T163	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18834	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T142	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T131	7		T39	3		T149	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T229	8		T50	6		T236	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	1		T52	9		T36	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T132	11		T134	4		T188	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T131	8		T208	11		T214	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T45	8		T26	11		T214	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T89	2		T37	3		T136	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T131	14		T132	12		T229	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T36	1		T140	6		T154	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	8		T14	1		T234	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T52	15		T84	6		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T52	16		T140	10		T143	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T8	22		T10	9		T53	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T84	4		T136	13		T141	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T84	11		T38	1		T214	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T6	9		T46	14		T141	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T225	12		T230	2		T264	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T188	20		T215	8		T280	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T224	10		T212	6		T20	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T134	10		T40	1		T164	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T277	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T142	17		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T133	1		T283	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T165	1		T285	1		T286	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T130	19		T243	8		T151	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	4		T145	1		T131	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T132	11		T14	10		T142	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T12	5		T52	1		T36	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T91	15		T130	11		T138	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T4	1		T48	1		T131	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T45	1		T87	11		T26	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T89	8		T37	6		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T41	1		T131	19		T132	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T140	1		T221	1		T206	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	21		T24	1		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T2	1		T36	5		T84	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T140	1		T162	1		T14	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T55	1		T52	1		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	1		T52	1		T41	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1412	1			T5	1		T8	2		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T4	1		T46	12		T141	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T5	1		T91	8		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	1		T138	9		T134	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18825	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T283	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T165	6		T285	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T243	13		T151	4		T248	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T131	7		T39	3		T149	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T132	11		T142	17		T50	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T52	9		T36	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T134	4		T229	8		T224	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T131	8		T208	11		T106	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T45	8		T26	11		T214	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T89	2		T37	3		T136	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T131	14		T132	12		T165	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T140	6		T206	12		T143	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T11	8		T229	3		T254	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T36	1		T84	6		T132	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T140	10		T14	1		T234	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T52	15		T38	2		T140	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T52	16		T84	4		T136	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T8	22		T10	9		T53	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T46	14		T141	10		T208	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T225	12		T230	2		T224	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T6	9		T134	10		T40	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

auto[0]

4406

1

T6

9

T8

22

T10

9