Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28307

1

T1

15

T2

1

T3

145

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24529

1

T1

15

T3

145

T5

1

auto[ADC_CTRL_FILTER_COND_OUT]

3778

1

T2

1

T4

2

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22307

1

T1

15

T2

1

T3

145

auto[1]

6000

1

T5

1

T6

10

T8

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24199

1

T1

15

T2

1

T3

145

auto[1]

4108

1

T7

3

T11

20

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	77	1			T259	18		T261	4		T100	22
values[0]	35	1			T157	1		T287	12		T247	1
values[1]	640	1			T6	10		T48	1		T142	16
values[2]	723	1			T4	1		T7	4		T37	9
values[3]	794	1			T2	1		T5	1		T41	1
values[4]	613	1			T52	17		T36	7		T48	1
values[5]	3107	1			T8	24		T10	10		T11	29
values[6]	835	1			T12	6		T52	16		T36	6
values[7]	586	1			T5	1		T41	1		T45	9
values[8]	794	1			T4	1		T84	23		T87	11
values[9]	1278	1			T5	1		T52	10		T84	12
minimum	18825	1			T1	15		T3	145		T9	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	941	1			T6	10		T48	1		T37	9
values[1]	617	1			T4	1		T5	1		T7	4
values[2]	654	1			T2	1		T41	1		T46	26
values[3]	3237	1			T8	24		T10	10		T13	1
values[4]	722	1			T11	29		T12	6		T52	16
values[5]	691	1			T41	1		T87	3		T91	8
values[6]	552	1			T5	1		T45	9		T145	1
values[7]	819	1			T4	1		T84	23		T87	11
values[8]	947	1			T5	1		T84	12		T89	10
values[9]	281	1			T52	10		T221	1		T214	16
minimum	18846	1			T1	15		T3	145		T9	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

4406

1

T6

9

T8

22

T10

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T6	10		T48	1		T37	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T136	14		T140	7		T142	28
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	1		T190	8		T143	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	1		T5	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T41	1		T84	7		T15	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T2	1		T46	15		T132	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1775	1			T8	24		T10	10		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T48	1		T138	1		T141	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	2		T155	1		T206	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T11	9		T52	16		T36	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T87	1		T91	1		T136	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T41	1		T145	1		T131	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	1		T132	13		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T45	9		T145	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T14	6		T26	12		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T4	1		T84	12		T87	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T89	3		T130	1		T141	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T5	1		T84	5		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T52	10		T221	1		T187	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T214	12		T188	13		T248	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18699	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T223	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T37	3		T38	2		T141	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T142	20		T214	13		T229	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	3		T190	7		T235	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T130	9		T39	5		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T84	8		T15	1		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T46	11		T132	10		T211	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1064	1			T36	3		T91	14		T137	33
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T138	8		T141	10		T234	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T12	4		T155	8		T206	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T11	20		T36	3		T250	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T87	2		T91	7		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T131	8		T132	7		T154	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T132	14		T14	9		T134	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T209	16		T244	13		T217	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T14	7		T26	12		T209	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T84	11		T87	10		T131	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T89	7		T130	8		T141	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T84	7		T130	10		T38	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T187	2		T16	11		T249	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T214	4		T188	14		T248	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T55	1		T37	1		T39	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T261	4		T100	12		T288	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T259	8		T289	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T287	12		T247	1		T290	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T157	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	10		T48	1		T15	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T142	10		T147	1		T214	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	1		T37	6		T38	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T4	1		T136	14		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T41	1		T84	7		T15	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T2	1		T5	1		T46	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T52	17		T36	4		T91	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T48	1		T138	1		T141	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1720	1			T8	24		T10	10		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	9		T234	10		T228	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	2		T87	1		T91	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T52	16		T36	3		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	1		T38	2		T132	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T41	1		T45	9		T132	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T14	1		T24	1		T26	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T4	1		T84	12		T87	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	383	1			T52	10		T89	3		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T5	1		T84	5		T130	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18691	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T100	10		T288	16		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T259	10		T289	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T290	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T156	11		T284	5		T250	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T142	6		T214	13		T229	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	3		T37	3		T38	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T130	9		T39	5		T142	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T84	8		T15	1		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T46	11		T132	10		T211	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T36	3		T91	14		T164	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T138	8		T141	10		T109	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T137	33		T146	23		T131	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	20		T234	10		T246	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T12	4		T87	2		T91	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T36	3		T131	8		T156	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T38	2		T132	14		T134	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T132	7		T154	12		T155	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	9		T26	12		T209	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T84	11		T87	10		T131	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T89	7		T130	8		T141	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T84	7		T130	10		T38	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	1		T37	1		T39	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T6	1		T48	1		T37	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T136	1		T140	1		T142	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	4		T190	8		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T4	1		T5	1		T130	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T41	1		T84	9		T15	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	1		T46	12		T132	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1423	1			T8	2		T10	1		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T48	1		T138	9		T141	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T12	5		T155	9		T206	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T11	21		T52	1		T36	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T87	3		T91	8		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T41	1		T145	1		T131	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	1		T132	15		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T45	1		T145	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T14	12		T26	13		T209	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T4	1		T84	12		T87	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T89	8		T130	9		T141	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T5	1		T84	8		T130	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T52	1		T221	1		T187	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T214	5		T188	15		T248	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18834	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T223	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T6	9		T37	3		T38	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T136	13		T140	6		T142	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T190	7		T143	6		T235	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T140	10		T39	3		T254	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T84	6		T15	1		T244	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T46	14		T132	11		T255	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1416	1			T8	22		T10	9		T52	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T141	10		T234	9		T246	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T12	1		T206	12		T50	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T11	8		T52	15		T36	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T136	14		T188	11		T215	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T131	8		T132	8		T154	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T132	12		T134	10		T208	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T45	8		T149	11		T280	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T14	1		T26	11		T187	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T84	11		T131	14		T26	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T89	2		T141	5		T208	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T84	4		T38	1		T40	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T52	9		T187	4		T16	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T214	11		T188	12		T248	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T291	7		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T223	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T261	1		T100	11		T288	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T259	11		T289	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T287	1		T247	1		T290	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T157	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	1		T48	1		T15	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T142	7		T147	1		T214	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T7	4		T37	6		T38	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	1		T136	1		T130	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T41	1		T84	9		T15	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	1		T5	1		T46	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T52	1		T36	6		T91	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T48	1		T138	9		T141	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1361	1			T8	2		T10	1		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	21		T234	11		T228	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	5		T87	3		T91	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T52	1		T36	5		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	1		T38	4		T132	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T41	1		T45	1		T132	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	10		T24	1		T26	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T4	1		T84	12		T87	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T52	1		T89	8		T130	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	435	1			T5	1		T84	8		T130	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18825	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T261	3		T100	11		T288	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T259	7		T289	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T287	11		T290	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T6	9		T15	1		T188	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T142	9		T214	11		T229	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T37	3		T38	2		T141	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T136	13		T140	16		T39	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T84	6		T15	1		T235	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T46	14		T132	11		T255	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T52	16		T36	1		T208	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T141	10		T243	13		T285	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T8	22		T10	9		T53	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	8		T234	9		T228	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	1		T136	14		T188	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T52	15		T36	1		T140	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T132	12		T134	10		T208	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T45	8		T132	8		T154	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T26	11		T143	17		T187	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T84	11		T131	14		T26	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T52	9		T89	2		T141	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T84	4		T38	1		T40	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

auto[0]

4406

1

T6

9

T8

22

T10

9