Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28307

1

T1

15

T2

1

T3

145

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24824

1

T1

15

T3

145

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3483

1

T2

1

T4

1

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21881

1

T1

15

T2

1

T3

145

auto[1]

6426

1

T5

3

T8

24

T10

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24199

1

T1

15

T2

1

T3

145

auto[1]

4108

1

T7

3

T11

20

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	30	1			T132	27		T110	1		T273	2
values[0]	42	1			T255	1		T268	14		T100	22
values[1]	796	1			T36	6		T45	9		T84	12
values[2]	664	1			T55	1		T87	3		T149	14
values[3]	757	1			T52	27		T41	1		T145	1
values[4]	696	1			T36	7		T41	1		T38	12
values[5]	385	1			T4	1		T5	1		T52	16
values[6]	723	1			T5	1		T136	14		T38	4
values[7]	888	1			T131	17		T155	11		T24	1
values[8]	655	1			T11	29		T12	6		T89	10
values[9]	3846	1			T2	1		T4	1		T5	1
minimum	18825	1			T1	15		T3	145		T9	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1011	1			T55	1		T36	6		T45	9
values[1]	532	1			T41	1		T87	3		T136	15
values[2]	829	1			T52	27		T41	1		T145	1
values[3]	621	1			T52	16		T36	7		T48	1
values[4]	435	1			T4	1		T5	1		T221	1
values[5]	838	1			T5	1		T136	14		T38	4
values[6]	3208	1			T8	24		T10	10		T13	1
values[7]	770	1			T11	29		T130	9		T39	13
values[8]	971	1			T2	1		T4	1		T6	10
values[9]	213	1			T5	1		T84	15		T91	8
minimum	18879	1			T1	15		T3	145		T9	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

4406

1

T6

9

T8

22

T10

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T55	1		T36	3		T45	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T154	7		T149	12		T234	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T87	1		T136	15		T141	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T41	1		T15	5		T208	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T52	17		T130	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T52	10		T41	1		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T52	16		T48	1		T38	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T36	4		T145	1		T15	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T4	1		T5	1		T210	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T221	1		T187	19		T237	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T136	14		T131	9		T134	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	1		T38	2		T206	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1783	1			T8	24		T10	10		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T188	10		T16	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T130	1		T39	8		T132	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T11	9		T141	6		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T6	10		T12	2		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T2	1		T4	1		T7	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T91	1		T131	15		T243	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T5	1		T84	7		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18704	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T14	1		T292	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T36	3		T84	7		T87	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T154	12		T234	10		T40	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T87	2		T141	10		T149	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T215	12		T237	8		T269	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T130	9		T229	4		T16	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T202	9		T209	1		T230	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T38	9		T14	7		T207	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T36	3		T15	1		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T230	6		T219	18		T293	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T187	7		T237	10		T248	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T131	8		T134	10		T211	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T38	2		T206	14		T209	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1020	1			T137	33		T146	23		T271	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T156	12		T164	2		T50	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T130	8		T39	5		T132	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	20		T141	5		T206	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T12	4		T37	3		T38	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	3		T46	11		T84	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T91	7		T131	18		T243	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T84	8		T138	11		T249	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T55	1		T37	1		T39	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T14	9		T292	10		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T132	13		T273	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T110	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T255	1		T268	8		T100	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T294	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T36	3		T45	9		T84	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T154	7		T14	1		T234	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T55	1		T87	1		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T149	12		T15	5		T208	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T52	17		T136	15		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T52	10		T41	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T38	3		T138	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T36	4		T41	1		T15	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T4	1		T5	1		T52	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T145	1		T225	13		T187	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T136	14		T134	5		T210	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	1		T38	2		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T131	9		T155	1		T24	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T206	13		T209	1		T16	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	2		T130	1		T39	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	9		T89	3		T141	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1980	1			T6	10		T8	24		T10	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	390	1			T2	1		T4	1		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18691	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T132	14		T273	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T268	6		T100	10		T220	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T36	3		T84	7		T87	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T154	12		T14	9		T234	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T87	2		T149	1		T142	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T215	12		T156	11		T17	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T130	9		T141	10		T207	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T209	1		T224	2		T250	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T38	9		T14	7		T264	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T36	3		T15	1		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T230	6		T179	11		T295	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T187	7		T237	10		T248	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T134	10		T211	2		T164	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T38	2		T215	9		T259	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T131	8		T155	10		T26	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T206	14		T209	14		T156	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T12	4		T130	8		T39	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	20		T89	7		T141	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1212	1			T91	7		T37	3		T137	33
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T7	3		T46	11		T84	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	1		T37	1		T39	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T55	1		T36	5		T45	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T154	13		T149	1		T234	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T87	3		T136	1		T141	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T41	1		T15	4		T208	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T52	1		T130	10		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T52	1		T41	1		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T52	1		T48	1		T38	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T36	6		T145	1		T15	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T4	1		T5	1		T210	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T221	1		T187	8		T237	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T136	1		T131	9		T134	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	1		T38	4		T206	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T8	2		T10	1		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T188	1		T16	1		T156	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T130	9		T39	10		T132	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T11	21		T141	6		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T6	1		T12	5		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	1		T4	1		T7	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T91	8		T131	19		T243	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T5	1		T84	9		T138	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18838	1			T1	15		T3	145		T9	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T14	10		T292	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T36	1		T45	8		T84	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T154	6		T149	11		T234	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T136	14		T141	10		T142	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T15	1		T208	10		T215	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T52	16		T140	10		T229	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T52	9		T140	6		T229	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T52	15		T38	1		T14	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T36	1		T15	1		T225	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T208	11		T230	2		T215	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T187	18		T237	7		T248	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T136	13		T131	8		T134	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T206	12		T224	10		T223	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1424	1			T8	22		T10	9		T53	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T188	9		T164	2		T50	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T39	3		T132	8		T26	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	8		T141	5		T206	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T6	9		T12	1		T37	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T46	14		T84	11		T89	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T131	14		T243	13		T276	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T84	6		T255	13		T249	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T132	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T292	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T132	15		T273	2		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T110	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T255	1		T268	7		T100	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T294	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T36	5		T45	1		T84	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T154	13		T14	10		T234	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T55	1		T87	3		T149	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T149	1		T15	4		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T52	1		T136	1		T130	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T52	1		T41	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T38	11		T138	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T36	6		T41	1		T15	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T4	1		T5	1		T52	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T145	1		T225	1		T187	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T136	1		T134	11		T210	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	1		T38	4		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T131	9		T155	11		T24	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T206	15		T209	15		T16	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	5		T130	9		T39	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T11	21		T89	8		T141	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1613	1			T6	1		T8	2		T10	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T2	1		T4	1		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18825	1			T1	15		T3	145		T9	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T132	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T268	7		T100	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T294	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T36	1		T45	8		T84	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T154	6		T234	9		T40	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T142	9		T214	11		T236	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T149	11		T15	1		T208	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T52	16		T136	14		T140	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T52	9		T140	6		T229	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T38	1		T14	1		T264	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T36	1		T15	1		T214	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T52	15		T230	2		T215	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T225	12		T187	18		T237	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T136	13		T134	4		T208	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T223	9		T259	7		T275	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T131	8		T26	15		T134	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T206	12		T224	10		T164	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T12	1		T39	3		T132	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	8		T89	2		T141	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1579	1			T6	9		T8	22		T10	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T46	14		T84	17		T225	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23901

1

T1

15

T2

1

T3

145

auto[1]

auto[0]

4406

1

T6

9

T8

22

T10

9