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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.78 99.07 96.67 100.00 100.00 98.83 98.33 91.59


Total test records in report: 919
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T792 /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.414513711 May 28 02:20:35 PM PDT 24 May 28 02:41:27 PM PDT 24 490872630049 ps
T793 /workspace/coverage/default/11.adc_ctrl_clock_gating.3742679848 May 28 02:21:49 PM PDT 24 May 28 02:25:08 PM PDT 24 356646824026 ps
T794 /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1687498243 May 28 02:20:37 PM PDT 24 May 28 02:23:39 PM PDT 24 357956379955 ps
T795 /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.137079307 May 28 02:26:49 PM PDT 24 May 28 02:30:41 PM PDT 24 375311796948 ps
T796 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1377940633 May 28 01:48:05 PM PDT 24 May 28 01:48:10 PM PDT 24 374683681 ps
T68 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.4082505417 May 28 01:48:01 PM PDT 24 May 28 01:48:07 PM PDT 24 356616458 ps
T797 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1491335890 May 28 01:47:52 PM PDT 24 May 28 01:47:55 PM PDT 24 396961060 ps
T69 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1627828909 May 28 01:47:38 PM PDT 24 May 28 01:47:43 PM PDT 24 512665062 ps
T112 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.25769672 May 28 01:47:56 PM PDT 24 May 28 01:47:59 PM PDT 24 428597403 ps
T113 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1777134147 May 28 01:47:49 PM PDT 24 May 28 01:47:52 PM PDT 24 1266952209 ps
T114 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1914757234 May 28 01:47:34 PM PDT 24 May 28 01:47:39 PM PDT 24 431535588 ps
T127 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2625814070 May 28 01:47:58 PM PDT 24 May 28 01:48:01 PM PDT 24 320317491 ps
T64 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1901737133 May 28 01:48:01 PM PDT 24 May 28 01:48:11 PM PDT 24 3840909054 ps
T798 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1689891436 May 28 01:48:06 PM PDT 24 May 28 01:48:12 PM PDT 24 324000026 ps
T62 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2454957832 May 28 01:47:34 PM PDT 24 May 28 01:47:41 PM PDT 24 494911951 ps
T72 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2172297144 May 28 01:48:03 PM PDT 24 May 28 01:48:10 PM PDT 24 966403530 ps
T799 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3782590642 May 28 01:48:06 PM PDT 24 May 28 01:48:13 PM PDT 24 362688842 ps
T92 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.4120870203 May 28 01:48:07 PM PDT 24 May 28 01:48:13 PM PDT 24 638828303 ps
T800 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1713943082 May 28 01:48:10 PM PDT 24 May 28 01:48:19 PM PDT 24 319113843 ps
T801 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3111036876 May 28 01:47:56 PM PDT 24 May 28 01:47:59 PM PDT 24 506335612 ps
T802 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.522349616 May 28 01:48:06 PM PDT 24 May 28 01:48:12 PM PDT 24 329124968 ps
T803 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3334910479 May 28 01:47:57 PM PDT 24 May 28 01:48:00 PM PDT 24 488135604 ps
T79 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.4272386406 May 28 01:47:56 PM PDT 24 May 28 01:48:00 PM PDT 24 473054638 ps
T115 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.766992813 May 28 01:47:31 PM PDT 24 May 28 01:47:36 PM PDT 24 527583794 ps
T804 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1391047608 May 28 01:48:00 PM PDT 24 May 28 01:48:04 PM PDT 24 329099012 ps
T805 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2434060930 May 28 01:48:00 PM PDT 24 May 28 01:48:05 PM PDT 24 466499762 ps
T806 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2978663179 May 28 01:47:31 PM PDT 24 May 28 01:47:34 PM PDT 24 381053988 ps
T93 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1442787245 May 28 01:47:55 PM PDT 24 May 28 01:47:58 PM PDT 24 506177635 ps
T73 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3342508294 May 28 01:48:03 PM PDT 24 May 28 01:48:10 PM PDT 24 565322557 ps
T59 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3328340256 May 28 01:47:37 PM PDT 24 May 28 01:48:31 PM PDT 24 48981366617 ps
T65 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.325825960 May 28 01:48:00 PM PDT 24 May 28 01:48:25 PM PDT 24 8290925879 ps
T807 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.741809711 May 28 01:48:00 PM PDT 24 May 28 01:48:03 PM PDT 24 380577943 ps
T63 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1036575517 May 28 01:48:01 PM PDT 24 May 28 01:48:07 PM PDT 24 426233894 ps
T129 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3651885833 May 28 01:47:56 PM PDT 24 May 28 01:47:58 PM PDT 24 397535271 ps
T116 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1476530162 May 28 01:47:34 PM PDT 24 May 28 01:47:42 PM PDT 24 1253377598 ps
T808 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3150492152 May 28 01:48:09 PM PDT 24 May 28 01:48:18 PM PDT 24 432718765 ps
T809 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2764775726 May 28 01:48:06 PM PDT 24 May 28 01:48:12 PM PDT 24 452074376 ps
T74 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.583097621 May 28 01:47:36 PM PDT 24 May 28 01:47:43 PM PDT 24 522658085 ps
T810 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3720589480 May 28 01:48:09 PM PDT 24 May 28 01:48:18 PM PDT 24 515925969 ps
T75 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3910763608 May 28 01:48:06 PM PDT 24 May 28 01:48:12 PM PDT 24 854552939 ps
T66 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1087009668 May 28 01:48:00 PM PDT 24 May 28 01:48:09 PM PDT 24 3984514056 ps
T76 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3734462818 May 28 01:47:49 PM PDT 24 May 28 01:47:54 PM PDT 24 816204176 ps
T322 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2553916060 May 28 01:48:00 PM PDT 24 May 28 01:48:23 PM PDT 24 7867988024 ps
T811 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3369006876 May 28 01:48:02 PM PDT 24 May 28 01:48:07 PM PDT 24 485157903 ps
T80 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1344891535 May 28 01:47:35 PM PDT 24 May 28 01:47:51 PM PDT 24 8141481307 ps
T812 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.785639021 May 28 01:48:06 PM PDT 24 May 28 01:48:14 PM PDT 24 508163429 ps
T813 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.878653127 May 28 01:48:03 PM PDT 24 May 28 01:48:08 PM PDT 24 377324349 ps
T814 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.334503215 May 28 01:47:49 PM PDT 24 May 28 01:47:53 PM PDT 24 610555615 ps
T815 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2319623969 May 28 01:47:51 PM PDT 24 May 28 01:47:55 PM PDT 24 323571479 ps
T816 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.967105964 May 28 01:48:07 PM PDT 24 May 28 01:48:13 PM PDT 24 449621559 ps
T817 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1017035469 May 28 01:47:58 PM PDT 24 May 28 01:48:02 PM PDT 24 577132209 ps
T818 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.565698239 May 28 01:48:10 PM PDT 24 May 28 01:48:20 PM PDT 24 496254796 ps
T324 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3967937441 May 28 01:48:01 PM PDT 24 May 28 01:48:10 PM PDT 24 8426184487 ps
T819 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1328396406 May 28 01:48:05 PM PDT 24 May 28 01:48:11 PM PDT 24 429504255 ps
T820 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3253800801 May 28 01:48:09 PM PDT 24 May 28 01:48:17 PM PDT 24 510150913 ps
T821 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1310557401 May 28 01:47:46 PM PDT 24 May 28 01:47:47 PM PDT 24 682201491 ps
T81 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.7107743 May 28 01:48:00 PM PDT 24 May 28 01:48:08 PM PDT 24 3992232221 ps
T822 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.216730610 May 28 01:48:03 PM PDT 24 May 28 01:48:08 PM PDT 24 540621289 ps
T823 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2598552114 May 28 01:47:36 PM PDT 24 May 28 01:47:42 PM PDT 24 742903679 ps
T824 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2981672301 May 28 01:47:50 PM PDT 24 May 28 01:47:53 PM PDT 24 348246917 ps
T825 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2682725274 May 28 01:47:39 PM PDT 24 May 28 01:47:43 PM PDT 24 567687427 ps
T826 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2620929054 May 28 01:48:07 PM PDT 24 May 28 01:48:13 PM PDT 24 448709765 ps
T60 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2537621713 May 28 01:47:56 PM PDT 24 May 28 01:48:08 PM PDT 24 4629230439 ps
T827 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3073965020 May 28 01:47:51 PM PDT 24 May 28 01:47:54 PM PDT 24 667753004 ps
T128 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2981518950 May 28 01:47:51 PM PDT 24 May 28 01:47:55 PM PDT 24 353655962 ps
T117 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.849233390 May 28 01:47:32 PM PDT 24 May 28 01:47:45 PM PDT 24 1973577783 ps
T828 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2333053763 May 28 01:47:49 PM PDT 24 May 28 01:48:10 PM PDT 24 8071261619 ps
T829 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1725690316 May 28 01:47:51 PM PDT 24 May 28 01:47:57 PM PDT 24 4613443155 ps
T830 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.582613070 May 28 01:47:54 PM PDT 24 May 28 01:47:58 PM PDT 24 720172424 ps
T831 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3965151466 May 28 01:47:57 PM PDT 24 May 28 01:48:05 PM PDT 24 9212348280 ps
T832 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.4223821367 May 28 01:47:34 PM PDT 24 May 28 01:47:44 PM PDT 24 4489163755 ps
T118 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2999605361 May 28 01:48:00 PM PDT 24 May 28 01:48:04 PM PDT 24 528938023 ps
T119 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.648879993 May 28 01:47:52 PM PDT 24 May 28 01:47:56 PM PDT 24 477617394 ps
T833 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3487988393 May 28 01:48:01 PM PDT 24 May 28 01:48:06 PM PDT 24 339583757 ps
T834 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.367734238 May 28 01:48:06 PM PDT 24 May 28 01:48:13 PM PDT 24 495716143 ps
T120 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.172837880 May 28 01:48:02 PM PDT 24 May 28 01:48:07 PM PDT 24 472702842 ps
T121 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1651568477 May 28 01:47:51 PM PDT 24 May 28 01:47:54 PM PDT 24 551466867 ps
T323 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1138719553 May 28 01:47:52 PM PDT 24 May 28 01:48:17 PM PDT 24 8664830633 ps
T835 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3369215442 May 28 01:48:11 PM PDT 24 May 28 01:48:19 PM PDT 24 519604927 ps
T836 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1380911656 May 28 01:47:35 PM PDT 24 May 28 01:47:41 PM PDT 24 449282293 ps
T837 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2807245618 May 28 01:47:34 PM PDT 24 May 28 01:47:40 PM PDT 24 503016499 ps
T838 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2987044274 May 28 01:48:02 PM PDT 24 May 28 01:48:07 PM PDT 24 631488700 ps
T839 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2780832087 May 28 01:47:35 PM PDT 24 May 28 01:47:44 PM PDT 24 2161268418 ps
T840 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3043974598 May 28 01:47:58 PM PDT 24 May 28 01:48:02 PM PDT 24 341117697 ps
T841 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2677910800 May 28 01:48:07 PM PDT 24 May 28 01:48:13 PM PDT 24 291102296 ps
T61 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2855712688 May 28 01:48:03 PM PDT 24 May 28 01:48:17 PM PDT 24 4413735510 ps
T842 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1140682481 May 28 01:47:48 PM PDT 24 May 28 01:47:56 PM PDT 24 4813555595 ps
T122 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3636240463 May 28 01:47:57 PM PDT 24 May 28 01:49:33 PM PDT 24 42494247525 ps
T123 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2236548752 May 28 01:47:47 PM PDT 24 May 28 01:48:00 PM PDT 24 14144659867 ps
T843 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2385860373 May 28 01:47:58 PM PDT 24 May 28 01:48:11 PM PDT 24 2291101743 ps
T844 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1272026184 May 28 01:48:10 PM PDT 24 May 28 01:48:19 PM PDT 24 494017037 ps
T845 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3804736267 May 28 01:47:50 PM PDT 24 May 28 01:47:56 PM PDT 24 4760200542 ps
T846 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3565690100 May 28 01:48:06 PM PDT 24 May 28 01:48:12 PM PDT 24 400099942 ps
T847 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3436337516 May 28 01:48:00 PM PDT 24 May 28 01:48:04 PM PDT 24 463472917 ps
T124 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3155623901 May 28 01:47:48 PM PDT 24 May 28 01:47:51 PM PDT 24 385666906 ps
T848 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2558277815 May 28 01:47:33 PM PDT 24 May 28 01:49:28 PM PDT 24 52474010742 ps
T125 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4047555887 May 28 01:48:00 PM PDT 24 May 28 01:48:05 PM PDT 24 376121543 ps
T849 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3484695194 May 28 01:47:35 PM PDT 24 May 28 01:47:43 PM PDT 24 4296149756 ps
T850 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2588808163 May 28 01:48:02 PM PDT 24 May 28 01:48:07 PM PDT 24 576133590 ps
T851 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3823417873 May 28 01:48:10 PM PDT 24 May 28 01:48:18 PM PDT 24 348403277 ps
T852 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.29774301 May 28 01:47:47 PM PDT 24 May 28 01:47:51 PM PDT 24 606556986 ps
T853 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2416911916 May 28 01:48:01 PM PDT 24 May 28 01:48:11 PM PDT 24 4415273754 ps
T854 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.960014072 May 28 01:48:03 PM PDT 24 May 28 01:48:11 PM PDT 24 4788331595 ps
T855 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3279717995 May 28 01:47:33 PM PDT 24 May 28 01:47:39 PM PDT 24 783451896 ps
T856 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2294228049 May 28 01:47:54 PM PDT 24 May 28 01:47:58 PM PDT 24 662719089 ps
T857 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.350492440 May 28 01:47:56 PM PDT 24 May 28 01:47:59 PM PDT 24 514364660 ps
T858 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3553138193 May 28 01:48:00 PM PDT 24 May 28 01:48:09 PM PDT 24 9109433462 ps
T859 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3510803960 May 28 01:47:58 PM PDT 24 May 28 01:48:01 PM PDT 24 500706820 ps
T860 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3915883401 May 28 01:48:10 PM PDT 24 May 28 01:48:18 PM PDT 24 497207288 ps
T861 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1673334835 May 28 01:47:56 PM PDT 24 May 28 01:48:02 PM PDT 24 4525301295 ps
T862 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2964650101 May 28 01:48:01 PM PDT 24 May 28 01:48:06 PM PDT 24 458855310 ps
T863 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3000408645 May 28 01:48:00 PM PDT 24 May 28 01:48:04 PM PDT 24 381213719 ps
T864 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2731248302 May 28 01:47:49 PM PDT 24 May 28 01:47:51 PM PDT 24 633356654 ps
T865 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.4209502446 May 28 01:48:00 PM PDT 24 May 28 01:48:04 PM PDT 24 335784199 ps
T866 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.398733004 May 28 01:47:37 PM PDT 24 May 28 01:48:03 PM PDT 24 5302688282 ps
T867 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1382921521 May 28 01:48:06 PM PDT 24 May 28 01:48:11 PM PDT 24 492375170 ps
T868 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1396599274 May 28 01:47:59 PM PDT 24 May 28 01:48:02 PM PDT 24 315243570 ps
T869 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.4166597587 May 28 01:47:54 PM PDT 24 May 28 01:48:09 PM PDT 24 5153848649 ps
T870 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1077804554 May 28 01:48:06 PM PDT 24 May 28 01:48:13 PM PDT 24 528850958 ps
T871 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2915250380 May 28 01:48:11 PM PDT 24 May 28 01:48:20 PM PDT 24 517825260 ps
T872 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3332033213 May 28 01:48:03 PM PDT 24 May 28 01:48:09 PM PDT 24 406358109 ps
T873 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4001145691 May 28 01:47:32 PM PDT 24 May 28 01:47:38 PM PDT 24 748811186 ps
T874 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2308377335 May 28 01:48:00 PM PDT 24 May 28 01:48:04 PM PDT 24 401278133 ps
T875 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3259812507 May 28 01:47:56 PM PDT 24 May 28 01:48:00 PM PDT 24 2248993308 ps
T876 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.937807436 May 28 01:48:02 PM PDT 24 May 28 01:48:07 PM PDT 24 495595857 ps
T877 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2620924276 May 28 01:47:47 PM PDT 24 May 28 01:47:49 PM PDT 24 380979835 ps
T878 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1533037773 May 28 01:48:03 PM PDT 24 May 28 01:48:11 PM PDT 24 4410761424 ps
T879 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3791194850 May 28 01:48:01 PM PDT 24 May 28 01:48:16 PM PDT 24 3955890487 ps
T880 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.712002871 May 28 01:48:03 PM PDT 24 May 28 01:48:15 PM PDT 24 3534187827 ps
T881 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.809917852 May 28 01:47:59 PM PDT 24 May 28 01:48:03 PM PDT 24 367727939 ps
T882 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1908350626 May 28 01:48:06 PM PDT 24 May 28 01:48:17 PM PDT 24 2204173050 ps
T883 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1302199279 May 28 01:47:58 PM PDT 24 May 28 01:48:02 PM PDT 24 491441477 ps
T884 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2854118784 May 28 01:47:58 PM PDT 24 May 28 01:48:01 PM PDT 24 553785000 ps
T885 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2820306700 May 28 01:47:57 PM PDT 24 May 28 01:48:01 PM PDT 24 1015939504 ps
T886 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2717866698 May 28 01:47:50 PM PDT 24 May 28 01:48:16 PM PDT 24 8377496898 ps
T887 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3596798563 May 28 01:48:00 PM PDT 24 May 28 01:48:06 PM PDT 24 2374501568 ps
T888 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3365767171 May 28 01:48:07 PM PDT 24 May 28 01:48:14 PM PDT 24 521280329 ps
T889 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3326232906 May 28 01:47:50 PM PDT 24 May 28 01:47:58 PM PDT 24 4247826197 ps
T890 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1128164976 May 28 01:48:06 PM PDT 24 May 28 01:48:13 PM PDT 24 360308030 ps
T891 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1292682541 May 28 01:47:35 PM PDT 24 May 28 01:47:40 PM PDT 24 757701076 ps
T892 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3703530310 May 28 01:47:52 PM PDT 24 May 28 01:47:55 PM PDT 24 499104871 ps
T893 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.794393311 May 28 01:47:59 PM PDT 24 May 28 01:48:02 PM PDT 24 760765959 ps
T126 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.4126900026 May 28 01:47:51 PM PDT 24 May 28 01:47:55 PM PDT 24 1241837268 ps
T894 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.4202379423 May 28 01:47:35 PM PDT 24 May 28 01:47:42 PM PDT 24 518958166 ps
T895 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.247909822 May 28 01:47:46 PM PDT 24 May 28 01:47:49 PM PDT 24 601900477 ps
T896 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3375624558 May 28 01:47:57 PM PDT 24 May 28 01:48:03 PM PDT 24 4299030182 ps
T897 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1106992075 May 28 01:47:34 PM PDT 24 May 28 01:47:40 PM PDT 24 1152437625 ps
T898 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.4120717591 May 28 01:48:02 PM PDT 24 May 28 01:48:08 PM PDT 24 2104391379 ps
T899 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.716943689 May 28 01:47:39 PM PDT 24 May 28 01:47:43 PM PDT 24 731673571 ps
T900 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.735895179 May 28 01:47:58 PM PDT 24 May 28 01:48:00 PM PDT 24 393291451 ps
T901 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1237672438 May 28 01:47:48 PM PDT 24 May 28 01:47:50 PM PDT 24 358353811 ps
T902 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.4025762205 May 28 01:48:09 PM PDT 24 May 28 01:48:17 PM PDT 24 330638323 ps
T903 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3093999236 May 28 01:47:50 PM PDT 24 May 28 01:47:53 PM PDT 24 528831078 ps
T904 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2389308759 May 28 01:47:37 PM PDT 24 May 28 01:47:44 PM PDT 24 491521919 ps
T905 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3218323502 May 28 01:47:50 PM PDT 24 May 28 01:47:53 PM PDT 24 316100299 ps
T906 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2558488242 May 28 01:48:03 PM PDT 24 May 28 01:48:08 PM PDT 24 350157000 ps
T907 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1449827506 May 28 01:47:30 PM PDT 24 May 28 01:47:36 PM PDT 24 1089552155 ps
T908 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1594076412 May 28 01:47:59 PM PDT 24 May 28 01:48:04 PM PDT 24 527334347 ps
T909 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2810000942 May 28 01:48:01 PM PDT 24 May 28 01:48:08 PM PDT 24 4439890233 ps
T910 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3242499719 May 28 01:48:01 PM PDT 24 May 28 01:48:08 PM PDT 24 1490909554 ps
T911 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.954879604 May 28 01:47:35 PM PDT 24 May 28 01:47:45 PM PDT 24 4076683830 ps
T912 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.4193367602 May 28 01:47:59 PM PDT 24 May 28 01:48:21 PM PDT 24 4980942553 ps
T913 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3068947452 May 28 01:48:05 PM PDT 24 May 28 01:48:10 PM PDT 24 528677792 ps
T914 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4102224887 May 28 01:47:51 PM PDT 24 May 28 01:47:55 PM PDT 24 781781647 ps
T915 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2414102041 May 28 01:47:48 PM PDT 24 May 28 01:47:51 PM PDT 24 512610261 ps
T916 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2931635383 May 28 01:47:37 PM PDT 24 May 28 01:48:01 PM PDT 24 8054574206 ps
T917 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3596725393 May 28 01:47:35 PM PDT 24 May 28 01:47:41 PM PDT 24 532055940 ps
T918 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.976535907 May 28 01:47:55 PM PDT 24 May 28 01:47:59 PM PDT 24 2530259197 ps
T919 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.850661734 May 28 01:47:50 PM PDT 24 May 28 01:47:55 PM PDT 24 605135384 ps

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2881644028
Short name T10
Test name
Test status
Simulation time 193545463854 ps
CPU time 110.16 seconds
Started May 28 02:26:47 PM PDT 24
Finished May 28 02:28:38 PM PDT 24
Peak memory 201820 kb
Host smart-8d0a17ac-ca22-4665-a2fa-1fe280d9a516
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881644028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2881644028
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3670910034
Short name T11
Test name
Test status
Simulation time 778404995043 ps
CPU time 1307.09 seconds
Started May 28 02:27:10 PM PDT 24
Finished May 28 02:48:58 PM PDT 24
Peak memory 213120 kb
Host smart-83143126-dd8e-4fa6-b2a2-801a18da9792
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670910034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3670910034
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.31218637
Short name T14
Test name
Test status
Simulation time 451123717696 ps
CPU time 571.61 seconds
Started May 28 02:21:54 PM PDT 24
Finished May 28 02:31:27 PM PDT 24
Peak memory 210536 kb
Host smart-785b1212-bbcb-4cc9-81ac-60845e618ed3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31218637 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.31218637
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2266946281
Short name T84
Test name
Test status
Simulation time 502216239709 ps
CPU time 89.87 seconds
Started May 28 02:25:35 PM PDT 24
Finished May 28 02:27:06 PM PDT 24
Peak memory 201844 kb
Host smart-0ab8333b-6ce2-4ebb-bcff-aba2da06dc58
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266946281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2266946281
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3982003265
Short name T16
Test name
Test status
Simulation time 556129110833 ps
CPU time 697.55 seconds
Started May 28 02:28:16 PM PDT 24
Finished May 28 02:39:55 PM PDT 24
Peak memory 218048 kb
Host smart-1a97eea5-d553-4f2d-8991-8bec56b8bbca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982003265 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3982003265
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3477026001
Short name T132
Test name
Test status
Simulation time 544123088182 ps
CPU time 307.61 seconds
Started May 28 02:23:14 PM PDT 24
Finished May 28 02:28:23 PM PDT 24
Peak memory 201852 kb
Host smart-75c592c9-f03d-4da7-bc3b-7a079380928a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477026001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3477026001
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1334323462
Short name T40
Test name
Test status
Simulation time 273614872939 ps
CPU time 347.85 seconds
Started May 28 02:26:01 PM PDT 24
Finished May 28 02:31:50 PM PDT 24
Peak memory 210540 kb
Host smart-3fb26c39-f881-47f5-8199-567aee159322
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334323462 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1334323462
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3148437811
Short name T52
Test name
Test status
Simulation time 562171864865 ps
CPU time 708.47 seconds
Started May 28 02:29:01 PM PDT 24
Finished May 28 02:40:50 PM PDT 24
Peak memory 201844 kb
Host smart-b1916fdd-33b8-4017-a4da-7b380f2d99aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148437811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3148437811
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3301942436
Short name T142
Test name
Test status
Simulation time 354376755894 ps
CPU time 214.01 seconds
Started May 28 02:19:49 PM PDT 24
Finished May 28 02:23:25 PM PDT 24
Peak memory 201856 kb
Host smart-c893ec29-ba7a-484c-ab0d-c9206a6cb62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301942436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3301942436
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2290392499
Short name T38
Test name
Test status
Simulation time 237547042445 ps
CPU time 151.16 seconds
Started May 28 02:26:06 PM PDT 24
Finished May 28 02:28:38 PM PDT 24
Peak memory 210396 kb
Host smart-8cadcf5e-645a-4a87-9409-295575f0dfb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290392499 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2290392499
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3342508294
Short name T73
Test name
Test status
Simulation time 565322557 ps
CPU time 2.91 seconds
Started May 28 01:48:03 PM PDT 24
Finished May 28 01:48:10 PM PDT 24
Peak memory 218328 kb
Host smart-839f85ca-8761-4144-9f98-af22be8727c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342508294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3342508294
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1129006969
Short name T230
Test name
Test status
Simulation time 657016374845 ps
CPU time 358.8 seconds
Started May 28 02:28:59 PM PDT 24
Finished May 28 02:34:59 PM PDT 24
Peak memory 201848 kb
Host smart-5fc7876c-4a5a-48cf-ac28-b34a044d7468
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129006969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1129006969
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3644853987
Short name T49
Test name
Test status
Simulation time 4246724328 ps
CPU time 3.01 seconds
Started May 28 02:19:47 PM PDT 24
Finished May 28 02:19:52 PM PDT 24
Peak memory 217484 kb
Host smart-ea32d29f-9362-4f8c-954e-c05217bceac4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644853987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3644853987
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.104816312
Short name T206
Test name
Test status
Simulation time 502113504613 ps
CPU time 325.98 seconds
Started May 28 02:20:31 PM PDT 24
Finished May 28 02:25:58 PM PDT 24
Peak memory 201932 kb
Host smart-f1610286-b4f0-44d4-87b6-29a308b4a827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104816312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.104816312
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1684041377
Short name T187
Test name
Test status
Simulation time 343748907077 ps
CPU time 754.56 seconds
Started May 28 02:24:59 PM PDT 24
Finished May 28 02:37:35 PM PDT 24
Peak memory 201864 kb
Host smart-5d887e85-2d46-4790-9997-981f8ceb109e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684041377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1684041377
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1073171520
Short name T50
Test name
Test status
Simulation time 425791202973 ps
CPU time 220.23 seconds
Started May 28 02:23:04 PM PDT 24
Finished May 28 02:26:46 PM PDT 24
Peak memory 210216 kb
Host smart-5e8146e2-e513-4c42-90e7-9343add146a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073171520 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1073171520
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2454957832
Short name T62
Test name
Test status
Simulation time 494911951 ps
CPU time 1.88 seconds
Started May 28 01:47:34 PM PDT 24
Finished May 28 01:47:41 PM PDT 24
Peak memory 201736 kb
Host smart-ec3fd295-0de2-407e-adda-931104c3263c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454957832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2454957832
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3068313548
Short name T215
Test name
Test status
Simulation time 499523849273 ps
CPU time 79.92 seconds
Started May 28 02:21:26 PM PDT 24
Finished May 28 02:22:47 PM PDT 24
Peak memory 201840 kb
Host smart-c607e438-66d5-40ca-88b1-dadee435cb52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068313548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3068313548
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1060459291
Short name T36
Test name
Test status
Simulation time 169796685886 ps
CPU time 157.16 seconds
Started May 28 02:19:50 PM PDT 24
Finished May 28 02:22:29 PM PDT 24
Peak memory 210528 kb
Host smart-1ff629c4-654f-40d3-b231-55df0925b0c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060459291 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1060459291
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2974519106
Short name T141
Test name
Test status
Simulation time 505884585434 ps
CPU time 1119.22 seconds
Started May 28 02:21:23 PM PDT 24
Finished May 28 02:40:03 PM PDT 24
Peak memory 201852 kb
Host smart-76026d60-d413-4662-93d6-fef20193ae4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974519106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2974519106
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3820184838
Short name T134
Test name
Test status
Simulation time 1440187315326 ps
CPU time 3492.63 seconds
Started May 28 02:21:12 PM PDT 24
Finished May 28 03:19:26 PM PDT 24
Peak memory 202260 kb
Host smart-6e42c20d-78ff-429d-acc8-acd9d580b1e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820184838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3820184838
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.744681041
Short name T224
Test name
Test status
Simulation time 319703463124 ps
CPU time 583 seconds
Started May 28 02:27:10 PM PDT 24
Finished May 28 02:36:54 PM PDT 24
Peak memory 201864 kb
Host smart-f6e30896-1996-4242-82e7-84e3e176b0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744681041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.744681041
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.253248372
Short name T268
Test name
Test status
Simulation time 356042407743 ps
CPU time 849.47 seconds
Started May 28 02:26:58 PM PDT 24
Finished May 28 02:41:09 PM PDT 24
Peak memory 201772 kb
Host smart-57569dd6-b967-49cf-8b6a-5a4ab88b1dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253248372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.253248372
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3401451817
Short name T130
Test name
Test status
Simulation time 492553197481 ps
CPU time 109.72 seconds
Started May 28 02:28:06 PM PDT 24
Finished May 28 02:29:57 PM PDT 24
Peak memory 201848 kb
Host smart-087671bb-183c-43d6-bffe-20b09d348744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401451817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3401451817
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1167407015
Short name T171
Test name
Test status
Simulation time 331904804764 ps
CPU time 359.44 seconds
Started May 28 02:20:13 PM PDT 24
Finished May 28 02:26:13 PM PDT 24
Peak memory 201836 kb
Host smart-0696d97a-1004-4f05-9260-344a5bb29366
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167407015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1167407015
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1344891535
Short name T80
Test name
Test status
Simulation time 8141481307 ps
CPU time 11.22 seconds
Started May 28 01:47:35 PM PDT 24
Finished May 28 01:47:51 PM PDT 24
Peak memory 202008 kb
Host smart-e14a24b0-f32f-4a65-97e3-66838f011cf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344891535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1344891535
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.174130305
Short name T276
Test name
Test status
Simulation time 582355900704 ps
CPU time 1350.37 seconds
Started May 28 02:21:34 PM PDT 24
Finished May 28 02:44:06 PM PDT 24
Peak memory 201852 kb
Host smart-f9438f97-0856-4cab-a1b0-3f1e45a8830f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174130305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.174130305
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1592455193
Short name T222
Test name
Test status
Simulation time 326594347193 ps
CPU time 192.24 seconds
Started May 28 02:25:10 PM PDT 24
Finished May 28 02:28:23 PM PDT 24
Peak memory 201928 kb
Host smart-484b85b0-6019-4302-84ee-d717ff7d3713
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592455193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1592455193
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1728587155
Short name T334
Test name
Test status
Simulation time 304395200 ps
CPU time 1.33 seconds
Started May 28 02:19:58 PM PDT 24
Finished May 28 02:20:02 PM PDT 24
Peak memory 201508 kb
Host smart-9ddeee41-70d1-42a8-93c3-390e21fead95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728587155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1728587155
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3034295420
Short name T203
Test name
Test status
Simulation time 364127778902 ps
CPU time 446.99 seconds
Started May 28 02:25:48 PM PDT 24
Finished May 28 02:33:16 PM PDT 24
Peak memory 201856 kb
Host smart-327a7117-60cc-4b41-a97e-a2a80b39a7a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034295420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3034295420
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3763613077
Short name T209
Test name
Test status
Simulation time 487284298248 ps
CPU time 292.49 seconds
Started May 28 02:27:53 PM PDT 24
Finished May 28 02:32:47 PM PDT 24
Peak memory 201848 kb
Host smart-0c00bf07-ecad-4c5e-8751-96f0c9f8c217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763613077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3763613077
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.10618604
Short name T17
Test name
Test status
Simulation time 319137290168 ps
CPU time 267.28 seconds
Started May 28 02:28:38 PM PDT 24
Finished May 28 02:33:06 PM PDT 24
Peak memory 210508 kb
Host smart-d212dc29-e57d-44d2-84dd-3a47ac56946d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10618604 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.10618604
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2989236902
Short name T285
Test name
Test status
Simulation time 517392541400 ps
CPU time 1239.56 seconds
Started May 28 02:22:43 PM PDT 24
Finished May 28 02:43:23 PM PDT 24
Peak memory 201828 kb
Host smart-e2570a9e-7dca-4b80-ae75-7a55f6a7c7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989236902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2989236902
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.331644729
Short name T245
Test name
Test status
Simulation time 340339216785 ps
CPU time 797.17 seconds
Started May 28 02:24:19 PM PDT 24
Finished May 28 02:37:37 PM PDT 24
Peak memory 201860 kb
Host smart-49fb4c2d-2853-4845-9987-a96c4c7f684d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331644729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.331644729
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2907368101
Short name T287
Test name
Test status
Simulation time 551275568342 ps
CPU time 1216.16 seconds
Started May 28 02:19:49 PM PDT 24
Finished May 28 02:40:07 PM PDT 24
Peak memory 201940 kb
Host smart-01f0b4ab-c702-46d5-a13d-9133b4fb3792
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907368101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2907368101
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1024419413
Short name T155
Test name
Test status
Simulation time 331298319448 ps
CPU time 213.77 seconds
Started May 28 02:23:28 PM PDT 24
Finished May 28 02:27:02 PM PDT 24
Peak memory 201860 kb
Host smart-e7f4ccfc-1148-4769-b3ab-a11a5677c54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024419413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1024419413
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1897314406
Short name T286
Test name
Test status
Simulation time 333255083355 ps
CPU time 602.17 seconds
Started May 28 02:23:39 PM PDT 24
Finished May 28 02:33:43 PM PDT 24
Peak memory 201920 kb
Host smart-8656a7ea-4525-49e7-9865-5896324080e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897314406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1897314406
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3328340256
Short name T59
Test name
Test status
Simulation time 48981366617 ps
CPU time 50.92 seconds
Started May 28 01:47:37 PM PDT 24
Finished May 28 01:48:31 PM PDT 24
Peak memory 201796 kb
Host smart-06211650-0ae3-40b4-9ab9-9831eb34a702
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328340256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3328340256
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3129782543
Short name T205
Test name
Test status
Simulation time 163191307795 ps
CPU time 197.49 seconds
Started May 28 02:26:34 PM PDT 24
Finished May 28 02:29:52 PM PDT 24
Peak memory 201932 kb
Host smart-1dd1d36a-9d06-4b7b-bf82-17a5ddbf4af0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129782543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3129782543
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.1486878433
Short name T261
Test name
Test status
Simulation time 557735107396 ps
CPU time 684.2 seconds
Started May 28 02:22:19 PM PDT 24
Finished May 28 02:33:44 PM PDT 24
Peak memory 201916 kb
Host smart-f9025695-8ac3-47bd-aac3-7522b1f13683
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486878433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.1486878433
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.748617371
Short name T151
Test name
Test status
Simulation time 564183232342 ps
CPU time 1098.37 seconds
Started May 28 02:25:23 PM PDT 24
Finished May 28 02:43:42 PM PDT 24
Peak memory 218580 kb
Host smart-8ec421f7-fe90-47f3-b24b-4baba0aeaf2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748617371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
748617371
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1189268695
Short name T157
Test name
Test status
Simulation time 274756708862 ps
CPU time 491.64 seconds
Started May 28 02:27:55 PM PDT 24
Finished May 28 02:36:07 PM PDT 24
Peak memory 202160 kb
Host smart-267632f8-43f8-47cc-a6dd-5088484d6f58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189268695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1189268695
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3375670721
Short name T283
Test name
Test status
Simulation time 335425962087 ps
CPU time 201.3 seconds
Started May 28 02:21:48 PM PDT 24
Finished May 28 02:25:10 PM PDT 24
Peak memory 201940 kb
Host smart-ab5e4606-a4d5-4866-8d04-0963667dcaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375670721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3375670721
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3351500925
Short name T316
Test name
Test status
Simulation time 853110787192 ps
CPU time 429.98 seconds
Started May 28 02:23:04 PM PDT 24
Finished May 28 02:30:16 PM PDT 24
Peak memory 211968 kb
Host smart-f0a4680d-613c-4790-8e7c-4a4e5d333665
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351500925 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3351500925
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1547480315
Short name T237
Test name
Test status
Simulation time 328016554159 ps
CPU time 191.27 seconds
Started May 28 02:25:35 PM PDT 24
Finished May 28 02:28:48 PM PDT 24
Peak memory 201864 kb
Host smart-bdec21e0-9e27-46f9-a751-9d3b53bf4abc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547480315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1547480315
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3881982990
Short name T248
Test name
Test status
Simulation time 248853311721 ps
CPU time 153.11 seconds
Started May 28 02:20:50 PM PDT 24
Finished May 28 02:23:24 PM PDT 24
Peak memory 210184 kb
Host smart-a2c00a71-a33c-48f4-bcb4-aefafbfd9b57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881982990 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3881982990
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1942757043
Short name T137
Test name
Test status
Simulation time 492550110267 ps
CPU time 246.11 seconds
Started May 28 02:19:50 PM PDT 24
Finished May 28 02:23:57 PM PDT 24
Peak memory 202132 kb
Host smart-6037e13d-7f00-425f-abba-fd9521c7418b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942757043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1942757043
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2320948347
Short name T304
Test name
Test status
Simulation time 495132957250 ps
CPU time 511.86 seconds
Started May 28 02:21:49 PM PDT 24
Finished May 28 02:30:22 PM PDT 24
Peak memory 201940 kb
Host smart-4b547bac-89c0-4f2e-8842-d86764586ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320948347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2320948347
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2613724448
Short name T259
Test name
Test status
Simulation time 518427455805 ps
CPU time 885.68 seconds
Started May 28 02:22:31 PM PDT 24
Finished May 28 02:37:17 PM PDT 24
Peak memory 201816 kb
Host smart-0755c313-825a-4b0e-aedc-882d7e6437ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613724448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2613724448
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1023253748
Short name T140
Test name
Test status
Simulation time 569831810840 ps
CPU time 307.63 seconds
Started May 28 02:24:44 PM PDT 24
Finished May 28 02:29:53 PM PDT 24
Peak memory 201924 kb
Host smart-32a5a767-3e30-4a16-a732-ad4588b984d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023253748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1023253748
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3332033213
Short name T872
Test name
Test status
Simulation time 406358109 ps
CPU time 2.33 seconds
Started May 28 01:48:03 PM PDT 24
Finished May 28 01:48:09 PM PDT 24
Peak memory 201988 kb
Host smart-af4b095a-afd2-49ab-bcda-944d788fb952
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332033213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3332033213
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3426912323
Short name T303
Test name
Test status
Simulation time 212368689764 ps
CPU time 239.82 seconds
Started May 28 02:23:05 PM PDT 24
Finished May 28 02:27:07 PM PDT 24
Peak memory 201904 kb
Host smart-7f93c822-1b60-494c-baee-cb50c3567ea1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426912323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3426912323
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2285808497
Short name T41
Test name
Test status
Simulation time 326374753042 ps
CPU time 697.17 seconds
Started May 28 02:23:48 PM PDT 24
Finished May 28 02:35:26 PM PDT 24
Peak memory 201840 kb
Host smart-d931c4ed-3ced-4538-929d-de1c96083cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285808497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2285808497
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2284455468
Short name T311
Test name
Test status
Simulation time 331288024986 ps
CPU time 119.89 seconds
Started May 28 02:26:45 PM PDT 24
Finished May 28 02:28:46 PM PDT 24
Peak memory 201928 kb
Host smart-6302d8a6-8a2f-4ac5-8241-7683c1c584d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284455468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2284455468
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1130161253
Short name T223
Test name
Test status
Simulation time 627272767946 ps
CPU time 671.99 seconds
Started May 28 02:27:10 PM PDT 24
Finished May 28 02:38:23 PM PDT 24
Peak memory 201896 kb
Host smart-38d06109-0594-4fcc-b0ed-0a7509f3cead
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130161253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1130161253
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1329624564
Short name T241
Test name
Test status
Simulation time 597316779686 ps
CPU time 1423.19 seconds
Started May 28 02:28:27 PM PDT 24
Finished May 28 02:52:11 PM PDT 24
Peak memory 201856 kb
Host smart-e5b821d4-45b9-411c-9fc8-797d85bb06e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329624564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1329624564
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2530332748
Short name T96
Test name
Test status
Simulation time 322381649558 ps
CPU time 205.06 seconds
Started May 28 02:19:39 PM PDT 24
Finished May 28 02:23:05 PM PDT 24
Peak memory 202068 kb
Host smart-948cd60d-a1aa-4a61-92d1-a29c7d5e80f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530332748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2530332748
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1241673509
Short name T294
Test name
Test status
Simulation time 462538596964 ps
CPU time 1103.87 seconds
Started May 28 02:21:55 PM PDT 24
Finished May 28 02:40:20 PM PDT 24
Peak memory 201840 kb
Host smart-3a9edee6-3851-4d8b-9150-c05dc00d50bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241673509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1241673509
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3959478761
Short name T290
Test name
Test status
Simulation time 533082492783 ps
CPU time 339.13 seconds
Started May 28 02:22:54 PM PDT 24
Finished May 28 02:28:35 PM PDT 24
Peak memory 201824 kb
Host smart-ce7e3ac2-f091-433e-a9c1-b97f9d521118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959478761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3959478761
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.4077203338
Short name T198
Test name
Test status
Simulation time 317787362812 ps
CPU time 1121.7 seconds
Started May 28 02:23:39 PM PDT 24
Finished May 28 02:42:23 PM PDT 24
Peak memory 212616 kb
Host smart-823f436b-7c4a-4b9b-ab2e-cc0050a0b2b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077203338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.4077203338
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2116590934
Short name T34
Test name
Test status
Simulation time 400194459219 ps
CPU time 308.18 seconds
Started May 28 02:29:25 PM PDT 24
Finished May 28 02:34:34 PM PDT 24
Peak memory 201852 kb
Host smart-3a0f7d29-5794-42d7-a1f6-5fc64221cb88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116590934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2116590934
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.325825960
Short name T65
Test name
Test status
Simulation time 8290925879 ps
CPU time 22.48 seconds
Started May 28 01:48:00 PM PDT 24
Finished May 28 01:48:25 PM PDT 24
Peak memory 201940 kb
Host smart-93d0d4da-361e-40f2-b8be-2bf959a23bc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325825960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.325825960
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2468665895
Short name T292
Test name
Test status
Simulation time 599377467975 ps
CPU time 1031.67 seconds
Started May 28 02:21:55 PM PDT 24
Finished May 28 02:39:08 PM PDT 24
Peak memory 210356 kb
Host smart-32506303-8983-49e8-b7a2-7f7338c05727
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468665895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2468665895
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3165742010
Short name T100
Test name
Test status
Simulation time 506518531566 ps
CPU time 318.67 seconds
Started May 28 02:24:00 PM PDT 24
Finished May 28 02:29:20 PM PDT 24
Peak memory 201792 kb
Host smart-b3daa3ed-63a9-4f77-a3ee-e58232372590
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165742010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3165742010
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.645545203
Short name T170
Test name
Test status
Simulation time 679878244157 ps
CPU time 186.27 seconds
Started May 28 02:24:46 PM PDT 24
Finished May 28 02:27:53 PM PDT 24
Peak memory 201848 kb
Host smart-2144a4a8-ee9c-4d3b-839d-cb275709316e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645545203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
645545203
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.566702292
Short name T110
Test name
Test status
Simulation time 161820853291 ps
CPU time 336.74 seconds
Started May 28 02:25:09 PM PDT 24
Finished May 28 02:30:46 PM PDT 24
Peak memory 201840 kb
Host smart-c172545f-5c72-492f-8f25-49e59a45ad0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566702292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.566702292
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.497479195
Short name T239
Test name
Test status
Simulation time 1369643878640 ps
CPU time 3456.42 seconds
Started May 28 02:28:09 PM PDT 24
Finished May 28 03:25:47 PM PDT 24
Peak memory 210432 kb
Host smart-cf7015ef-c34e-4423-b256-f650a46d8f10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497479195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
497479195
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2136459273
Short name T108
Test name
Test status
Simulation time 344489634500 ps
CPU time 213.96 seconds
Started May 28 02:20:51 PM PDT 24
Finished May 28 02:24:26 PM PDT 24
Peak memory 201944 kb
Host smart-a7fd88e3-196d-40c1-b8db-d2cf02df96d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136459273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2136459273
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1655387012
Short name T315
Test name
Test status
Simulation time 207680650531 ps
CPU time 437.66 seconds
Started May 28 02:19:47 PM PDT 24
Finished May 28 02:27:07 PM PDT 24
Peak memory 201908 kb
Host smart-7d3fd3da-5b84-42e1-a463-616039ddac67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655387012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1655387012
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.28915102
Short name T26
Test name
Test status
Simulation time 340103290102 ps
CPU time 194.04 seconds
Started May 28 02:21:55 PM PDT 24
Finished May 28 02:25:11 PM PDT 24
Peak memory 201840 kb
Host smart-efd5af7c-1a95-4baf-a39d-e0820a76c016
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28915102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gatin
g.28915102
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2834301924
Short name T53
Test name
Test status
Simulation time 195884640793 ps
CPU time 440.18 seconds
Started May 28 02:21:57 PM PDT 24
Finished May 28 02:29:18 PM PDT 24
Peak memory 201920 kb
Host smart-d1696a23-95c7-41a2-8aba-f0ff14f3cc58
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834301924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.2834301924
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1713276917
Short name T199
Test name
Test status
Simulation time 436282998548 ps
CPU time 1419.86 seconds
Started May 28 02:22:17 PM PDT 24
Finished May 28 02:45:59 PM PDT 24
Peak memory 212488 kb
Host smart-b22d463e-ff0c-4d63-8885-4c0071b127cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713276917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1713276917
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.789016734
Short name T226
Test name
Test status
Simulation time 176767180700 ps
CPU time 415.19 seconds
Started May 28 02:23:17 PM PDT 24
Finished May 28 02:30:13 PM PDT 24
Peak memory 201928 kb
Host smart-a8952d6e-f1f7-463c-88e4-6a6c6ebc4f38
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789016734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.789016734
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.334283057
Short name T256
Test name
Test status
Simulation time 174422707318 ps
CPU time 101.94 seconds
Started May 28 02:23:50 PM PDT 24
Finished May 28 02:25:33 PM PDT 24
Peak memory 201932 kb
Host smart-448ff096-7e52-40f4-bf56-8ad75574d3fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334283057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.334283057
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1742529415
Short name T277
Test name
Test status
Simulation time 336395081371 ps
CPU time 757.47 seconds
Started May 28 02:25:00 PM PDT 24
Finished May 28 02:37:39 PM PDT 24
Peak memory 201856 kb
Host smart-c5470032-5169-4863-95ba-7aed5c2da8fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742529415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1742529415
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3345342459
Short name T262
Test name
Test status
Simulation time 353697299217 ps
CPU time 807.2 seconds
Started May 28 02:25:24 PM PDT 24
Finished May 28 02:38:52 PM PDT 24
Peak memory 201828 kb
Host smart-4edb0cf0-c0cb-45af-8eef-607faff0a7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345342459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3345342459
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.648419403
Short name T196
Test name
Test status
Simulation time 103716780147 ps
CPU time 368.26 seconds
Started May 28 02:20:15 PM PDT 24
Finished May 28 02:26:25 PM PDT 24
Peak memory 202164 kb
Host smart-a39350b6-c81e-481a-9ffb-2f1547840b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648419403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.648419403
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.4228790091
Short name T291
Test name
Test status
Simulation time 201182981553 ps
CPU time 413.98 seconds
Started May 28 02:20:13 PM PDT 24
Finished May 28 02:27:09 PM PDT 24
Peak memory 201908 kb
Host smart-85ad8bf8-9ff5-4d40-92cb-6526ba5eae54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228790091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
4228790091
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2644195453
Short name T161
Test name
Test status
Simulation time 161363988393 ps
CPU time 182.56 seconds
Started May 28 02:26:34 PM PDT 24
Finished May 28 02:29:38 PM PDT 24
Peak memory 201832 kb
Host smart-4685ea1a-242c-4da0-8b12-7b9726a24797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644195453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2644195453
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1055407077
Short name T251
Test name
Test status
Simulation time 326457454513 ps
CPU time 190.68 seconds
Started May 28 02:26:59 PM PDT 24
Finished May 28 02:30:10 PM PDT 24
Peak memory 201912 kb
Host smart-4a70ab05-9cc0-4533-a7c5-f78be46037c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055407077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1055407077
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2914954794
Short name T289
Test name
Test status
Simulation time 155393535328 ps
CPU time 191.68 seconds
Started May 28 02:27:53 PM PDT 24
Finished May 28 02:31:06 PM PDT 24
Peak memory 202016 kb
Host smart-24770815-455f-4c25-acb1-959f63dd20be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914954794 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2914954794
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2468313397
Short name T309
Test name
Test status
Simulation time 522378963765 ps
CPU time 1019.31 seconds
Started May 28 02:29:26 PM PDT 24
Finished May 28 02:46:26 PM PDT 24
Peak memory 201920 kb
Host smart-e3a40770-053a-4787-91cf-b71b71d5441b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468313397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2468313397
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3310686465
Short name T22
Test name
Test status
Simulation time 237872927013 ps
CPU time 174.45 seconds
Started May 28 02:20:59 PM PDT 24
Finished May 28 02:23:55 PM PDT 24
Peak memory 210448 kb
Host smart-939a0c07-289d-4745-953a-45849939e125
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310686465 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3310686465
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.182456490
Short name T266
Test name
Test status
Simulation time 560711095847 ps
CPU time 323.78 seconds
Started May 28 02:20:57 PM PDT 24
Finished May 28 02:26:22 PM PDT 24
Peak memory 201652 kb
Host smart-e9d03ac3-2088-4387-be64-659b0cfa1e44
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182456490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.182456490
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2598552114
Short name T823
Test name
Test status
Simulation time 742903679 ps
CPU time 2.03 seconds
Started May 28 01:47:36 PM PDT 24
Finished May 28 01:47:42 PM PDT 24
Peak memory 201948 kb
Host smart-54cd067b-1990-46df-b045-df055d1426ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598552114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2598552114
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2558277815
Short name T848
Test name
Test status
Simulation time 52474010742 ps
CPU time 110.93 seconds
Started May 28 01:47:33 PM PDT 24
Finished May 28 01:49:28 PM PDT 24
Peak memory 201984 kb
Host smart-9b43e986-6791-4996-beab-368eff16379b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558277815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2558277815
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1106992075
Short name T897
Test name
Test status
Simulation time 1152437625 ps
CPU time 1.84 seconds
Started May 28 01:47:34 PM PDT 24
Finished May 28 01:47:40 PM PDT 24
Peak memory 201728 kb
Host smart-6585432d-76ac-42f9-ba13-7de39e21b23c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106992075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.1106992075
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2682725274
Short name T825
Test name
Test status
Simulation time 567687427 ps
CPU time 1.53 seconds
Started May 28 01:47:39 PM PDT 24
Finished May 28 01:47:43 PM PDT 24
Peak memory 201728 kb
Host smart-6c75aaa6-3b29-4408-b7ef-5ca08f9fa4e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682725274 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2682725274
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2807245618
Short name T837
Test name
Test status
Simulation time 503016499 ps
CPU time 1.77 seconds
Started May 28 01:47:34 PM PDT 24
Finished May 28 01:47:40 PM PDT 24
Peak memory 201724 kb
Host smart-2bedb571-c243-464d-9164-218e7fe2b674
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807245618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2807245618
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2780832087
Short name T839
Test name
Test status
Simulation time 2161268418 ps
CPU time 4.78 seconds
Started May 28 01:47:35 PM PDT 24
Finished May 28 01:47:44 PM PDT 24
Peak memory 201796 kb
Host smart-359f3e39-8a11-4197-acf2-7941aefd2f5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780832087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2780832087
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.716943689
Short name T899
Test name
Test status
Simulation time 731673571 ps
CPU time 1.94 seconds
Started May 28 01:47:39 PM PDT 24
Finished May 28 01:47:43 PM PDT 24
Peak memory 201912 kb
Host smart-fef5a039-a8ee-4557-bfc4-bea80c2f0c08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716943689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.716943689
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4001145691
Short name T873
Test name
Test status
Simulation time 748811186 ps
CPU time 3.76 seconds
Started May 28 01:47:32 PM PDT 24
Finished May 28 01:47:38 PM PDT 24
Peak memory 201964 kb
Host smart-91b251d2-c86a-41f3-9e1d-be5466566be8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001145691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.4001145691
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.849233390
Short name T117
Test name
Test status
Simulation time 1973577783 ps
CPU time 9.48 seconds
Started May 28 01:47:32 PM PDT 24
Finished May 28 01:47:45 PM PDT 24
Peak memory 201916 kb
Host smart-e5de5146-f345-47e5-a524-2c6300edcc1d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849233390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.849233390
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3279717995
Short name T855
Test name
Test status
Simulation time 783451896 ps
CPU time 2.57 seconds
Started May 28 01:47:33 PM PDT 24
Finished May 28 01:47:39 PM PDT 24
Peak memory 201744 kb
Host smart-bbfc464a-ce90-40d8-a582-9a009fc04edd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279717995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3279717995
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1627828909
Short name T69
Test name
Test status
Simulation time 512665062 ps
CPU time 2.28 seconds
Started May 28 01:47:38 PM PDT 24
Finished May 28 01:47:43 PM PDT 24
Peak memory 201696 kb
Host smart-cd16a313-6d3d-4b4d-a15e-d9706501bb56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627828909 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1627828909
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1914757234
Short name T114
Test name
Test status
Simulation time 431535588 ps
CPU time 1.04 seconds
Started May 28 01:47:34 PM PDT 24
Finished May 28 01:47:39 PM PDT 24
Peak memory 201748 kb
Host smart-d6735728-7f43-4f06-9b69-d24828c61074
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914757234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1914757234
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3596725393
Short name T917
Test name
Test status
Simulation time 532055940 ps
CPU time 1 seconds
Started May 28 01:47:35 PM PDT 24
Finished May 28 01:47:41 PM PDT 24
Peak memory 201648 kb
Host smart-d4783978-4d2f-4df4-a071-45a9786d9142
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596725393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3596725393
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.954879604
Short name T911
Test name
Test status
Simulation time 4076683830 ps
CPU time 5.94 seconds
Started May 28 01:47:35 PM PDT 24
Finished May 28 01:47:45 PM PDT 24
Peak memory 201972 kb
Host smart-7baaa485-410f-48b6-85b1-f3e86a264535
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954879604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.954879604
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.4202379423
Short name T894
Test name
Test status
Simulation time 518958166 ps
CPU time 3.31 seconds
Started May 28 01:47:35 PM PDT 24
Finished May 28 01:47:42 PM PDT 24
Peak memory 201972 kb
Host smart-ff2b938a-2533-4311-ba15-71f208d914f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202379423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.4202379423
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.4223821367
Short name T832
Test name
Test status
Simulation time 4489163755 ps
CPU time 6.3 seconds
Started May 28 01:47:34 PM PDT 24
Finished May 28 01:47:44 PM PDT 24
Peak memory 201980 kb
Host smart-18c03635-69ed-468a-842a-5a5ec3751a9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223821367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.4223821367
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.247909822
Short name T895
Test name
Test status
Simulation time 601900477 ps
CPU time 2.24 seconds
Started May 28 01:47:46 PM PDT 24
Finished May 28 01:47:49 PM PDT 24
Peak memory 201748 kb
Host smart-f07b64a8-6b00-4a98-a96b-a2f2d8bd8be7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247909822 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.247909822
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2981518950
Short name T128
Test name
Test status
Simulation time 353655962 ps
CPU time 1.51 seconds
Started May 28 01:47:51 PM PDT 24
Finished May 28 01:47:55 PM PDT 24
Peak memory 201660 kb
Host smart-9499d883-ff83-484e-a5f6-a5e9bd45f40d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981518950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2981518950
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.878653127
Short name T813
Test name
Test status
Simulation time 377324349 ps
CPU time 0.83 seconds
Started May 28 01:48:03 PM PDT 24
Finished May 28 01:48:08 PM PDT 24
Peak memory 201740 kb
Host smart-0b5f7c71-b257-440b-ab55-37467acfa8e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878653127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.878653127
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.712002871
Short name T880
Test name
Test status
Simulation time 3534187827 ps
CPU time 8.33 seconds
Started May 28 01:48:03 PM PDT 24
Finished May 28 01:48:15 PM PDT 24
Peak memory 202048 kb
Host smart-c02bfd8b-b7e0-43d6-bea1-195db1cd472e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712002871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.712002871
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.334503215
Short name T814
Test name
Test status
Simulation time 610555615 ps
CPU time 2.55 seconds
Started May 28 01:47:49 PM PDT 24
Finished May 28 01:47:53 PM PDT 24
Peak memory 218376 kb
Host smart-8accebb3-c76c-4716-8fbb-56f5a9e5928a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334503215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.334503215
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3553138193
Short name T858
Test name
Test status
Simulation time 9109433462 ps
CPU time 5.68 seconds
Started May 28 01:48:00 PM PDT 24
Finished May 28 01:48:09 PM PDT 24
Peak memory 202000 kb
Host smart-a595db08-9f72-4845-9632-37f43e366be7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553138193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3553138193
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3703530310
Short name T892
Test name
Test status
Simulation time 499104871 ps
CPU time 1.3 seconds
Started May 28 01:47:52 PM PDT 24
Finished May 28 01:47:55 PM PDT 24
Peak memory 201776 kb
Host smart-15981772-db1a-4567-b502-5c9d870ce239
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703530310 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3703530310
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.25769672
Short name T112
Test name
Test status
Simulation time 428597403 ps
CPU time 1.04 seconds
Started May 28 01:47:56 PM PDT 24
Finished May 28 01:47:59 PM PDT 24
Peak memory 201748 kb
Host smart-f136e094-2a4b-4bab-a897-ce1494e01fd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25769672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.25769672
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3093999236
Short name T903
Test name
Test status
Simulation time 528831078 ps
CPU time 1.82 seconds
Started May 28 01:47:50 PM PDT 24
Finished May 28 01:47:53 PM PDT 24
Peak memory 201672 kb
Host smart-00b13a7f-e359-41f3-b087-9362e71c00f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093999236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3093999236
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.960014072
Short name T854
Test name
Test status
Simulation time 4788331595 ps
CPU time 3.58 seconds
Started May 28 01:48:03 PM PDT 24
Finished May 28 01:48:11 PM PDT 24
Peak memory 202048 kb
Host smart-fa24918d-859c-4cda-a2b5-fe02bdd781a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960014072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.960014072
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3734462818
Short name T76
Test name
Test status
Simulation time 816204176 ps
CPU time 2.97 seconds
Started May 28 01:47:49 PM PDT 24
Finished May 28 01:47:54 PM PDT 24
Peak memory 217884 kb
Host smart-04a3135c-3556-4960-afb7-d674dc36fdbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734462818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3734462818
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1138719553
Short name T323
Test name
Test status
Simulation time 8664830633 ps
CPU time 23.2 seconds
Started May 28 01:47:52 PM PDT 24
Finished May 28 01:48:17 PM PDT 24
Peak memory 202004 kb
Host smart-ba46dc98-582d-42ad-85f6-3e56a8f45e14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138719553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1138719553
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1302199279
Short name T883
Test name
Test status
Simulation time 491441477 ps
CPU time 2.13 seconds
Started May 28 01:47:58 PM PDT 24
Finished May 28 01:48:02 PM PDT 24
Peak memory 201780 kb
Host smart-62c77b20-51b4-49ca-ac94-8c9f308ffb46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302199279 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.1302199279
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.172837880
Short name T120
Test name
Test status
Simulation time 472702842 ps
CPU time 1.74 seconds
Started May 28 01:48:02 PM PDT 24
Finished May 28 01:48:07 PM PDT 24
Peak memory 201704 kb
Host smart-19605413-5219-45de-aaa3-d1887eff724d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172837880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.172837880
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3334910479
Short name T803
Test name
Test status
Simulation time 488135604 ps
CPU time 1.15 seconds
Started May 28 01:47:57 PM PDT 24
Finished May 28 01:48:00 PM PDT 24
Peak memory 201720 kb
Host smart-0ed9c091-e09e-4bc9-b16f-98b020afa918
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334910479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3334910479
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.4120717591
Short name T898
Test name
Test status
Simulation time 2104391379 ps
CPU time 2.39 seconds
Started May 28 01:48:02 PM PDT 24
Finished May 28 01:48:08 PM PDT 24
Peak memory 201708 kb
Host smart-880d602f-4e5d-4184-883b-2c6097d682f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120717591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.4120717591
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1725690316
Short name T829
Test name
Test status
Simulation time 4613443155 ps
CPU time 4.55 seconds
Started May 28 01:47:51 PM PDT 24
Finished May 28 01:47:57 PM PDT 24
Peak memory 202004 kb
Host smart-e0266e42-b66b-4a64-8c09-6295fcbf7b0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725690316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1725690316
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2588808163
Short name T850
Test name
Test status
Simulation time 576133590 ps
CPU time 1.48 seconds
Started May 28 01:48:02 PM PDT 24
Finished May 28 01:48:07 PM PDT 24
Peak memory 201776 kb
Host smart-b202b82d-6a3b-4956-b98d-d1dcdac87b4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588808163 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2588808163
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1036575517
Short name T63
Test name
Test status
Simulation time 426233894 ps
CPU time 1.81 seconds
Started May 28 01:48:01 PM PDT 24
Finished May 28 01:48:07 PM PDT 24
Peak memory 201664 kb
Host smart-3b72d87c-9015-4d55-842f-f9d84bb95f9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036575517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1036575517
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2558488242
Short name T906
Test name
Test status
Simulation time 350157000 ps
CPU time 0.79 seconds
Started May 28 01:48:03 PM PDT 24
Finished May 28 01:48:08 PM PDT 24
Peak memory 201728 kb
Host smart-715c2237-cfaf-4d7c-a998-a585a9d4877a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558488242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2558488242
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1533037773
Short name T878
Test name
Test status
Simulation time 4410761424 ps
CPU time 4.72 seconds
Started May 28 01:48:03 PM PDT 24
Finished May 28 01:48:11 PM PDT 24
Peak memory 202020 kb
Host smart-b0b115d3-8497-4a0e-a973-3c31139eeaa2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533037773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1533037773
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.809917852
Short name T881
Test name
Test status
Simulation time 367727939 ps
CPU time 2.8 seconds
Started May 28 01:47:59 PM PDT 24
Finished May 28 01:48:03 PM PDT 24
Peak memory 210220 kb
Host smart-61b6be01-bfed-48f0-bef4-841b0985d945
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809917852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.809917852
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1901737133
Short name T64
Test name
Test status
Simulation time 3840909054 ps
CPU time 5.69 seconds
Started May 28 01:48:01 PM PDT 24
Finished May 28 01:48:11 PM PDT 24
Peak memory 201936 kb
Host smart-060a7bb3-f9e3-42c3-9625-799bf49fbf7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901737133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1901737133
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2987044274
Short name T838
Test name
Test status
Simulation time 631488700 ps
CPU time 1.55 seconds
Started May 28 01:48:02 PM PDT 24
Finished May 28 01:48:07 PM PDT 24
Peak memory 201776 kb
Host smart-ad81c07b-b9b6-4790-a46a-12dcfa295282
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987044274 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2987044274
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2999605361
Short name T118
Test name
Test status
Simulation time 528938023 ps
CPU time 1.05 seconds
Started May 28 01:48:00 PM PDT 24
Finished May 28 01:48:04 PM PDT 24
Peak memory 201660 kb
Host smart-a73c8166-37e8-4238-aa09-637e820d4d74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999605361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2999605361
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3487988393
Short name T833
Test name
Test status
Simulation time 339583757 ps
CPU time 0.9 seconds
Started May 28 01:48:01 PM PDT 24
Finished May 28 01:48:06 PM PDT 24
Peak memory 201932 kb
Host smart-45343817-00b0-4efe-9ff9-dc42f58c4ffe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487988393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3487988393
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3596798563
Short name T887
Test name
Test status
Simulation time 2374501568 ps
CPU time 2.84 seconds
Started May 28 01:48:00 PM PDT 24
Finished May 28 01:48:06 PM PDT 24
Peak memory 201728 kb
Host smart-8555dd81-8939-432e-b90d-a02cb1216257
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596798563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3596798563
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3965151466
Short name T831
Test name
Test status
Simulation time 9212348280 ps
CPU time 5.56 seconds
Started May 28 01:47:57 PM PDT 24
Finished May 28 01:48:05 PM PDT 24
Peak memory 202028 kb
Host smart-0a464bdc-700a-4639-8172-d0efd4a11995
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965151466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3965151466
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.4120870203
Short name T92
Test name
Test status
Simulation time 638828303 ps
CPU time 1.09 seconds
Started May 28 01:48:07 PM PDT 24
Finished May 28 01:48:13 PM PDT 24
Peak memory 201780 kb
Host smart-372ccb52-df6f-4325-8239-13e532102978
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120870203 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.4120870203
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3565690100
Short name T846
Test name
Test status
Simulation time 400099942 ps
CPU time 1.63 seconds
Started May 28 01:48:06 PM PDT 24
Finished May 28 01:48:12 PM PDT 24
Peak memory 201716 kb
Host smart-5c4652b5-bbe7-4170-9a3a-b0575b33b273
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565690100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3565690100
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3436337516
Short name T847
Test name
Test status
Simulation time 463472917 ps
CPU time 0.79 seconds
Started May 28 01:48:00 PM PDT 24
Finished May 28 01:48:04 PM PDT 24
Peak memory 201720 kb
Host smart-a28db8a8-bad4-496b-a65e-17679961d68b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436337516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3436337516
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1908350626
Short name T882
Test name
Test status
Simulation time 2204173050 ps
CPU time 5.41 seconds
Started May 28 01:48:06 PM PDT 24
Finished May 28 01:48:17 PM PDT 24
Peak memory 201788 kb
Host smart-f6a6c744-21c4-4b14-ac63-512154e72f8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908350626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1908350626
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3365767171
Short name T888
Test name
Test status
Simulation time 521280329 ps
CPU time 1.56 seconds
Started May 28 01:48:07 PM PDT 24
Finished May 28 01:48:14 PM PDT 24
Peak memory 201948 kb
Host smart-5c452d14-5339-444f-b14f-033b376114a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365767171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3365767171
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2810000942
Short name T909
Test name
Test status
Simulation time 4439890233 ps
CPU time 4.33 seconds
Started May 28 01:48:01 PM PDT 24
Finished May 28 01:48:08 PM PDT 24
Peak memory 201992 kb
Host smart-4b83f0fa-6a12-4d0f-9547-ea5d597a253f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810000942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2810000942
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.216730610
Short name T822
Test name
Test status
Simulation time 540621289 ps
CPU time 1.15 seconds
Started May 28 01:48:03 PM PDT 24
Finished May 28 01:48:08 PM PDT 24
Peak memory 201800 kb
Host smart-5a0f8f84-c747-4a0f-8caa-3296e97a2f73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216730610 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.216730610
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1382921521
Short name T867
Test name
Test status
Simulation time 492375170 ps
CPU time 1.12 seconds
Started May 28 01:48:06 PM PDT 24
Finished May 28 01:48:11 PM PDT 24
Peak memory 201720 kb
Host smart-2e4970f8-2235-4975-8aad-04beaf834b1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382921521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1382921521
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3369006876
Short name T811
Test name
Test status
Simulation time 485157903 ps
CPU time 1.19 seconds
Started May 28 01:48:02 PM PDT 24
Finished May 28 01:48:07 PM PDT 24
Peak memory 201724 kb
Host smart-03fc198a-2d18-4438-8860-03a9a7a2187a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369006876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3369006876
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2385860373
Short name T843
Test name
Test status
Simulation time 2291101743 ps
CPU time 11.1 seconds
Started May 28 01:47:58 PM PDT 24
Finished May 28 01:48:11 PM PDT 24
Peak memory 201816 kb
Host smart-5c285026-fda6-4371-9601-5b711e273f12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385860373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2385860373
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3910763608
Short name T75
Test name
Test status
Simulation time 854552939 ps
CPU time 1.31 seconds
Started May 28 01:48:06 PM PDT 24
Finished May 28 01:48:12 PM PDT 24
Peak memory 202016 kb
Host smart-7c5df1c4-3453-41df-b04f-9daeb976c69d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910763608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3910763608
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1087009668
Short name T66
Test name
Test status
Simulation time 3984514056 ps
CPU time 5.82 seconds
Started May 28 01:48:00 PM PDT 24
Finished May 28 01:48:09 PM PDT 24
Peak memory 201992 kb
Host smart-879ea349-7b47-4c86-870b-272053cbfd2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087009668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1087009668
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.4272386406
Short name T79
Test name
Test status
Simulation time 473054638 ps
CPU time 1.81 seconds
Started May 28 01:47:56 PM PDT 24
Finished May 28 01:48:00 PM PDT 24
Peak memory 201772 kb
Host smart-e5f05211-d56b-4439-a007-31db0e20532b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272386406 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.4272386406
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.735895179
Short name T900
Test name
Test status
Simulation time 393291451 ps
CPU time 0.93 seconds
Started May 28 01:47:58 PM PDT 24
Finished May 28 01:48:00 PM PDT 24
Peak memory 201716 kb
Host smart-d54b8f56-72e6-4508-8911-cffcd2465d86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735895179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.735895179
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1396599274
Short name T868
Test name
Test status
Simulation time 315243570 ps
CPU time 0.98 seconds
Started May 28 01:47:59 PM PDT 24
Finished May 28 01:48:02 PM PDT 24
Peak memory 201696 kb
Host smart-337315d5-1dc9-4fb1-a477-a41726c7964d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396599274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1396599274
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3375624558
Short name T896
Test name
Test status
Simulation time 4299030182 ps
CPU time 3.56 seconds
Started May 28 01:47:57 PM PDT 24
Finished May 28 01:48:03 PM PDT 24
Peak memory 202020 kb
Host smart-53517fc4-47d6-48a5-8bd3-e22295058c88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375624558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3375624558
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2172297144
Short name T72
Test name
Test status
Simulation time 966403530 ps
CPU time 3.08 seconds
Started May 28 01:48:03 PM PDT 24
Finished May 28 01:48:10 PM PDT 24
Peak memory 218024 kb
Host smart-17297cca-eda6-4fa6-94ec-8c429ef73d67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172297144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2172297144
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2981672301
Short name T824
Test name
Test status
Simulation time 348246917 ps
CPU time 1.64 seconds
Started May 28 01:47:50 PM PDT 24
Finished May 28 01:47:53 PM PDT 24
Peak memory 201764 kb
Host smart-83984c0e-abb6-47e5-a04d-5172a96fd4d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981672301 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2981672301
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4047555887
Short name T125
Test name
Test status
Simulation time 376121543 ps
CPU time 1.65 seconds
Started May 28 01:48:00 PM PDT 24
Finished May 28 01:48:05 PM PDT 24
Peak memory 201760 kb
Host smart-98a81848-fc5d-4dd8-8e91-f7b18ea4a180
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047555887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.4047555887
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3218323502
Short name T905
Test name
Test status
Simulation time 316100299 ps
CPU time 0.99 seconds
Started May 28 01:47:50 PM PDT 24
Finished May 28 01:47:53 PM PDT 24
Peak memory 201672 kb
Host smart-cb64c80a-b32d-408f-8535-9557d09eaeea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218323502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3218323502
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2416911916
Short name T853
Test name
Test status
Simulation time 4415273754 ps
CPU time 6.03 seconds
Started May 28 01:48:01 PM PDT 24
Finished May 28 01:48:11 PM PDT 24
Peak memory 201948 kb
Host smart-1dbe2bec-4c9f-4ea4-94cf-3011184940d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416911916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2416911916
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1594076412
Short name T908
Test name
Test status
Simulation time 527334347 ps
CPU time 2.73 seconds
Started May 28 01:47:59 PM PDT 24
Finished May 28 01:48:04 PM PDT 24
Peak memory 201972 kb
Host smart-cb4a8ab4-09ea-4a69-8b55-ae9d6e043ee2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594076412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1594076412
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2553916060
Short name T322
Test name
Test status
Simulation time 7867988024 ps
CPU time 19.85 seconds
Started May 28 01:48:00 PM PDT 24
Finished May 28 01:48:23 PM PDT 24
Peak memory 201964 kb
Host smart-b598e617-a342-4583-ae8b-873bb4531d54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553916060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2553916060
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.937807436
Short name T876
Test name
Test status
Simulation time 495595857 ps
CPU time 1.92 seconds
Started May 28 01:48:02 PM PDT 24
Finished May 28 01:48:07 PM PDT 24
Peak memory 201784 kb
Host smart-51517c65-4b31-4145-b17d-ca28dfee6a22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937807436 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.937807436
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.648879993
Short name T119
Test name
Test status
Simulation time 477617394 ps
CPU time 1.91 seconds
Started May 28 01:47:52 PM PDT 24
Finished May 28 01:47:56 PM PDT 24
Peak memory 201748 kb
Host smart-b684aa02-808c-42b6-afa9-7451e044cac3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648879993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.648879993
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1491335890
Short name T797
Test name
Test status
Simulation time 396961060 ps
CPU time 1.18 seconds
Started May 28 01:47:52 PM PDT 24
Finished May 28 01:47:55 PM PDT 24
Peak memory 201728 kb
Host smart-b39c1ec8-4d61-47d1-8cfc-b1a2cc160637
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491335890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1491335890
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2537621713
Short name T60
Test name
Test status
Simulation time 4629230439 ps
CPU time 10.03 seconds
Started May 28 01:47:56 PM PDT 24
Finished May 28 01:48:08 PM PDT 24
Peak memory 201996 kb
Host smart-daaff0a5-8b4c-4946-b107-4287a5931b90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537621713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2537621713
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4102224887
Short name T914
Test name
Test status
Simulation time 781781647 ps
CPU time 1.9 seconds
Started May 28 01:47:51 PM PDT 24
Finished May 28 01:47:55 PM PDT 24
Peak memory 201976 kb
Host smart-384d54a1-2b23-4f20-b7db-e2a0343ed168
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102224887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.4102224887
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.7107743
Short name T81
Test name
Test status
Simulation time 3992232221 ps
CPU time 3.85 seconds
Started May 28 01:48:00 PM PDT 24
Finished May 28 01:48:08 PM PDT 24
Peak memory 202188 kb
Host smart-09c6a766-47e1-4c41-9e5d-6cac042329e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7107743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_intg
_err.7107743
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1449827506
Short name T907
Test name
Test status
Simulation time 1089552155 ps
CPU time 4.39 seconds
Started May 28 01:47:30 PM PDT 24
Finished May 28 01:47:36 PM PDT 24
Peak memory 201948 kb
Host smart-ada93c35-2e73-464b-86f2-c4b7ccd29188
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449827506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1449827506
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1476530162
Short name T116
Test name
Test status
Simulation time 1253377598 ps
CPU time 3.6 seconds
Started May 28 01:47:34 PM PDT 24
Finished May 28 01:47:42 PM PDT 24
Peak memory 201736 kb
Host smart-4ed1d426-57fd-4233-9688-2d6b36acda14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476530162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1476530162
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1292682541
Short name T891
Test name
Test status
Simulation time 757701076 ps
CPU time 0.91 seconds
Started May 28 01:47:35 PM PDT 24
Finished May 28 01:47:40 PM PDT 24
Peak memory 201804 kb
Host smart-097f8e6d-a361-4999-b23d-172e155f76aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292682541 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1292682541
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.766992813
Short name T115
Test name
Test status
Simulation time 527583794 ps
CPU time 2.04 seconds
Started May 28 01:47:31 PM PDT 24
Finished May 28 01:47:36 PM PDT 24
Peak memory 201948 kb
Host smart-74348d17-80ff-456e-ad55-4c1cfb85dd69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766992813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.766992813
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1380911656
Short name T836
Test name
Test status
Simulation time 449282293 ps
CPU time 1.75 seconds
Started May 28 01:47:35 PM PDT 24
Finished May 28 01:47:41 PM PDT 24
Peak memory 201736 kb
Host smart-5ab0708b-a8cc-47bf-90d0-9d4fed6aa780
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380911656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1380911656
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.398733004
Short name T866
Test name
Test status
Simulation time 5302688282 ps
CPU time 22.22 seconds
Started May 28 01:47:37 PM PDT 24
Finished May 28 01:48:03 PM PDT 24
Peak memory 201908 kb
Host smart-731d2901-8dc0-4df1-8b63-e463724ca2cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398733004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.398733004
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2389308759
Short name T904
Test name
Test status
Simulation time 491521919 ps
CPU time 3.33 seconds
Started May 28 01:47:37 PM PDT 24
Finished May 28 01:47:44 PM PDT 24
Peak memory 201924 kb
Host smart-ec260fdd-058f-4af6-9b32-b728d36daa5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389308759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2389308759
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3484695194
Short name T849
Test name
Test status
Simulation time 4296149756 ps
CPU time 3.91 seconds
Started May 28 01:47:35 PM PDT 24
Finished May 28 01:47:43 PM PDT 24
Peak memory 202040 kb
Host smart-03535da3-1782-4459-961e-8dadc67039fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484695194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3484695194
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.4209502446
Short name T865
Test name
Test status
Simulation time 335784199 ps
CPU time 0.87 seconds
Started May 28 01:48:00 PM PDT 24
Finished May 28 01:48:04 PM PDT 24
Peak memory 201696 kb
Host smart-0844245b-a7b3-44fa-aca6-8464deea4089
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209502446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.4209502446
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3510803960
Short name T859
Test name
Test status
Simulation time 500706820 ps
CPU time 1.78 seconds
Started May 28 01:47:58 PM PDT 24
Finished May 28 01:48:01 PM PDT 24
Peak memory 201680 kb
Host smart-18a453e6-1a35-46b6-bd6e-b551eee246da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510803960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3510803960
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2308377335
Short name T874
Test name
Test status
Simulation time 401278133 ps
CPU time 0.93 seconds
Started May 28 01:48:00 PM PDT 24
Finished May 28 01:48:04 PM PDT 24
Peak memory 201656 kb
Host smart-09f1740a-249d-4612-a616-1aa9a34e6468
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308377335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2308377335
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3111036876
Short name T801
Test name
Test status
Simulation time 506335612 ps
CPU time 1.26 seconds
Started May 28 01:47:56 PM PDT 24
Finished May 28 01:47:59 PM PDT 24
Peak memory 201704 kb
Host smart-772faf03-14d0-4bf3-b341-933080ee1cef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111036876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3111036876
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2434060930
Short name T805
Test name
Test status
Simulation time 466499762 ps
CPU time 1.85 seconds
Started May 28 01:48:00 PM PDT 24
Finished May 28 01:48:05 PM PDT 24
Peak memory 201644 kb
Host smart-8d94ed99-9e66-45cd-aef4-819f4501bb44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434060930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2434060930
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1077804554
Short name T870
Test name
Test status
Simulation time 528850958 ps
CPU time 1.05 seconds
Started May 28 01:48:06 PM PDT 24
Finished May 28 01:48:13 PM PDT 24
Peak memory 201724 kb
Host smart-0d5975a8-21f9-41fe-9084-c07955268e81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077804554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1077804554
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3150492152
Short name T808
Test name
Test status
Simulation time 432718765 ps
CPU time 1.72 seconds
Started May 28 01:48:09 PM PDT 24
Finished May 28 01:48:18 PM PDT 24
Peak memory 201716 kb
Host smart-5e2f94ab-b267-4daa-b85d-6d17987f0204
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150492152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3150492152
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3915883401
Short name T860
Test name
Test status
Simulation time 497207288 ps
CPU time 0.85 seconds
Started May 28 01:48:10 PM PDT 24
Finished May 28 01:48:18 PM PDT 24
Peak memory 201732 kb
Host smart-a1416801-6e42-4a31-9dea-7b987aad86d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915883401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3915883401
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2677910800
Short name T841
Test name
Test status
Simulation time 291102296 ps
CPU time 1.31 seconds
Started May 28 01:48:07 PM PDT 24
Finished May 28 01:48:13 PM PDT 24
Peak memory 201724 kb
Host smart-4f763aaf-dbff-489d-83cc-3ff9b83c9fc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677910800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2677910800
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.367734238
Short name T834
Test name
Test status
Simulation time 495716143 ps
CPU time 1.67 seconds
Started May 28 01:48:06 PM PDT 24
Finished May 28 01:48:13 PM PDT 24
Peak memory 201728 kb
Host smart-2931b2d0-7451-4daf-aedd-a8b4c9a761e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367734238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.367734238
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2820306700
Short name T885
Test name
Test status
Simulation time 1015939504 ps
CPU time 1.85 seconds
Started May 28 01:47:57 PM PDT 24
Finished May 28 01:48:01 PM PDT 24
Peak memory 201912 kb
Host smart-b6e7b8c8-c106-4843-8525-808d969be61c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820306700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2820306700
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3636240463
Short name T122
Test name
Test status
Simulation time 42494247525 ps
CPU time 93.96 seconds
Started May 28 01:47:57 PM PDT 24
Finished May 28 01:49:33 PM PDT 24
Peak memory 201960 kb
Host smart-350a2d35-202e-4b52-bfa7-7082f9a53508
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636240463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3636240463
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1777134147
Short name T113
Test name
Test status
Simulation time 1266952209 ps
CPU time 1.5 seconds
Started May 28 01:47:49 PM PDT 24
Finished May 28 01:47:52 PM PDT 24
Peak memory 201728 kb
Host smart-e75b0a48-dbe5-4ca8-9a4e-d8e085b45a19
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777134147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1777134147
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3073965020
Short name T827
Test name
Test status
Simulation time 667753004 ps
CPU time 1.32 seconds
Started May 28 01:47:51 PM PDT 24
Finished May 28 01:47:54 PM PDT 24
Peak memory 201800 kb
Host smart-f8350a58-3118-43a8-ba7a-06c4b2085bd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073965020 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3073965020
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1310557401
Short name T821
Test name
Test status
Simulation time 682201491 ps
CPU time 0.88 seconds
Started May 28 01:47:46 PM PDT 24
Finished May 28 01:47:47 PM PDT 24
Peak memory 201740 kb
Host smart-9cc85b84-7973-4551-809e-9893ab2c71bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310557401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1310557401
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2978663179
Short name T806
Test name
Test status
Simulation time 381053988 ps
CPU time 0.87 seconds
Started May 28 01:47:31 PM PDT 24
Finished May 28 01:47:34 PM PDT 24
Peak memory 201696 kb
Host smart-8d2ad818-e690-4d5f-95b4-b0c422f3fc36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978663179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2978663179
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1140682481
Short name T842
Test name
Test status
Simulation time 4813555595 ps
CPU time 6.46 seconds
Started May 28 01:47:48 PM PDT 24
Finished May 28 01:47:56 PM PDT 24
Peak memory 201988 kb
Host smart-e7b06ca1-d8ce-44d3-9fa3-a1e27a6e02b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140682481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1140682481
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.583097621
Short name T74
Test name
Test status
Simulation time 522658085 ps
CPU time 3.01 seconds
Started May 28 01:47:36 PM PDT 24
Finished May 28 01:47:43 PM PDT 24
Peak memory 211192 kb
Host smart-f288552d-a6d0-478e-9064-29116e6a33b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583097621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.583097621
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2931635383
Short name T916
Test name
Test status
Simulation time 8054574206 ps
CPU time 20.32 seconds
Started May 28 01:47:37 PM PDT 24
Finished May 28 01:48:01 PM PDT 24
Peak memory 201928 kb
Host smart-c5bae759-0ac8-4960-a894-9b33fdc50bbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931635383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.2931635383
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1713943082
Short name T800
Test name
Test status
Simulation time 319113843 ps
CPU time 1.42 seconds
Started May 28 01:48:10 PM PDT 24
Finished May 28 01:48:19 PM PDT 24
Peak memory 201732 kb
Host smart-0cf359d1-3b7d-4148-87e1-7356920799f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713943082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1713943082
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1272026184
Short name T844
Test name
Test status
Simulation time 494017037 ps
CPU time 1.89 seconds
Started May 28 01:48:10 PM PDT 24
Finished May 28 01:48:19 PM PDT 24
Peak memory 201716 kb
Host smart-da87e7ff-de61-4247-88ef-e2a36c6807d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272026184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1272026184
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3068947452
Short name T913
Test name
Test status
Simulation time 528677792 ps
CPU time 1 seconds
Started May 28 01:48:05 PM PDT 24
Finished May 28 01:48:10 PM PDT 24
Peak memory 201716 kb
Host smart-2fef098f-46d3-4091-8ff3-671e69a08f1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068947452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3068947452
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1328396406
Short name T819
Test name
Test status
Simulation time 429504255 ps
CPU time 1.64 seconds
Started May 28 01:48:05 PM PDT 24
Finished May 28 01:48:11 PM PDT 24
Peak memory 201740 kb
Host smart-a73e1454-8eb4-4496-898d-658ac375b232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328396406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1328396406
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3823417873
Short name T851
Test name
Test status
Simulation time 348403277 ps
CPU time 0.76 seconds
Started May 28 01:48:10 PM PDT 24
Finished May 28 01:48:18 PM PDT 24
Peak memory 201740 kb
Host smart-6a6a9fdd-16ca-4ed3-a839-31326e71f8bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823417873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3823417873
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.522349616
Short name T802
Test name
Test status
Simulation time 329124968 ps
CPU time 0.73 seconds
Started May 28 01:48:06 PM PDT 24
Finished May 28 01:48:12 PM PDT 24
Peak memory 201740 kb
Host smart-aa378773-9e49-4fb9-a7e5-b16aaf41ad02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522349616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.522349616
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1128164976
Short name T890
Test name
Test status
Simulation time 360308030 ps
CPU time 1.09 seconds
Started May 28 01:48:06 PM PDT 24
Finished May 28 01:48:13 PM PDT 24
Peak memory 201704 kb
Host smart-42903a9e-b821-4e82-b302-7c40953bce45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128164976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1128164976
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2764775726
Short name T809
Test name
Test status
Simulation time 452074376 ps
CPU time 1.12 seconds
Started May 28 01:48:06 PM PDT 24
Finished May 28 01:48:12 PM PDT 24
Peak memory 201724 kb
Host smart-85f9c4ec-2fec-4f9e-a95f-6a650402996b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764775726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2764775726
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3782590642
Short name T799
Test name
Test status
Simulation time 362688842 ps
CPU time 0.85 seconds
Started May 28 01:48:06 PM PDT 24
Finished May 28 01:48:13 PM PDT 24
Peak memory 201716 kb
Host smart-35be5035-afc6-4de1-8f34-bbafdfacde86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782590642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3782590642
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3253800801
Short name T820
Test name
Test status
Simulation time 510150913 ps
CPU time 1.19 seconds
Started May 28 01:48:09 PM PDT 24
Finished May 28 01:48:17 PM PDT 24
Peak memory 201724 kb
Host smart-f1a357b5-0e2e-4e93-a108-b9f822c1fb80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253800801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3253800801
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.4126900026
Short name T126
Test name
Test status
Simulation time 1241837268 ps
CPU time 2.51 seconds
Started May 28 01:47:51 PM PDT 24
Finished May 28 01:47:55 PM PDT 24
Peak memory 201920 kb
Host smart-9e65610d-f861-4b2d-993f-35cf33be77a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126900026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.4126900026
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2236548752
Short name T123
Test name
Test status
Simulation time 14144659867 ps
CPU time 12.13 seconds
Started May 28 01:47:47 PM PDT 24
Finished May 28 01:48:00 PM PDT 24
Peak memory 202020 kb
Host smart-29f935fd-8f93-4421-a386-f07156c52fd3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236548752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2236548752
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.582613070
Short name T830
Test name
Test status
Simulation time 720172424 ps
CPU time 2.37 seconds
Started May 28 01:47:54 PM PDT 24
Finished May 28 01:47:58 PM PDT 24
Peak memory 201740 kb
Host smart-438965a8-527a-4aad-a9aa-0bc71d8a1d80
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582613070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re
set.582613070
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1442787245
Short name T93
Test name
Test status
Simulation time 506177635 ps
CPU time 1.3 seconds
Started May 28 01:47:55 PM PDT 24
Finished May 28 01:47:58 PM PDT 24
Peak memory 201780 kb
Host smart-597f5109-9847-424b-be49-e9fb2f2cc0a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442787245 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1442787245
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3651885833
Short name T129
Test name
Test status
Simulation time 397535271 ps
CPU time 0.94 seconds
Started May 28 01:47:56 PM PDT 24
Finished May 28 01:47:58 PM PDT 24
Peak memory 201712 kb
Host smart-38fcc5b7-5636-4236-a100-40f63ceede79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651885833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3651885833
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2964650101
Short name T862
Test name
Test status
Simulation time 458855310 ps
CPU time 1.14 seconds
Started May 28 01:48:01 PM PDT 24
Finished May 28 01:48:06 PM PDT 24
Peak memory 201636 kb
Host smart-99f26bf2-c198-41e3-befb-d692395252fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964650101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2964650101
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.4166597587
Short name T869
Test name
Test status
Simulation time 5153848649 ps
CPU time 14.01 seconds
Started May 28 01:47:54 PM PDT 24
Finished May 28 01:48:09 PM PDT 24
Peak memory 201992 kb
Host smart-6820bfbf-c175-43a9-bdf5-a41eb7492cdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166597587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.4166597587
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.850661734
Short name T919
Test name
Test status
Simulation time 605135384 ps
CPU time 3.71 seconds
Started May 28 01:47:50 PM PDT 24
Finished May 28 01:47:55 PM PDT 24
Peak memory 217888 kb
Host smart-151ee3a7-4094-42a0-84af-9aa622adb1ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850661734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.850661734
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3791194850
Short name T879
Test name
Test status
Simulation time 3955890487 ps
CPU time 11.39 seconds
Started May 28 01:48:01 PM PDT 24
Finished May 28 01:48:16 PM PDT 24
Peak memory 201628 kb
Host smart-b89a0efb-a217-4209-bb6c-a9a0f5579420
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791194850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3791194850
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3369215442
Short name T835
Test name
Test status
Simulation time 519604927 ps
CPU time 0.94 seconds
Started May 28 01:48:11 PM PDT 24
Finished May 28 01:48:19 PM PDT 24
Peak memory 201712 kb
Host smart-fc058454-b530-4eb4-a6a0-29ae323f5d29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369215442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3369215442
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.4025762205
Short name T902
Test name
Test status
Simulation time 330638323 ps
CPU time 0.69 seconds
Started May 28 01:48:09 PM PDT 24
Finished May 28 01:48:17 PM PDT 24
Peak memory 201732 kb
Host smart-7b4dff76-ef66-43fc-bc05-cf8dcefc6196
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025762205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.4025762205
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.565698239
Short name T818
Test name
Test status
Simulation time 496254796 ps
CPU time 1.71 seconds
Started May 28 01:48:10 PM PDT 24
Finished May 28 01:48:20 PM PDT 24
Peak memory 201748 kb
Host smart-d9815cba-8516-4ef9-be78-2236b0547494
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565698239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.565698239
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1689891436
Short name T798
Test name
Test status
Simulation time 324000026 ps
CPU time 0.95 seconds
Started May 28 01:48:06 PM PDT 24
Finished May 28 01:48:12 PM PDT 24
Peak memory 201732 kb
Host smart-0889268f-f965-4810-bf37-886e8be74b62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689891436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1689891436
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.785639021
Short name T812
Test name
Test status
Simulation time 508163429 ps
CPU time 1.9 seconds
Started May 28 01:48:06 PM PDT 24
Finished May 28 01:48:14 PM PDT 24
Peak memory 201740 kb
Host smart-9e48ef5d-43fd-4c7f-9413-f29a3a0ed557
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785639021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.785639021
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.967105964
Short name T816
Test name
Test status
Simulation time 449621559 ps
CPU time 0.89 seconds
Started May 28 01:48:07 PM PDT 24
Finished May 28 01:48:13 PM PDT 24
Peak memory 201740 kb
Host smart-ccd54437-d879-4501-a3f8-59da71aae421
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967105964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.967105964
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1377940633
Short name T796
Test name
Test status
Simulation time 374683681 ps
CPU time 0.83 seconds
Started May 28 01:48:05 PM PDT 24
Finished May 28 01:48:10 PM PDT 24
Peak memory 201728 kb
Host smart-02308cbc-da4d-49da-84ab-839d009e7c74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377940633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1377940633
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3720589480
Short name T810
Test name
Test status
Simulation time 515925969 ps
CPU time 1.34 seconds
Started May 28 01:48:09 PM PDT 24
Finished May 28 01:48:18 PM PDT 24
Peak memory 201724 kb
Host smart-b8bae8af-6f3c-42dc-8d25-e2791a86eb28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720589480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3720589480
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2915250380
Short name T871
Test name
Test status
Simulation time 517825260 ps
CPU time 0.93 seconds
Started May 28 01:48:11 PM PDT 24
Finished May 28 01:48:20 PM PDT 24
Peak memory 201732 kb
Host smart-34a237e8-c0a6-4633-a72c-976f7e8975ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915250380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2915250380
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2620929054
Short name T826
Test name
Test status
Simulation time 448709765 ps
CPU time 1.17 seconds
Started May 28 01:48:07 PM PDT 24
Finished May 28 01:48:13 PM PDT 24
Peak memory 201728 kb
Host smart-58d6b4e8-42c4-4552-907e-e83ad3d2d6a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620929054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2620929054
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1017035469
Short name T817
Test name
Test status
Simulation time 577132209 ps
CPU time 2.2 seconds
Started May 28 01:47:58 PM PDT 24
Finished May 28 01:48:02 PM PDT 24
Peak memory 201832 kb
Host smart-ee45a0ef-c8b2-4d11-8c72-c29202aa4441
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017035469 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1017035469
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2854118784
Short name T884
Test name
Test status
Simulation time 553785000 ps
CPU time 1 seconds
Started May 28 01:47:58 PM PDT 24
Finished May 28 01:48:01 PM PDT 24
Peak memory 201664 kb
Host smart-5d040293-a3ba-4702-a682-1a986fd7e196
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854118784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2854118784
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3000408645
Short name T863
Test name
Test status
Simulation time 381213719 ps
CPU time 1.51 seconds
Started May 28 01:48:00 PM PDT 24
Finished May 28 01:48:04 PM PDT 24
Peak memory 201676 kb
Host smart-8affb7cf-029d-4697-b214-c8842c02fb22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000408645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3000408645
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3326232906
Short name T889
Test name
Test status
Simulation time 4247826197 ps
CPU time 6.1 seconds
Started May 28 01:47:50 PM PDT 24
Finished May 28 01:47:58 PM PDT 24
Peak memory 201976 kb
Host smart-c501c10c-3091-4b30-8929-41a51dfc687c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326232906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3326232906
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2294228049
Short name T856
Test name
Test status
Simulation time 662719089 ps
CPU time 2.12 seconds
Started May 28 01:47:54 PM PDT 24
Finished May 28 01:47:58 PM PDT 24
Peak memory 211224 kb
Host smart-8195340b-1215-41f6-afc7-b900f4f81ef2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294228049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.2294228049
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2333053763
Short name T828
Test name
Test status
Simulation time 8071261619 ps
CPU time 20.18 seconds
Started May 28 01:47:49 PM PDT 24
Finished May 28 01:48:10 PM PDT 24
Peak memory 201992 kb
Host smart-859a3453-91ae-45b6-8ea6-3936c6d5c6ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333053763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2333053763
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2414102041
Short name T915
Test name
Test status
Simulation time 512610261 ps
CPU time 1.35 seconds
Started May 28 01:47:48 PM PDT 24
Finished May 28 01:47:51 PM PDT 24
Peak memory 201772 kb
Host smart-5addd0aa-e30d-4237-9d94-f79ed4ae1ebd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414102041 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2414102041
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3155623901
Short name T124
Test name
Test status
Simulation time 385666906 ps
CPU time 1.2 seconds
Started May 28 01:47:48 PM PDT 24
Finished May 28 01:47:51 PM PDT 24
Peak memory 201740 kb
Host smart-4bd8bd8b-9a02-432a-9e54-177cae687f62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155623901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3155623901
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2620924276
Short name T877
Test name
Test status
Simulation time 380979835 ps
CPU time 0.69 seconds
Started May 28 01:47:47 PM PDT 24
Finished May 28 01:47:49 PM PDT 24
Peak memory 201648 kb
Host smart-6f7be8e0-2a83-46ab-9e70-b99a42a46d7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620924276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2620924276
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.4193367602
Short name T912
Test name
Test status
Simulation time 4980942553 ps
CPU time 20.01 seconds
Started May 28 01:47:59 PM PDT 24
Finished May 28 01:48:21 PM PDT 24
Peak memory 202016 kb
Host smart-b6dac05c-9716-444a-b08a-fcfa388732b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193367602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.4193367602
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.4082505417
Short name T68
Test name
Test status
Simulation time 356616458 ps
CPU time 2.36 seconds
Started May 28 01:48:01 PM PDT 24
Finished May 28 01:48:07 PM PDT 24
Peak memory 201836 kb
Host smart-089041f5-adbc-41c0-a27c-3dfa26b29acf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082505417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.4082505417
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3967937441
Short name T324
Test name
Test status
Simulation time 8426184487 ps
CPU time 4.73 seconds
Started May 28 01:48:01 PM PDT 24
Finished May 28 01:48:10 PM PDT 24
Peak memory 202180 kb
Host smart-bb01ac5b-7456-4a59-b029-1d5ed71a6bbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967937441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3967937441
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.350492440
Short name T857
Test name
Test status
Simulation time 514364660 ps
CPU time 1.16 seconds
Started May 28 01:47:56 PM PDT 24
Finished May 28 01:47:59 PM PDT 24
Peak memory 201796 kb
Host smart-9bee6720-649a-43ad-bc4b-46f11076c19b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350492440 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.350492440
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1237672438
Short name T901
Test name
Test status
Simulation time 358353811 ps
CPU time 0.91 seconds
Started May 28 01:47:48 PM PDT 24
Finished May 28 01:47:50 PM PDT 24
Peak memory 201740 kb
Host smart-7a58e15a-67b7-4a08-bc06-126c256f0b8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237672438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1237672438
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1391047608
Short name T804
Test name
Test status
Simulation time 329099012 ps
CPU time 0.82 seconds
Started May 28 01:48:00 PM PDT 24
Finished May 28 01:48:04 PM PDT 24
Peak memory 201688 kb
Host smart-1eb73774-a145-4324-849d-e5644da90973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391047608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1391047608
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.976535907
Short name T918
Test name
Test status
Simulation time 2530259197 ps
CPU time 2.28 seconds
Started May 28 01:47:55 PM PDT 24
Finished May 28 01:47:59 PM PDT 24
Peak memory 201772 kb
Host smart-ba9e3acc-366f-428f-976d-398ef5c37cad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976535907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.976535907
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3043974598
Short name T840
Test name
Test status
Simulation time 341117697 ps
CPU time 1.99 seconds
Started May 28 01:47:58 PM PDT 24
Finished May 28 01:48:02 PM PDT 24
Peak memory 202032 kb
Host smart-0cc96172-d24c-48a6-9b72-745545cae61e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043974598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3043974598
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2717866698
Short name T886
Test name
Test status
Simulation time 8377496898 ps
CPU time 23.51 seconds
Started May 28 01:47:50 PM PDT 24
Finished May 28 01:48:16 PM PDT 24
Peak memory 202036 kb
Host smart-8deee281-26d7-448c-b09d-af2ede5c87c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717866698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2717866698
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2731248302
Short name T864
Test name
Test status
Simulation time 633356654 ps
CPU time 1.17 seconds
Started May 28 01:47:49 PM PDT 24
Finished May 28 01:47:51 PM PDT 24
Peak memory 201792 kb
Host smart-8ef7e46e-061f-4eb6-adb3-6c60eae0c14c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731248302 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2731248302
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2625814070
Short name T127
Test name
Test status
Simulation time 320317491 ps
CPU time 1.38 seconds
Started May 28 01:47:58 PM PDT 24
Finished May 28 01:48:01 PM PDT 24
Peak memory 201664 kb
Host smart-c2e5ee44-af03-4bee-bcd7-d92b295edf13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625814070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2625814070
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.741809711
Short name T807
Test name
Test status
Simulation time 380577943 ps
CPU time 1.07 seconds
Started May 28 01:48:00 PM PDT 24
Finished May 28 01:48:03 PM PDT 24
Peak memory 201724 kb
Host smart-9c7a712f-7ed2-48ef-81f8-e9d286705bf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741809711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.741809711
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3259812507
Short name T875
Test name
Test status
Simulation time 2248993308 ps
CPU time 2.61 seconds
Started May 28 01:47:56 PM PDT 24
Finished May 28 01:48:00 PM PDT 24
Peak memory 201772 kb
Host smart-b9b888fd-0e09-4f69-9f22-bc7cc79a4505
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259812507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3259812507
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.29774301
Short name T852
Test name
Test status
Simulation time 606556986 ps
CPU time 2.88 seconds
Started May 28 01:47:47 PM PDT 24
Finished May 28 01:47:51 PM PDT 24
Peak memory 210188 kb
Host smart-a958d6f0-68fc-4276-bcc9-05280bfffe8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29774301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.29774301
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1673334835
Short name T861
Test name
Test status
Simulation time 4525301295 ps
CPU time 4.38 seconds
Started May 28 01:47:56 PM PDT 24
Finished May 28 01:48:02 PM PDT 24
Peak memory 201964 kb
Host smart-bd472477-d131-48fd-9456-71b2fd10bd43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673334835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1673334835
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.794393311
Short name T893
Test name
Test status
Simulation time 760765959 ps
CPU time 1.2 seconds
Started May 28 01:47:59 PM PDT 24
Finished May 28 01:48:02 PM PDT 24
Peak memory 201760 kb
Host smart-2b647b8f-193a-4df2-8ea3-6987d0093f44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794393311 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.794393311
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1651568477
Short name T121
Test name
Test status
Simulation time 551466867 ps
CPU time 1.28 seconds
Started May 28 01:47:51 PM PDT 24
Finished May 28 01:47:54 PM PDT 24
Peak memory 201656 kb
Host smart-7f6dd4fb-a746-4d78-99bb-25bff2fbeb21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651568477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1651568477
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2319623969
Short name T815
Test name
Test status
Simulation time 323571479 ps
CPU time 1.41 seconds
Started May 28 01:47:51 PM PDT 24
Finished May 28 01:47:55 PM PDT 24
Peak memory 201652 kb
Host smart-8132fe3d-1bcd-43d1-9c94-9c171ddefbe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319623969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2319623969
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2855712688
Short name T61
Test name
Test status
Simulation time 4413735510 ps
CPU time 9.76 seconds
Started May 28 01:48:03 PM PDT 24
Finished May 28 01:48:17 PM PDT 24
Peak memory 201992 kb
Host smart-085f4cf6-141b-464a-9b2e-390761ddbf6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855712688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2855712688
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3242499719
Short name T910
Test name
Test status
Simulation time 1490909554 ps
CPU time 2.96 seconds
Started May 28 01:48:01 PM PDT 24
Finished May 28 01:48:08 PM PDT 24
Peak memory 209728 kb
Host smart-1ed3eadd-933a-436b-89f9-704857f3fc8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242499719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3242499719
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3804736267
Short name T845
Test name
Test status
Simulation time 4760200542 ps
CPU time 4.12 seconds
Started May 28 01:47:50 PM PDT 24
Finished May 28 01:47:56 PM PDT 24
Peak memory 201960 kb
Host smart-3512406f-4935-46c1-b0ff-0912f89c1e86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804736267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3804736267
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.3654425112
Short name T608
Test name
Test status
Simulation time 375485048 ps
CPU time 0.83 seconds
Started May 28 02:19:46 PM PDT 24
Finished May 28 02:19:49 PM PDT 24
Peak memory 201512 kb
Host smart-c4b6c566-2727-4b71-b1aa-5a1eefa5ae9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654425112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3654425112
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1239031742
Short name T788
Test name
Test status
Simulation time 544982186925 ps
CPU time 345.24 seconds
Started May 28 02:19:37 PM PDT 24
Finished May 28 02:25:23 PM PDT 24
Peak memory 201884 kb
Host smart-21ff9643-10ee-4cf7-a254-b4185fdac491
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239031742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1239031742
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.236213623
Short name T455
Test name
Test status
Simulation time 161885905555 ps
CPU time 88.39 seconds
Started May 28 02:19:36 PM PDT 24
Finished May 28 02:21:06 PM PDT 24
Peak memory 201840 kb
Host smart-8f99d827-790e-4e76-91b0-60683b1f5a5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=236213623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.236213623
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2437926577
Short name T501
Test name
Test status
Simulation time 165233265333 ps
CPU time 89.49 seconds
Started May 28 02:19:39 PM PDT 24
Finished May 28 02:21:10 PM PDT 24
Peak memory 201828 kb
Host smart-c7d27031-7904-43b3-9033-228e15cb8a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437926577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2437926577
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.393620057
Short name T43
Test name
Test status
Simulation time 491677532002 ps
CPU time 584.01 seconds
Started May 28 02:19:35 PM PDT 24
Finished May 28 02:29:20 PM PDT 24
Peak memory 201860 kb
Host smart-11713040-54a9-4ab7-b16c-4ae4ab5ac5bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=393620057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed
.393620057
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.123328806
Short name T204
Test name
Test status
Simulation time 341654580349 ps
CPU time 725.23 seconds
Started May 28 02:19:38 PM PDT 24
Finished May 28 02:31:45 PM PDT 24
Peak memory 201864 kb
Host smart-c7759247-34ed-4390-8acb-c4e57a7f6c44
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123328806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.123328806
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2845289846
Short name T409
Test name
Test status
Simulation time 595079859278 ps
CPU time 118.79 seconds
Started May 28 02:19:37 PM PDT 24
Finished May 28 02:21:37 PM PDT 24
Peak memory 201908 kb
Host smart-27a511f2-7c54-4ef3-8b17-97a093248765
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845289846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2845289846
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.221148454
Short name T790
Test name
Test status
Simulation time 125308762160 ps
CPU time 628.29 seconds
Started May 28 02:19:48 PM PDT 24
Finished May 28 02:30:18 PM PDT 24
Peak memory 202168 kb
Host smart-58562202-75fe-44ac-b57b-babb4314adf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221148454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.221148454
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2930953898
Short name T417
Test name
Test status
Simulation time 26593966764 ps
CPU time 29.05 seconds
Started May 28 02:19:47 PM PDT 24
Finished May 28 02:20:18 PM PDT 24
Peak memory 201668 kb
Host smart-2ab0c455-bd84-4429-8cbb-39d274309b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930953898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2930953898
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.568851904
Short name T705
Test name
Test status
Simulation time 2935732286 ps
CPU time 8.05 seconds
Started May 28 02:19:38 PM PDT 24
Finished May 28 02:19:48 PM PDT 24
Peak memory 201588 kb
Host smart-30b7c2c3-f30a-448d-b4ba-cd8d7a7afecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568851904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.568851904
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.819139171
Short name T549
Test name
Test status
Simulation time 5957756297 ps
CPU time 7.99 seconds
Started May 28 02:19:38 PM PDT 24
Finished May 28 02:19:47 PM PDT 24
Peak memory 201484 kb
Host smart-781427a8-7f39-4c99-9a9f-e13e0b406d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819139171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.819139171
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2240186139
Short name T722
Test name
Test status
Simulation time 46719962318 ps
CPU time 104.94 seconds
Started May 28 02:19:47 PM PDT 24
Finished May 28 02:21:34 PM PDT 24
Peak memory 213132 kb
Host smart-796f0db8-c6aa-4641-be67-93986f1b7255
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240186139 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2240186139
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2209269377
Short name T444
Test name
Test status
Simulation time 394507685 ps
CPU time 0.9 seconds
Started May 28 02:19:47 PM PDT 24
Finished May 28 02:19:49 PM PDT 24
Peak memory 201536 kb
Host smart-76f67f59-f338-451b-a9b2-0cb9ee74d4a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209269377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2209269377
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.3099874265
Short name T263
Test name
Test status
Simulation time 349881897238 ps
CPU time 507.16 seconds
Started May 28 02:19:48 PM PDT 24
Finished May 28 02:28:17 PM PDT 24
Peak memory 201848 kb
Host smart-dd620d21-f17e-4afc-b5c3-6b1bf3bd494b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099874265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.3099874265
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2240375921
Short name T167
Test name
Test status
Simulation time 163414672378 ps
CPU time 392.3 seconds
Started May 28 02:19:49 PM PDT 24
Finished May 28 02:26:23 PM PDT 24
Peak memory 201740 kb
Host smart-d98454d8-9229-4182-822e-d0c5352c0ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240375921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2240375921
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.196454263
Short name T139
Test name
Test status
Simulation time 329618779116 ps
CPU time 121.41 seconds
Started May 28 02:19:50 PM PDT 24
Finished May 28 02:21:53 PM PDT 24
Peak memory 202096 kb
Host smart-19e03244-8fbe-4886-945b-137dd33bc644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196454263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.196454263
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2207922105
Short name T689
Test name
Test status
Simulation time 161364666060 ps
CPU time 370.38 seconds
Started May 28 02:19:46 PM PDT 24
Finished May 28 02:25:58 PM PDT 24
Peak memory 201836 kb
Host smart-01f1a3c0-0135-4afb-af94-b9bb388ceaab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207922105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2207922105
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1431080154
Short name T341
Test name
Test status
Simulation time 619191633220 ps
CPU time 379.55 seconds
Started May 28 02:19:50 PM PDT 24
Finished May 28 02:26:11 PM PDT 24
Peak memory 201920 kb
Host smart-00902e87-fa1a-4ceb-ba3d-844b4c46969f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431080154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1431080154
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2272419240
Short name T27
Test name
Test status
Simulation time 94800852712 ps
CPU time 418.94 seconds
Started May 28 02:19:47 PM PDT 24
Finished May 28 02:26:48 PM PDT 24
Peak memory 202236 kb
Host smart-f95a5cb5-cf5e-4c1e-a4a5-c430f5d85eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272419240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2272419240
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2247700785
Short name T725
Test name
Test status
Simulation time 35319353878 ps
CPU time 20.82 seconds
Started May 28 02:19:47 PM PDT 24
Finished May 28 02:20:09 PM PDT 24
Peak memory 201668 kb
Host smart-91ddb755-a5c7-4fe2-85b6-a9978792986e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247700785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2247700785
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3495909321
Short name T602
Test name
Test status
Simulation time 3722238784 ps
CPU time 3.83 seconds
Started May 28 02:19:48 PM PDT 24
Finished May 28 02:19:53 PM PDT 24
Peak memory 201580 kb
Host smart-3f21656e-89aa-4031-b284-1c8511b7e40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495909321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3495909321
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.4176129176
Short name T83
Test name
Test status
Simulation time 8264432506 ps
CPU time 5.84 seconds
Started May 28 02:19:48 PM PDT 24
Finished May 28 02:19:56 PM PDT 24
Peak memory 218460 kb
Host smart-eac46f6e-e21d-4ee7-a0ab-c3c017b991ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176129176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.4176129176
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3716963257
Short name T568
Test name
Test status
Simulation time 5630526627 ps
CPU time 5.95 seconds
Started May 28 02:19:47 PM PDT 24
Finished May 28 02:19:54 PM PDT 24
Peak memory 201656 kb
Host smart-abe088d3-34f1-4212-a8c5-f9d9806f2dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716963257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3716963257
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.4053679636
Short name T163
Test name
Test status
Simulation time 309174882889 ps
CPU time 542.72 seconds
Started May 28 02:19:48 PM PDT 24
Finished May 28 02:28:52 PM PDT 24
Peak memory 212292 kb
Host smart-6c5c717a-d86a-40e2-a72c-bfd93c0cb65f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053679636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
4053679636
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.972428829
Short name T506
Test name
Test status
Simulation time 484570013 ps
CPU time 1.69 seconds
Started May 28 02:21:34 PM PDT 24
Finished May 28 02:21:36 PM PDT 24
Peak memory 201532 kb
Host smart-517d69c0-0015-46e1-88d2-c25fc951f47f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972428829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.972428829
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.425987074
Short name T150
Test name
Test status
Simulation time 365694888172 ps
CPU time 889.91 seconds
Started May 28 02:21:26 PM PDT 24
Finished May 28 02:36:17 PM PDT 24
Peak memory 201916 kb
Host smart-39b5f1bd-fb38-4632-a950-559fd84ce3cc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425987074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gati
ng.425987074
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1394298826
Short name T270
Test name
Test status
Simulation time 165354100473 ps
CPU time 365.48 seconds
Started May 28 02:21:23 PM PDT 24
Finished May 28 02:27:30 PM PDT 24
Peak memory 201864 kb
Host smart-04a781b7-b553-4b19-8c4d-752512be5a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394298826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1394298826
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2222620055
Short name T753
Test name
Test status
Simulation time 324549441602 ps
CPU time 129.19 seconds
Started May 28 02:21:23 PM PDT 24
Finished May 28 02:23:34 PM PDT 24
Peak memory 201832 kb
Host smart-e07a128d-efcf-451b-b6c5-35255ae944b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222620055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2222620055
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3537486101
Short name T475
Test name
Test status
Simulation time 331407336601 ps
CPU time 372.84 seconds
Started May 28 02:21:24 PM PDT 24
Finished May 28 02:27:38 PM PDT 24
Peak memory 201888 kb
Host smart-c7e25566-522c-4b73-851f-6482921a5e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537486101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3537486101
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3768614708
Short name T368
Test name
Test status
Simulation time 162046000020 ps
CPU time 88.81 seconds
Started May 28 02:21:22 PM PDT 24
Finished May 28 02:22:52 PM PDT 24
Peak memory 201824 kb
Host smart-479a2a47-43d9-4ad5-9848-dcde121aa9ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768614708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3768614708
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.4067633228
Short name T133
Test name
Test status
Simulation time 183741350013 ps
CPU time 429.83 seconds
Started May 28 02:21:22 PM PDT 24
Finished May 28 02:28:33 PM PDT 24
Peak memory 201868 kb
Host smart-33ded308-6da9-40a8-9399-3ed7ef8956f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067633228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.4067633228
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2378940340
Short name T585
Test name
Test status
Simulation time 590178758648 ps
CPU time 413.85 seconds
Started May 28 02:21:23 PM PDT 24
Finished May 28 02:28:18 PM PDT 24
Peak memory 201784 kb
Host smart-bdbdd45d-2d5e-4516-aac3-8562776af9bb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378940340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2378940340
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2366181115
Short name T407
Test name
Test status
Simulation time 126772681772 ps
CPU time 628.06 seconds
Started May 28 02:21:34 PM PDT 24
Finished May 28 02:32:04 PM PDT 24
Peak memory 202216 kb
Host smart-2e29dfae-f24c-46ba-b5d0-dab9757304fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366181115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2366181115
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.4103927909
Short name T731
Test name
Test status
Simulation time 44048042182 ps
CPU time 24.42 seconds
Started May 28 02:21:36 PM PDT 24
Finished May 28 02:22:01 PM PDT 24
Peak memory 201644 kb
Host smart-657537af-9dbb-4aa1-8e3e-302174be3213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103927909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.4103927909
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1549711273
Short name T333
Test name
Test status
Simulation time 3782052645 ps
CPU time 10.59 seconds
Started May 28 02:21:36 PM PDT 24
Finished May 28 02:21:48 PM PDT 24
Peak memory 201828 kb
Host smart-5a03c696-5287-4b39-b61a-5447214b792f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549711273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1549711273
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.424749084
Short name T600
Test name
Test status
Simulation time 5745985325 ps
CPU time 4.12 seconds
Started May 28 02:21:23 PM PDT 24
Finished May 28 02:21:29 PM PDT 24
Peak memory 201684 kb
Host smart-272e9fd1-5dff-4e74-be21-ac7f9da8ce37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424749084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.424749084
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1815380941
Short name T503
Test name
Test status
Simulation time 178510827743 ps
CPU time 223.59 seconds
Started May 28 02:21:33 PM PDT 24
Finished May 28 02:25:17 PM PDT 24
Peak memory 201848 kb
Host smart-3e9f10e5-c90d-486c-b3d7-cf2c743cff9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815380941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1815380941
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1261820222
Short name T67
Test name
Test status
Simulation time 621935132103 ps
CPU time 661.09 seconds
Started May 28 02:21:36 PM PDT 24
Finished May 28 02:32:38 PM PDT 24
Peak memory 218060 kb
Host smart-ee4cbcc2-dba6-4564-8485-7c41e3dac607
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261820222 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1261820222
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.292451551
Short name T569
Test name
Test status
Simulation time 339305947 ps
CPU time 0.79 seconds
Started May 28 02:21:44 PM PDT 24
Finished May 28 02:21:46 PM PDT 24
Peak memory 201556 kb
Host smart-966adeb5-cc2d-4356-a9ad-be5fea2aa4dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292451551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.292451551
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3742679848
Short name T793
Test name
Test status
Simulation time 356646824026 ps
CPU time 198.83 seconds
Started May 28 02:21:49 PM PDT 24
Finished May 28 02:25:08 PM PDT 24
Peak memory 201868 kb
Host smart-ad74b0a7-b515-4fe3-a519-d9606ce630a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742679848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3742679848
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.563391173
Short name T273
Test name
Test status
Simulation time 171944223381 ps
CPU time 205.62 seconds
Started May 28 02:21:33 PM PDT 24
Finished May 28 02:25:00 PM PDT 24
Peak memory 201832 kb
Host smart-7b65962d-3437-4e6e-b71a-df2a838d4b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563391173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.563391173
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2404281627
Short name T629
Test name
Test status
Simulation time 326321267885 ps
CPU time 197.01 seconds
Started May 28 02:21:35 PM PDT 24
Finished May 28 02:24:53 PM PDT 24
Peak memory 201828 kb
Host smart-684cb1df-29a5-47e2-98a5-ef424a2e04bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404281627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2404281627
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.905472914
Short name T189
Test name
Test status
Simulation time 326024869958 ps
CPU time 74.57 seconds
Started May 28 02:21:34 PM PDT 24
Finished May 28 02:22:50 PM PDT 24
Peak memory 201884 kb
Host smart-4e8e6df4-20b4-4db2-b854-59912a3f9afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905472914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.905472914
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2919336705
Short name T524
Test name
Test status
Simulation time 492993724990 ps
CPU time 1174.95 seconds
Started May 28 02:21:34 PM PDT 24
Finished May 28 02:41:10 PM PDT 24
Peak memory 201816 kb
Host smart-6c44e18e-2693-4546-a153-b1605207b9e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919336705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2919336705
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2217959832
Short name T45
Test name
Test status
Simulation time 174952214791 ps
CPU time 110.47 seconds
Started May 28 02:21:34 PM PDT 24
Finished May 28 02:23:26 PM PDT 24
Peak memory 201948 kb
Host smart-c529ab14-f4e2-47b5-8e6a-a3989c04e3cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217959832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2217959832
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.930410772
Short name T183
Test name
Test status
Simulation time 198512066144 ps
CPU time 239.87 seconds
Started May 28 02:21:42 PM PDT 24
Finished May 28 02:25:43 PM PDT 24
Peak memory 201844 kb
Host smart-d89fa464-ab02-404c-92b6-a529d46ec17c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930410772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
adc_ctrl_filters_wakeup_fixed.930410772
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.4238070531
Short name T191
Test name
Test status
Simulation time 119826242211 ps
CPU time 442.66 seconds
Started May 28 02:21:48 PM PDT 24
Finished May 28 02:29:12 PM PDT 24
Peak memory 202172 kb
Host smart-6a8f35eb-9024-4ac2-bb91-700a66c4a00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238070531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.4238070531
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.333450704
Short name T630
Test name
Test status
Simulation time 37872851317 ps
CPU time 43.55 seconds
Started May 28 02:21:44 PM PDT 24
Finished May 28 02:22:29 PM PDT 24
Peak memory 201644 kb
Host smart-14c4d980-b873-4720-a1e4-ace40768f247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333450704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.333450704
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.3630639323
Short name T42
Test name
Test status
Simulation time 5225683507 ps
CPU time 3.94 seconds
Started May 28 02:21:44 PM PDT 24
Finished May 28 02:21:49 PM PDT 24
Peak memory 201672 kb
Host smart-779979d7-5bd5-4152-bab3-6925a65dc990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630639323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3630639323
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.897391011
Short name T358
Test name
Test status
Simulation time 5983432759 ps
CPU time 11.69 seconds
Started May 28 02:21:35 PM PDT 24
Finished May 28 02:21:48 PM PDT 24
Peak memory 201656 kb
Host smart-7a000068-8b3b-4b45-9bc8-c4bb73fc933a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897391011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.897391011
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.1159015600
Short name T576
Test name
Test status
Simulation time 134411583266 ps
CPU time 464.6 seconds
Started May 28 02:21:44 PM PDT 24
Finished May 28 02:29:30 PM PDT 24
Peak memory 202240 kb
Host smart-c1343d3a-8f2c-474f-980d-fdc9e009533b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159015600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.1159015600
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3382271384
Short name T267
Test name
Test status
Simulation time 71980198586 ps
CPU time 72.28 seconds
Started May 28 02:21:44 PM PDT 24
Finished May 28 02:22:57 PM PDT 24
Peak memory 210208 kb
Host smart-ddb0d54f-e7cd-487e-896e-9dfb623bce46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382271384 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3382271384
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3365214845
Short name T513
Test name
Test status
Simulation time 296544114 ps
CPU time 1.24 seconds
Started May 28 02:21:57 PM PDT 24
Finished May 28 02:21:59 PM PDT 24
Peak memory 201524 kb
Host smart-c1551915-5e8f-4e44-be95-d7c548ac4369
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365214845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3365214845
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.528047947
Short name T160
Test name
Test status
Simulation time 501858413105 ps
CPU time 658.8 seconds
Started May 28 02:21:54 PM PDT 24
Finished May 28 02:32:54 PM PDT 24
Peak memory 201832 kb
Host smart-cbf3eb61-fbc1-4270-8df8-ceb9e234bdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528047947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.528047947
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2640028333
Short name T375
Test name
Test status
Simulation time 505219022654 ps
CPU time 1210.92 seconds
Started May 28 02:21:49 PM PDT 24
Finished May 28 02:42:01 PM PDT 24
Peak memory 201864 kb
Host smart-9225f3ec-9ea8-409f-b91d-477c188f2b21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640028333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2640028333
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2224169187
Short name T721
Test name
Test status
Simulation time 163878327064 ps
CPU time 171.75 seconds
Started May 28 02:21:43 PM PDT 24
Finished May 28 02:24:36 PM PDT 24
Peak memory 201816 kb
Host smart-32b45325-9c5d-40fd-b67e-9aefcb057daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224169187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2224169187
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.554493819
Short name T550
Test name
Test status
Simulation time 160306352179 ps
CPU time 374.63 seconds
Started May 28 02:21:44 PM PDT 24
Finished May 28 02:28:00 PM PDT 24
Peak memory 201896 kb
Host smart-80e6850a-f1ff-4923-9005-76da8060289c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=554493819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixe
d.554493819
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1790298090
Short name T724
Test name
Test status
Simulation time 514964948586 ps
CPU time 636.77 seconds
Started May 28 02:21:55 PM PDT 24
Finished May 28 02:32:33 PM PDT 24
Peak memory 201844 kb
Host smart-afcbfc71-7a62-4269-ab3f-978798dee882
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790298090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1790298090
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.692874225
Short name T489
Test name
Test status
Simulation time 115411065938 ps
CPU time 396.58 seconds
Started May 28 02:21:55 PM PDT 24
Finished May 28 02:28:33 PM PDT 24
Peak memory 202200 kb
Host smart-2d9e6216-2dac-4baf-bfed-3b74a3e099d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692874225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.692874225
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.679854123
Short name T376
Test name
Test status
Simulation time 45499455269 ps
CPU time 110.27 seconds
Started May 28 02:21:55 PM PDT 24
Finished May 28 02:23:47 PM PDT 24
Peak memory 201636 kb
Host smart-daf8e497-ceeb-44cb-9115-6ec378a790ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679854123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.679854123
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2322902376
Short name T484
Test name
Test status
Simulation time 4688195655 ps
CPU time 11.17 seconds
Started May 28 02:21:56 PM PDT 24
Finished May 28 02:22:09 PM PDT 24
Peak memory 201664 kb
Host smart-0cd3d91d-046c-4887-9334-570ead5608a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322902376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2322902376
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3189612316
Short name T667
Test name
Test status
Simulation time 5861379215 ps
CPU time 3.34 seconds
Started May 28 02:21:43 PM PDT 24
Finished May 28 02:21:47 PM PDT 24
Peak memory 201676 kb
Host smart-d589db8d-7f74-46aa-b3e6-77ab4ef66792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189612316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3189612316
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2689822149
Short name T644
Test name
Test status
Simulation time 506304750 ps
CPU time 0.69 seconds
Started May 28 02:22:05 PM PDT 24
Finished May 28 02:22:07 PM PDT 24
Peak memory 201544 kb
Host smart-8ce8b14a-1279-455f-b1d5-a67961b25d88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689822149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2689822149
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1025555686
Short name T154
Test name
Test status
Simulation time 164604305113 ps
CPU time 91.64 seconds
Started May 28 02:22:05 PM PDT 24
Finished May 28 02:23:37 PM PDT 24
Peak memory 201656 kb
Host smart-0c4f2bb4-b1f7-444c-badb-87790566c170
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025555686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1025555686
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.4055434412
Short name T164
Test name
Test status
Simulation time 493038903475 ps
CPU time 285.29 seconds
Started May 28 02:22:06 PM PDT 24
Finished May 28 02:26:53 PM PDT 24
Peak memory 201888 kb
Host smart-e27dc754-321d-4328-8c8a-d613b1479538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055434412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.4055434412
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2951496752
Short name T626
Test name
Test status
Simulation time 166502106775 ps
CPU time 107.7 seconds
Started May 28 02:21:54 PM PDT 24
Finished May 28 02:23:42 PM PDT 24
Peak memory 201916 kb
Host smart-7c2b16e7-f8fb-44d8-9cce-c0842bf7c43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951496752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2951496752
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1599830967
Short name T690
Test name
Test status
Simulation time 493687728459 ps
CPU time 293.31 seconds
Started May 28 02:21:56 PM PDT 24
Finished May 28 02:26:50 PM PDT 24
Peak memory 201812 kb
Host smart-ce43d4e0-02c7-47ae-9e06-32c910754ac3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599830967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1599830967
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3237184013
Short name T598
Test name
Test status
Simulation time 494795262329 ps
CPU time 1157.56 seconds
Started May 28 02:21:55 PM PDT 24
Finished May 28 02:41:14 PM PDT 24
Peak memory 201820 kb
Host smart-a5d8059d-98c6-4036-bfbf-817263bdb459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237184013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3237184013
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1423721470
Short name T13
Test name
Test status
Simulation time 159057916520 ps
CPU time 350.58 seconds
Started May 28 02:21:55 PM PDT 24
Finished May 28 02:27:47 PM PDT 24
Peak memory 201816 kb
Host smart-2c124bb9-544c-4d32-9530-231b42aa3e40
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423721470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1423721470
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3699474726
Short name T764
Test name
Test status
Simulation time 584585159684 ps
CPU time 373.44 seconds
Started May 28 02:22:06 PM PDT 24
Finished May 28 02:28:21 PM PDT 24
Peak memory 201852 kb
Host smart-6ad9854c-8b39-4927-8d73-f62ffbf34e7d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699474726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3699474726
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2943645987
Short name T570
Test name
Test status
Simulation time 75419336273 ps
CPU time 372.92 seconds
Started May 28 02:22:04 PM PDT 24
Finished May 28 02:28:18 PM PDT 24
Peak memory 202124 kb
Host smart-1be65bbf-2818-4ee2-8367-b798b6e9943f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943645987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2943645987
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3850573434
Short name T390
Test name
Test status
Simulation time 46095731756 ps
CPU time 105.93 seconds
Started May 28 02:22:05 PM PDT 24
Finished May 28 02:23:53 PM PDT 24
Peak memory 201652 kb
Host smart-4c3005ec-d744-4528-afbc-0e8c6146340a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850573434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3850573434
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.357117371
Short name T370
Test name
Test status
Simulation time 3892949911 ps
CPU time 9.69 seconds
Started May 28 02:22:06 PM PDT 24
Finished May 28 02:22:17 PM PDT 24
Peak memory 201628 kb
Host smart-62542768-5845-499d-9baa-c624d933dd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357117371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.357117371
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3104457858
Short name T645
Test name
Test status
Simulation time 5697013676 ps
CPU time 12.85 seconds
Started May 28 02:21:54 PM PDT 24
Finished May 28 02:22:08 PM PDT 24
Peak memory 201688 kb
Host smart-4ea683dc-9c0e-4b7f-b49b-87f018188114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104457858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3104457858
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3392475177
Short name T652
Test name
Test status
Simulation time 129894191387 ps
CPU time 596.01 seconds
Started May 28 02:22:05 PM PDT 24
Finished May 28 02:32:03 PM PDT 24
Peak memory 202172 kb
Host smart-0edd2297-6155-424c-ab6e-dc7a9557171f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392475177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3392475177
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3535550375
Short name T39
Test name
Test status
Simulation time 123546849387 ps
CPU time 194.76 seconds
Started May 28 02:22:04 PM PDT 24
Finished May 28 02:25:20 PM PDT 24
Peak memory 210496 kb
Host smart-8bc39215-56cb-45cc-9291-38d1fa73a840
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535550375 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3535550375
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.603167518
Short name T95
Test name
Test status
Simulation time 385928235 ps
CPU time 0.88 seconds
Started May 28 02:22:18 PM PDT 24
Finished May 28 02:22:20 PM PDT 24
Peak memory 201544 kb
Host smart-261e97ca-0931-4f00-9d15-68cfa8f4a5fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603167518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.603167518
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3122560560
Short name T265
Test name
Test status
Simulation time 186073809062 ps
CPU time 383.65 seconds
Started May 28 02:22:17 PM PDT 24
Finished May 28 02:28:42 PM PDT 24
Peak memory 201928 kb
Host smart-d35772e1-cccd-4455-9024-1ba178b4dc2a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122560560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3122560560
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3680053494
Short name T622
Test name
Test status
Simulation time 494306391643 ps
CPU time 311.49 seconds
Started May 28 02:22:19 PM PDT 24
Finished May 28 02:27:32 PM PDT 24
Peak memory 201920 kb
Host smart-6ef3ad53-67a5-4176-b738-552374442862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680053494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3680053494
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3365666477
Short name T152
Test name
Test status
Simulation time 324962168476 ps
CPU time 363.99 seconds
Started May 28 02:22:19 PM PDT 24
Finished May 28 02:28:24 PM PDT 24
Peak memory 201828 kb
Host smart-f196309f-8c2f-4b28-ab89-39bd6ebacb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365666477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3365666477
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.4133544699
Short name T610
Test name
Test status
Simulation time 494977481882 ps
CPU time 1211.33 seconds
Started May 28 02:22:16 PM PDT 24
Finished May 28 02:42:28 PM PDT 24
Peak memory 201832 kb
Host smart-93231e39-bdb4-413c-a7fc-f5cd10de028c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133544699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.4133544699
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3297319648
Short name T756
Test name
Test status
Simulation time 161733547988 ps
CPU time 59.93 seconds
Started May 28 02:22:05 PM PDT 24
Finished May 28 02:23:07 PM PDT 24
Peak memory 201836 kb
Host smart-5d351492-3842-4cc8-84c7-04e3a5c675fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297319648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3297319648
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1399318089
Short name T668
Test name
Test status
Simulation time 326057975928 ps
CPU time 330.82 seconds
Started May 28 02:22:05 PM PDT 24
Finished May 28 02:27:38 PM PDT 24
Peak memory 201840 kb
Host smart-65cdd3cd-cada-4064-9409-ddb87a607be8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399318089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.1399318089
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3374117901
Short name T255
Test name
Test status
Simulation time 531621683972 ps
CPU time 1234.22 seconds
Started May 28 02:22:17 PM PDT 24
Finished May 28 02:42:52 PM PDT 24
Peak memory 201840 kb
Host smart-18a1ffee-b997-499f-a705-14d64302e7b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374117901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3374117901
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3586442304
Short name T339
Test name
Test status
Simulation time 211930582390 ps
CPU time 470.82 seconds
Started May 28 02:22:17 PM PDT 24
Finished May 28 02:30:09 PM PDT 24
Peak memory 201840 kb
Host smart-31cfbcd7-76e0-4dc9-a750-793791fa99fe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586442304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3586442304
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3945068237
Short name T389
Test name
Test status
Simulation time 88972910389 ps
CPU time 350.11 seconds
Started May 28 02:22:17 PM PDT 24
Finished May 28 02:28:08 PM PDT 24
Peak memory 202152 kb
Host smart-fda6d478-9287-46da-9089-2e33d7efca69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945068237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3945068237
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2354437391
Short name T90
Test name
Test status
Simulation time 36439931594 ps
CPU time 64.83 seconds
Started May 28 02:22:17 PM PDT 24
Finished May 28 02:23:23 PM PDT 24
Peak memory 201636 kb
Host smart-9f83d263-2d9e-4651-8aa9-54f9580a15a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354437391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2354437391
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3852811366
Short name T364
Test name
Test status
Simulation time 3730848954 ps
CPU time 9.17 seconds
Started May 28 02:22:18 PM PDT 24
Finished May 28 02:22:29 PM PDT 24
Peak memory 201592 kb
Host smart-fa880a02-7221-479a-9bbe-813000e3d97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852811366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3852811366
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2140133398
Short name T361
Test name
Test status
Simulation time 6139962255 ps
CPU time 13.34 seconds
Started May 28 02:22:05 PM PDT 24
Finished May 28 02:22:19 PM PDT 24
Peak memory 201660 kb
Host smart-82a78a64-bfc9-4816-aafe-656454836c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140133398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2140133398
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.281161492
Short name T457
Test name
Test status
Simulation time 204967237554 ps
CPU time 35.07 seconds
Started May 28 02:22:18 PM PDT 24
Finished May 28 02:22:55 PM PDT 24
Peak memory 210212 kb
Host smart-77117e7a-8025-4532-adc9-3c24f8947c2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281161492 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.281161492
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.993017450
Short name T474
Test name
Test status
Simulation time 455870046 ps
CPU time 1.7 seconds
Started May 28 02:22:30 PM PDT 24
Finished May 28 02:22:32 PM PDT 24
Peak memory 201556 kb
Host smart-6c9be2f9-d607-473b-8a77-53d5cb6e4c77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993017450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.993017450
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2365642993
Short name T701
Test name
Test status
Simulation time 162215885764 ps
CPU time 111.72 seconds
Started May 28 02:22:28 PM PDT 24
Finished May 28 02:24:21 PM PDT 24
Peak memory 201844 kb
Host smart-be47a451-b37c-41fe-9996-5288aa9bda80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365642993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2365642993
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3168159623
Short name T320
Test name
Test status
Simulation time 327995228661 ps
CPU time 793.66 seconds
Started May 28 02:22:17 PM PDT 24
Finished May 28 02:35:32 PM PDT 24
Peak memory 201920 kb
Host smart-a9be8765-af13-4ac4-81e5-00550a99a11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168159623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3168159623
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2077081053
Short name T496
Test name
Test status
Simulation time 484056256859 ps
CPU time 1188.79 seconds
Started May 28 02:22:19 PM PDT 24
Finished May 28 02:42:09 PM PDT 24
Peak memory 201848 kb
Host smart-83c225db-bf90-4cf6-9b84-801d1783eb9e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077081053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2077081053
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.4210222144
Short name T646
Test name
Test status
Simulation time 159615545043 ps
CPU time 43.7 seconds
Started May 28 02:22:16 PM PDT 24
Finished May 28 02:23:01 PM PDT 24
Peak memory 201840 kb
Host smart-938049fe-55a3-4aa9-8cd8-38243bb8052f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210222144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.4210222144
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2931836942
Short name T351
Test name
Test status
Simulation time 163339761644 ps
CPU time 190.73 seconds
Started May 28 02:22:18 PM PDT 24
Finished May 28 02:25:30 PM PDT 24
Peak memory 201832 kb
Host smart-152943b5-30ee-4d60-9c8e-519c058fe309
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931836942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2931836942
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3572342101
Short name T510
Test name
Test status
Simulation time 587547229520 ps
CPU time 295.78 seconds
Started May 28 02:22:17 PM PDT 24
Finished May 28 02:27:14 PM PDT 24
Peak memory 201844 kb
Host smart-111b1bae-7cc6-4dd5-8dac-61de65537726
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572342101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3572342101
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.4199781497
Short name T418
Test name
Test status
Simulation time 105064380694 ps
CPU time 530.76 seconds
Started May 28 02:22:29 PM PDT 24
Finished May 28 02:31:21 PM PDT 24
Peak memory 202156 kb
Host smart-1e5b2e34-417d-4822-b562-bf86afed01b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199781497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.4199781497
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.447255104
Short name T758
Test name
Test status
Simulation time 39675347954 ps
CPU time 19.97 seconds
Started May 28 02:22:31 PM PDT 24
Finished May 28 02:22:51 PM PDT 24
Peak memory 201648 kb
Host smart-1802d071-2041-4d05-9dcf-8772684da737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447255104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.447255104
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.882213973
Short name T456
Test name
Test status
Simulation time 4265483807 ps
CPU time 1.28 seconds
Started May 28 02:22:30 PM PDT 24
Finished May 28 02:22:32 PM PDT 24
Peak memory 201584 kb
Host smart-3ed70fc9-1a3f-43aa-866a-1aee50f6c385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882213973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.882213973
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.671477565
Short name T740
Test name
Test status
Simulation time 5754785286 ps
CPU time 13.9 seconds
Started May 28 02:22:18 PM PDT 24
Finished May 28 02:22:34 PM PDT 24
Peak memory 201656 kb
Host smart-c0991388-ff3f-4067-a679-9fdc5d037252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671477565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.671477565
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.3180860048
Short name T319
Test name
Test status
Simulation time 359317452931 ps
CPU time 902.19 seconds
Started May 28 02:22:31 PM PDT 24
Finished May 28 02:37:34 PM PDT 24
Peak memory 202160 kb
Host smart-6eb91cc0-69ec-45c2-bc1b-63762cc6820d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180860048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.3180860048
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1612555660
Short name T23
Test name
Test status
Simulation time 91904478897 ps
CPU time 159.12 seconds
Started May 28 02:22:29 PM PDT 24
Finished May 28 02:25:10 PM PDT 24
Peak memory 210224 kb
Host smart-3b172de7-73c6-4334-84c4-db4e4c0067b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612555660 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1612555660
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3210895201
Short name T766
Test name
Test status
Simulation time 352934949 ps
CPU time 1.47 seconds
Started May 28 02:22:44 PM PDT 24
Finished May 28 02:22:47 PM PDT 24
Peak memory 201544 kb
Host smart-a457e461-e1e7-4621-9000-9e5f8186fb76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210895201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3210895201
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3330291350
Short name T492
Test name
Test status
Simulation time 332768568631 ps
CPU time 157.58 seconds
Started May 28 02:22:44 PM PDT 24
Finished May 28 02:25:23 PM PDT 24
Peak memory 201824 kb
Host smart-fe8de325-503f-4213-aa25-04e0ddefb024
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330291350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3330291350
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.480478816
Short name T207
Test name
Test status
Simulation time 165234843590 ps
CPU time 376.95 seconds
Started May 28 02:22:36 PM PDT 24
Finished May 28 02:28:54 PM PDT 24
Peak memory 202100 kb
Host smart-6803719d-10fd-422a-8c17-b7cdb6680560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480478816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.480478816
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.4094497564
Short name T363
Test name
Test status
Simulation time 159475791473 ps
CPU time 345.25 seconds
Started May 28 02:22:31 PM PDT 24
Finished May 28 02:28:17 PM PDT 24
Peak memory 201844 kb
Host smart-41193b76-3f44-4be5-913c-26ada932c623
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094497564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.4094497564
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.272612390
Short name T135
Test name
Test status
Simulation time 493920845714 ps
CPU time 1185.17 seconds
Started May 28 02:22:30 PM PDT 24
Finished May 28 02:42:16 PM PDT 24
Peak memory 201924 kb
Host smart-f2c0455c-b132-4de9-9082-1c3d70afd4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272612390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.272612390
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3695670788
Short name T599
Test name
Test status
Simulation time 330559423881 ps
CPU time 847.57 seconds
Started May 28 02:22:31 PM PDT 24
Finished May 28 02:36:39 PM PDT 24
Peak memory 201808 kb
Host smart-04452d5b-bd07-4b4f-9313-b0062b41ca11
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695670788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3695670788
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2303884478
Short name T752
Test name
Test status
Simulation time 184527908022 ps
CPU time 419.83 seconds
Started May 28 02:22:29 PM PDT 24
Finished May 28 02:29:30 PM PDT 24
Peak memory 201944 kb
Host smart-c7bc2c33-11ed-43a7-a927-6cc1000df9e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303884478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2303884478
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3427675998
Short name T442
Test name
Test status
Simulation time 405940055963 ps
CPU time 258.03 seconds
Started May 28 02:22:45 PM PDT 24
Finished May 28 02:27:04 PM PDT 24
Peak memory 201844 kb
Host smart-1ac0c60c-c324-4f12-831d-739f54a9cb58
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427675998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3427675998
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.1710789278
Short name T438
Test name
Test status
Simulation time 136142465387 ps
CPU time 546.83 seconds
Started May 28 02:22:43 PM PDT 24
Finished May 28 02:31:51 PM PDT 24
Peak memory 202132 kb
Host smart-7127bb4d-7a61-4bda-bca7-24fcff09a97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710789278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.1710789278
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2409433974
Short name T174
Test name
Test status
Simulation time 31018201570 ps
CPU time 19.48 seconds
Started May 28 02:22:44 PM PDT 24
Finished May 28 02:23:04 PM PDT 24
Peak memory 201640 kb
Host smart-eab8cb8c-a044-4fb4-bb74-5fc9f8bc539f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409433974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2409433974
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.829485266
Short name T679
Test name
Test status
Simulation time 3615859221 ps
CPU time 9.65 seconds
Started May 28 02:22:44 PM PDT 24
Finished May 28 02:22:55 PM PDT 24
Peak memory 201608 kb
Host smart-cab73117-cd9c-46f6-84eb-c9c1b2102f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829485266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.829485266
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.782412948
Short name T385
Test name
Test status
Simulation time 5874076467 ps
CPU time 14.96 seconds
Started May 28 02:22:31 PM PDT 24
Finished May 28 02:22:46 PM PDT 24
Peak memory 201680 kb
Host smart-a90362e1-68ce-48db-8ab5-d47f2fd90ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782412948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.782412948
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3223586806
Short name T192
Test name
Test status
Simulation time 205971001971 ps
CPU time 1065.94 seconds
Started May 28 02:22:47 PM PDT 24
Finished May 28 02:40:34 PM PDT 24
Peak memory 202232 kb
Host smart-a2735d25-fac9-4031-b819-ac7d319a3c78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223586806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3223586806
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3833380584
Short name T641
Test name
Test status
Simulation time 889035439742 ps
CPU time 389.87 seconds
Started May 28 02:22:45 PM PDT 24
Finished May 28 02:29:15 PM PDT 24
Peak memory 210140 kb
Host smart-2a945a9b-0010-4d75-9f78-76ff7598c660
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833380584 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3833380584
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.1706324259
Short name T566
Test name
Test status
Simulation time 285229277 ps
CPU time 1.15 seconds
Started May 28 02:23:05 PM PDT 24
Finished May 28 02:23:08 PM PDT 24
Peak memory 201528 kb
Host smart-db3db8e0-e6ff-43ad-a3c5-9fa50d5222c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706324259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1706324259
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3077185204
Short name T559
Test name
Test status
Simulation time 163370818001 ps
CPU time 95.32 seconds
Started May 28 02:22:56 PM PDT 24
Finished May 28 02:24:32 PM PDT 24
Peak memory 201916 kb
Host smart-02871034-5f6b-47e6-9495-575ec17c0325
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077185204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3077185204
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.4124841351
Short name T156
Test name
Test status
Simulation time 497982524257 ps
CPU time 311.06 seconds
Started May 28 02:22:52 PM PDT 24
Finished May 28 02:28:04 PM PDT 24
Peak memory 201932 kb
Host smart-b820d500-49d0-45dc-9a70-9b82e302b9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124841351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.4124841351
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3581934298
Short name T587
Test name
Test status
Simulation time 327058803785 ps
CPU time 533.41 seconds
Started May 28 02:22:56 PM PDT 24
Finished May 28 02:31:51 PM PDT 24
Peak memory 201840 kb
Host smart-e8fc7206-d635-47a8-9060-c9d274a5284b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581934298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.3581934298
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1727564159
Short name T231
Test name
Test status
Simulation time 499331947200 ps
CPU time 298.42 seconds
Started May 28 02:22:44 PM PDT 24
Finished May 28 02:27:44 PM PDT 24
Peak memory 201908 kb
Host smart-3096bb9e-086d-4247-b0ed-827193cf9fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727564159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1727564159
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2683988779
Short name T421
Test name
Test status
Simulation time 328389868505 ps
CPU time 388.11 seconds
Started May 28 02:22:53 PM PDT 24
Finished May 28 02:29:22 PM PDT 24
Peak memory 201828 kb
Host smart-9816699b-1eb4-42b7-a0f9-41edf63526b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683988779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2683988779
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1595961371
Short name T703
Test name
Test status
Simulation time 202286599757 ps
CPU time 429.85 seconds
Started May 28 02:22:53 PM PDT 24
Finished May 28 02:30:04 PM PDT 24
Peak memory 201876 kb
Host smart-dd178d4a-c8f2-4d85-9700-3670bd66bac0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595961371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1595961371
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1669743314
Short name T515
Test name
Test status
Simulation time 207729186310 ps
CPU time 412.89 seconds
Started May 28 02:22:54 PM PDT 24
Finished May 28 02:29:48 PM PDT 24
Peak memory 201936 kb
Host smart-41faed4d-8d33-4d0c-ace3-bddcf7cee34a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669743314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1669743314
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.303764884
Short name T329
Test name
Test status
Simulation time 91099280429 ps
CPU time 296.47 seconds
Started May 28 02:22:56 PM PDT 24
Finished May 28 02:27:53 PM PDT 24
Peak memory 202228 kb
Host smart-a1aca0e6-363b-454e-aada-511d05523a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303764884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.303764884
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.632158552
Short name T352
Test name
Test status
Simulation time 42946751583 ps
CPU time 97.94 seconds
Started May 28 02:22:54 PM PDT 24
Finished May 28 02:24:33 PM PDT 24
Peak memory 201664 kb
Host smart-b8e27e58-2056-4cf6-9f65-9b1c5ba0290b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632158552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.632158552
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2926135334
Short name T480
Test name
Test status
Simulation time 4572627654 ps
CPU time 11.79 seconds
Started May 28 02:22:52 PM PDT 24
Finished May 28 02:23:05 PM PDT 24
Peak memory 201660 kb
Host smart-5d9bcc2a-6799-4257-8cf9-8fc7c57c69e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926135334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2926135334
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.381024667
Short name T706
Test name
Test status
Simulation time 5770706800 ps
CPU time 2.05 seconds
Started May 28 02:22:43 PM PDT 24
Finished May 28 02:22:46 PM PDT 24
Peak memory 201920 kb
Host smart-8f8db88a-4380-41b9-b877-575fcf892308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381024667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.381024667
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.611043277
Short name T618
Test name
Test status
Simulation time 497424076 ps
CPU time 1.62 seconds
Started May 28 02:23:04 PM PDT 24
Finished May 28 02:23:08 PM PDT 24
Peak memory 201548 kb
Host smart-5956ccdb-6de0-4f6c-80a6-110937fff9ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611043277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.611043277
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1568451223
Short name T595
Test name
Test status
Simulation time 513581374952 ps
CPU time 852.09 seconds
Started May 28 02:23:04 PM PDT 24
Finished May 28 02:37:19 PM PDT 24
Peak memory 201860 kb
Host smart-e10316e4-d065-46e0-b8a3-e5df101ee661
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568451223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1568451223
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.330035191
Short name T710
Test name
Test status
Simulation time 163408642863 ps
CPU time 354.32 seconds
Started May 28 02:23:04 PM PDT 24
Finished May 28 02:29:01 PM PDT 24
Peak memory 201856 kb
Host smart-26be06dd-a166-4362-9311-d2d3badf2805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330035191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.330035191
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3814459476
Short name T162
Test name
Test status
Simulation time 161508471260 ps
CPU time 76.6 seconds
Started May 28 02:23:02 PM PDT 24
Finished May 28 02:24:20 PM PDT 24
Peak memory 201844 kb
Host smart-e7c234e7-8952-4274-8d7e-ede4585f9d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814459476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3814459476
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.4023946325
Short name T773
Test name
Test status
Simulation time 162942195701 ps
CPU time 188.06 seconds
Started May 28 02:23:03 PM PDT 24
Finished May 28 02:26:13 PM PDT 24
Peak memory 201828 kb
Host smart-99a9295e-dc2d-4a60-a0f6-63e7e881fbea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023946325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.4023946325
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.883746541
Short name T247
Test name
Test status
Simulation time 331832206576 ps
CPU time 390.79 seconds
Started May 28 02:23:03 PM PDT 24
Finished May 28 02:29:37 PM PDT 24
Peak memory 201824 kb
Host smart-8cd56023-d486-4e4b-8fb1-180c5c24e280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883746541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.883746541
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2521253840
Short name T344
Test name
Test status
Simulation time 164725374047 ps
CPU time 361.54 seconds
Started May 28 02:23:04 PM PDT 24
Finished May 28 02:29:08 PM PDT 24
Peak memory 201780 kb
Host smart-a3cddbaa-a31e-425b-b90c-673671364bb8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521253840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2521253840
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.248767654
Short name T560
Test name
Test status
Simulation time 287083093109 ps
CPU time 662.13 seconds
Started May 28 02:23:04 PM PDT 24
Finished May 28 02:34:09 PM PDT 24
Peak memory 201948 kb
Host smart-28113749-f8be-4ec2-bf23-1d9ede9c6e4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248767654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.248767654
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1882034780
Short name T102
Test name
Test status
Simulation time 582013845953 ps
CPU time 1313.05 seconds
Started May 28 02:23:04 PM PDT 24
Finished May 28 02:44:59 PM PDT 24
Peak memory 201900 kb
Host smart-c9a84bd7-d4ff-4010-8d68-31f7b0f6a4bc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882034780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1882034780
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.254618473
Short name T200
Test name
Test status
Simulation time 75597209337 ps
CPU time 266.06 seconds
Started May 28 02:23:03 PM PDT 24
Finished May 28 02:27:30 PM PDT 24
Peak memory 202220 kb
Host smart-4d99fceb-fe08-4d12-8fbb-4035a302a55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254618473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.254618473
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3602404247
Short name T366
Test name
Test status
Simulation time 31572941325 ps
CPU time 68.54 seconds
Started May 28 02:23:03 PM PDT 24
Finished May 28 02:24:14 PM PDT 24
Peak memory 201720 kb
Host smart-113f937a-e4af-413c-8bcd-04f92e537cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602404247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3602404247
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2710264297
Short name T54
Test name
Test status
Simulation time 3786254988 ps
CPU time 8.12 seconds
Started May 28 02:23:04 PM PDT 24
Finished May 28 02:23:15 PM PDT 24
Peak memory 201624 kb
Host smart-39acd7b5-61a3-47cc-85f6-66d7dad430f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710264297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2710264297
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.763335143
Short name T499
Test name
Test status
Simulation time 5575224841 ps
CPU time 7.92 seconds
Started May 28 02:23:04 PM PDT 24
Finished May 28 02:23:14 PM PDT 24
Peak memory 201688 kb
Host smart-b010e066-de2b-4d34-9d29-859a5103ea0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763335143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.763335143
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.592642690
Short name T55
Test name
Test status
Simulation time 164767610267 ps
CPU time 82.6 seconds
Started May 28 02:23:03 PM PDT 24
Finished May 28 02:24:29 PM PDT 24
Peak memory 201856 kb
Host smart-5be103dc-b92b-4f09-bb4c-2a1c3ec6d503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592642690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.
592642690
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2340881265
Short name T450
Test name
Test status
Simulation time 486015742 ps
CPU time 0.78 seconds
Started May 28 02:23:27 PM PDT 24
Finished May 28 02:23:29 PM PDT 24
Peak memory 201536 kb
Host smart-385e3806-79fc-4d32-a012-24f433fedb05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340881265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2340881265
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2979990300
Short name T149
Test name
Test status
Simulation time 371078716452 ps
CPU time 158.14 seconds
Started May 28 02:23:15 PM PDT 24
Finished May 28 02:25:54 PM PDT 24
Peak memory 201908 kb
Host smart-c0d49260-6b66-4b00-964b-be643379ae6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979990300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2979990300
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.424596323
Short name T639
Test name
Test status
Simulation time 163154262890 ps
CPU time 389.02 seconds
Started May 28 02:23:15 PM PDT 24
Finished May 28 02:29:45 PM PDT 24
Peak memory 201864 kb
Host smart-f37d244e-44c7-44b7-b206-ac87921c2f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424596323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.424596323
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.4125626827
Short name T464
Test name
Test status
Simulation time 163949797867 ps
CPU time 408.04 seconds
Started May 28 02:23:14 PM PDT 24
Finished May 28 02:30:03 PM PDT 24
Peak memory 201844 kb
Host smart-5e3d74b0-bec1-4dad-ae31-60b55392dfba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125626827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.4125626827
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.4099372712
Short name T159
Test name
Test status
Simulation time 327433423470 ps
CPU time 687.52 seconds
Started May 28 02:23:14 PM PDT 24
Finished May 28 02:34:42 PM PDT 24
Peak memory 201820 kb
Host smart-d40936e2-fd0f-489e-bd53-451898b3fa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099372712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.4099372712
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2224036731
Short name T588
Test name
Test status
Simulation time 490746459042 ps
CPU time 1168.51 seconds
Started May 28 02:23:16 PM PDT 24
Finished May 28 02:42:46 PM PDT 24
Peak memory 201648 kb
Host smart-751f6cb8-9d6e-49ff-bac3-e7a9e6bc1377
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224036731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2224036731
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.880903491
Short name T369
Test name
Test status
Simulation time 199505174281 ps
CPU time 148.9 seconds
Started May 28 02:23:14 PM PDT 24
Finished May 28 02:25:44 PM PDT 24
Peak memory 201840 kb
Host smart-cbf69b1b-982e-4d08-b2e0-9e7045fa8399
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880903491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.880903491
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2987062781
Short name T201
Test name
Test status
Simulation time 120383819128 ps
CPU time 676.36 seconds
Started May 28 02:23:29 PM PDT 24
Finished May 28 02:34:47 PM PDT 24
Peak memory 202204 kb
Host smart-21553574-eaf4-4c27-8b0e-c8593e0818e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987062781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2987062781
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1043785547
Short name T175
Test name
Test status
Simulation time 34744174490 ps
CPU time 21.69 seconds
Started May 28 02:23:14 PM PDT 24
Finished May 28 02:23:37 PM PDT 24
Peak memory 201688 kb
Host smart-72fafbe9-a750-40d8-94c4-bf5203e2ea74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043785547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1043785547
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2791995277
Short name T373
Test name
Test status
Simulation time 5334527112 ps
CPU time 11.39 seconds
Started May 28 02:23:16 PM PDT 24
Finished May 28 02:23:28 PM PDT 24
Peak memory 201672 kb
Host smart-94ec1dec-d7ff-4849-9d57-639bf83f78c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791995277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2791995277
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1163818209
Short name T531
Test name
Test status
Simulation time 6121702194 ps
CPU time 4.44 seconds
Started May 28 02:23:03 PM PDT 24
Finished May 28 02:23:10 PM PDT 24
Peak memory 201668 kb
Host smart-d983b27a-9997-4767-b431-a14649860614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163818209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1163818209
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.451252908
Short name T571
Test name
Test status
Simulation time 374203906139 ps
CPU time 396.42 seconds
Started May 28 02:23:29 PM PDT 24
Finished May 28 02:30:07 PM PDT 24
Peak memory 201844 kb
Host smart-d1303a05-2e62-4e23-b62c-6f7a37ec643c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451252908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
451252908
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1612833248
Short name T759
Test name
Test status
Simulation time 350582225941 ps
CPU time 272.32 seconds
Started May 28 02:23:28 PM PDT 24
Finished May 28 02:28:02 PM PDT 24
Peak memory 210476 kb
Host smart-21d10de9-526d-47b8-9da2-cc920b89e36f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612833248 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1612833248
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3415037098
Short name T770
Test name
Test status
Simulation time 505853144468 ps
CPU time 703.69 seconds
Started May 28 02:19:57 PM PDT 24
Finished May 28 02:31:43 PM PDT 24
Peak memory 201844 kb
Host smart-ef895c02-63a1-42a0-a517-359e84010640
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415037098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3415037098
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.452473605
Short name T573
Test name
Test status
Simulation time 165144249682 ps
CPU time 191.86 seconds
Started May 28 02:19:58 PM PDT 24
Finished May 28 02:23:11 PM PDT 24
Peak memory 201928 kb
Host smart-34c80efc-bb6e-4412-83ab-6867d6cc3433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452473605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.452473605
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.202679875
Short name T387
Test name
Test status
Simulation time 165087684534 ps
CPU time 90.1 seconds
Started May 28 02:19:57 PM PDT 24
Finished May 28 02:21:29 PM PDT 24
Peak memory 201868 kb
Host smart-2ee7c42a-e515-4019-8d5e-7e079ea1ab3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202679875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.202679875
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3259054364
Short name T714
Test name
Test status
Simulation time 490964461744 ps
CPU time 280.48 seconds
Started May 28 02:19:57 PM PDT 24
Finished May 28 02:24:40 PM PDT 24
Peak memory 201828 kb
Host smart-63e0edbe-5c9c-40f0-bef4-d8fdc407735a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259054364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3259054364
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.694730997
Short name T148
Test name
Test status
Simulation time 487159199679 ps
CPU time 644.41 seconds
Started May 28 02:19:58 PM PDT 24
Finished May 28 02:30:44 PM PDT 24
Peak memory 201792 kb
Host smart-63e55036-daa3-4f28-9fd7-dc80827a53ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694730997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.694730997
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.666982504
Short name T715
Test name
Test status
Simulation time 324853743936 ps
CPU time 387.01 seconds
Started May 28 02:19:58 PM PDT 24
Finished May 28 02:26:27 PM PDT 24
Peak memory 201852 kb
Host smart-3677c55a-2a5a-4d5c-8803-e8a9af688c95
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=666982504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.666982504
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2110488502
Short name T509
Test name
Test status
Simulation time 176035469350 ps
CPU time 105.61 seconds
Started May 28 02:19:58 PM PDT 24
Finished May 28 02:21:45 PM PDT 24
Peak memory 201952 kb
Host smart-a95eab2d-9450-4dfc-a86c-c331d5d2caca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110488502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2110488502
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2610234338
Short name T8
Test name
Test status
Simulation time 390377370073 ps
CPU time 535.72 seconds
Started May 28 02:19:59 PM PDT 24
Finished May 28 02:28:57 PM PDT 24
Peak memory 201856 kb
Host smart-a9ede041-f381-4786-ba1b-90d325a6e5e2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610234338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2610234338
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.790777119
Short name T527
Test name
Test status
Simulation time 70113065727 ps
CPU time 275.98 seconds
Started May 28 02:19:59 PM PDT 24
Finished May 28 02:24:36 PM PDT 24
Peak memory 202212 kb
Host smart-3a88bbbb-7fcc-4ceb-aff1-29fd7b33ee55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790777119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.790777119
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.7891019
Short name T483
Test name
Test status
Simulation time 25504735579 ps
CPU time 64.6 seconds
Started May 28 02:19:57 PM PDT 24
Finished May 28 02:21:04 PM PDT 24
Peak memory 201648 kb
Host smart-b3d37b9c-5958-4b83-967c-2a392f355408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7891019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.7891019
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.100878816
Short name T590
Test name
Test status
Simulation time 3052492250 ps
CPU time 4.43 seconds
Started May 28 02:19:57 PM PDT 24
Finished May 28 02:20:03 PM PDT 24
Peak memory 201612 kb
Host smart-8c71a514-ebdf-4edd-885f-b4c366d46b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100878816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.100878816
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2393087099
Short name T82
Test name
Test status
Simulation time 7932428588 ps
CPU time 19.73 seconds
Started May 28 02:19:58 PM PDT 24
Finished May 28 02:20:20 PM PDT 24
Peak memory 218580 kb
Host smart-41f63c7b-d2e2-4f3b-b2b7-ed1828b7d2b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393087099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2393087099
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3505913873
Short name T672
Test name
Test status
Simulation time 5634070314 ps
CPU time 14.2 seconds
Started May 28 02:19:47 PM PDT 24
Finished May 28 02:20:02 PM PDT 24
Peak memory 201668 kb
Host smart-9d4e363d-15b9-47b8-b43c-09dbca43c9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505913873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3505913873
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3454759768
Short name T202
Test name
Test status
Simulation time 278419547112 ps
CPU time 607.27 seconds
Started May 28 02:19:58 PM PDT 24
Finished May 28 02:30:07 PM PDT 24
Peak memory 202176 kb
Host smart-79a02e55-9f2e-4eeb-9e39-1fadd4ac52e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454759768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3454759768
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2180789864
Short name T19
Test name
Test status
Simulation time 30881536772 ps
CPU time 91.51 seconds
Started May 28 02:19:57 PM PDT 24
Finished May 28 02:21:30 PM PDT 24
Peak memory 210468 kb
Host smart-61bff229-cdde-45bc-80d6-e1e38ac18b82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180789864 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2180789864
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.573554036
Short name T404
Test name
Test status
Simulation time 357712029 ps
CPU time 0.83 seconds
Started May 28 02:23:39 PM PDT 24
Finished May 28 02:23:42 PM PDT 24
Peak memory 201520 kb
Host smart-271cceb0-9776-474a-9dd8-c319383e0697
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573554036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.573554036
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2430041225
Short name T12
Test name
Test status
Simulation time 239420505005 ps
CPU time 457.11 seconds
Started May 28 02:23:28 PM PDT 24
Finished May 28 02:31:06 PM PDT 24
Peak memory 201928 kb
Host smart-5d001a71-b881-4660-826a-5713d73c27aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430041225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2430041225
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2668621649
Short name T243
Test name
Test status
Simulation time 160184535542 ps
CPU time 201.34 seconds
Started May 28 02:23:28 PM PDT 24
Finished May 28 02:26:51 PM PDT 24
Peak memory 201852 kb
Host smart-a7b297b5-86bc-47f1-bfe5-c099dea72266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668621649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2668621649
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.769553326
Short name T719
Test name
Test status
Simulation time 323657947924 ps
CPU time 207.57 seconds
Started May 28 02:23:29 PM PDT 24
Finished May 28 02:26:58 PM PDT 24
Peak memory 201836 kb
Host smart-2967d1ac-81f9-4cfb-9f4b-bf3c6820efd8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=769553326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.769553326
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.519432869
Short name T313
Test name
Test status
Simulation time 337402704040 ps
CPU time 803.43 seconds
Started May 28 02:23:27 PM PDT 24
Finished May 28 02:36:52 PM PDT 24
Peak memory 201920 kb
Host smart-f09e0ab2-d157-404c-8a00-187bc3410218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519432869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.519432869
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2019365187
Short name T578
Test name
Test status
Simulation time 489545381612 ps
CPU time 259.35 seconds
Started May 28 02:23:28 PM PDT 24
Finished May 28 02:27:49 PM PDT 24
Peak memory 201828 kb
Host smart-190bf35a-ea97-43fd-a474-ce20528098b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019365187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2019365187
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.1471200151
Short name T748
Test name
Test status
Simulation time 514349516303 ps
CPU time 1066.07 seconds
Started May 28 02:23:29 PM PDT 24
Finished May 28 02:41:17 PM PDT 24
Peak memory 201868 kb
Host smart-99ee4f78-d4e1-4b25-bdbf-9150327e6b26
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471200151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.1471200151
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1884130219
Short name T437
Test name
Test status
Simulation time 604240758981 ps
CPU time 1409.46 seconds
Started May 28 02:23:27 PM PDT 24
Finished May 28 02:46:58 PM PDT 24
Peak memory 201820 kb
Host smart-5805a630-9e3d-41a1-b9d6-715d937edb45
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884130219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1884130219
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1382166730
Short name T676
Test name
Test status
Simulation time 127334106661 ps
CPU time 427.22 seconds
Started May 28 02:23:40 PM PDT 24
Finished May 28 02:30:49 PM PDT 24
Peak memory 202408 kb
Host smart-19d274e9-1554-420a-ad7d-84e230d6ed98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382166730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1382166730
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2236282774
Short name T1
Test name
Test status
Simulation time 35873212840 ps
CPU time 21.3 seconds
Started May 28 02:23:40 PM PDT 24
Finished May 28 02:24:03 PM PDT 24
Peak memory 201668 kb
Host smart-2ae47a9f-997f-4c83-aa4b-644d5e2031b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236282774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2236282774
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.4148919281
Short name T396
Test name
Test status
Simulation time 2991556277 ps
CPU time 7.7 seconds
Started May 28 02:23:39 PM PDT 24
Finished May 28 02:23:49 PM PDT 24
Peak memory 201588 kb
Host smart-b9954eaa-1813-4932-a20b-3a927932e775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148919281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.4148919281
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3155729044
Short name T577
Test name
Test status
Simulation time 5827685158 ps
CPU time 7.69 seconds
Started May 28 02:23:30 PM PDT 24
Finished May 28 02:23:39 PM PDT 24
Peak memory 201676 kb
Host smart-bae82b5f-544d-41c0-842b-126a15786a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155729044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3155729044
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2437423552
Short name T737
Test name
Test status
Simulation time 211636961395 ps
CPU time 209.27 seconds
Started May 28 02:23:40 PM PDT 24
Finished May 28 02:27:11 PM PDT 24
Peak memory 211480 kb
Host smart-b1cebde3-0c9d-48d5-8d3c-b3103e6b58e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437423552 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2437423552
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3902750130
Short name T684
Test name
Test status
Simulation time 327296717 ps
CPU time 1.01 seconds
Started May 28 02:23:50 PM PDT 24
Finished May 28 02:23:52 PM PDT 24
Peak memory 201552 kb
Host smart-07dd6f0b-2df2-4f53-9666-d7b34dd13a54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902750130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3902750130
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2764144397
Short name T236
Test name
Test status
Simulation time 398607411230 ps
CPU time 127.83 seconds
Started May 28 02:23:39 PM PDT 24
Finished May 28 02:25:49 PM PDT 24
Peak memory 201912 kb
Host smart-e9a5b043-fb22-4111-bd68-521889035ba2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764144397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2764144397
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2368120798
Short name T321
Test name
Test status
Simulation time 357526275379 ps
CPU time 217.51 seconds
Started May 28 02:23:39 PM PDT 24
Finished May 28 02:27:19 PM PDT 24
Peak memory 201868 kb
Host smart-b0573065-c2a8-4ade-a8d2-7ceaadc50f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368120798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2368120798
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1383471847
Short name T544
Test name
Test status
Simulation time 161232237633 ps
CPU time 194.23 seconds
Started May 28 02:23:38 PM PDT 24
Finished May 28 02:26:55 PM PDT 24
Peak memory 201796 kb
Host smart-b3fc9375-bd6f-4e4e-8125-5b02841a2db9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383471847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1383471847
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3762128310
Short name T260
Test name
Test status
Simulation time 164761360095 ps
CPU time 395.7 seconds
Started May 28 02:23:40 PM PDT 24
Finished May 28 02:30:17 PM PDT 24
Peak memory 201836 kb
Host smart-5ee7ea34-cdc4-482a-a888-017e178bfbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762128310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3762128310
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2563880474
Short name T682
Test name
Test status
Simulation time 164276769593 ps
CPU time 99.19 seconds
Started May 28 02:23:38 PM PDT 24
Finished May 28 02:25:20 PM PDT 24
Peak memory 201812 kb
Host smart-1647289a-f2e8-4067-ad9b-4e34be33abf5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563880474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2563880474
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2888694348
Short name T743
Test name
Test status
Simulation time 539075899653 ps
CPU time 652.15 seconds
Started May 28 02:23:38 PM PDT 24
Finished May 28 02:34:32 PM PDT 24
Peak memory 201796 kb
Host smart-851a23ef-c9ef-4f5a-b07e-1cbe862ee010
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888694348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2888694348
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1666551395
Short name T391
Test name
Test status
Simulation time 403620084402 ps
CPU time 808.85 seconds
Started May 28 02:23:39 PM PDT 24
Finished May 28 02:37:10 PM PDT 24
Peak memory 201828 kb
Host smart-4b991b69-c0e4-4f3e-a3a4-48e664bd5e6a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666551395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1666551395
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1674529845
Short name T537
Test name
Test status
Simulation time 111925978797 ps
CPU time 447.49 seconds
Started May 28 02:23:49 PM PDT 24
Finished May 28 02:31:18 PM PDT 24
Peak memory 202160 kb
Host smart-91ec5581-bb44-4daa-ad53-97073ac9776c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674529845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1674529845
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.4081194358
Short name T521
Test name
Test status
Simulation time 36789642955 ps
CPU time 40.5 seconds
Started May 28 02:23:48 PM PDT 24
Finished May 28 02:24:30 PM PDT 24
Peak memory 201684 kb
Host smart-ee90ee12-df1d-4209-90e7-bbf96cc4c5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081194358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.4081194358
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2096048331
Short name T88
Test name
Test status
Simulation time 5041354333 ps
CPU time 3.75 seconds
Started May 28 02:23:41 PM PDT 24
Finished May 28 02:23:46 PM PDT 24
Peak memory 201680 kb
Host smart-73ce3416-0279-4940-834b-05ba1425fdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096048331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2096048331
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2813381592
Short name T614
Test name
Test status
Simulation time 6045027199 ps
CPU time 12.8 seconds
Started May 28 02:23:38 PM PDT 24
Finished May 28 02:23:53 PM PDT 24
Peak memory 201672 kb
Host smart-334c692c-26c0-452f-98b5-834b1f4ac1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813381592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2813381592
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2211910824
Short name T751
Test name
Test status
Simulation time 120008810098 ps
CPU time 592.97 seconds
Started May 28 02:23:50 PM PDT 24
Finished May 28 02:33:44 PM PDT 24
Peak memory 210440 kb
Host smart-3f1634be-ef82-48a7-ba59-dca83ff15aaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211910824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2211910824
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.296199302
Short name T699
Test name
Test status
Simulation time 55240030405 ps
CPU time 126.24 seconds
Started May 28 02:23:54 PM PDT 24
Finished May 28 02:26:01 PM PDT 24
Peak memory 210192 kb
Host smart-a96c49d8-4774-4631-a93b-62447dbdc93a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296199302 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.296199302
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.4015174019
Short name T520
Test name
Test status
Simulation time 533066037 ps
CPU time 1.96 seconds
Started May 28 02:24:00 PM PDT 24
Finished May 28 02:24:03 PM PDT 24
Peak memory 201556 kb
Host smart-60c0f0a9-bd5d-4634-a9eb-8e474edd6f7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015174019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.4015174019
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3361759169
Short name T476
Test name
Test status
Simulation time 330957510409 ps
CPU time 215.26 seconds
Started May 28 02:23:49 PM PDT 24
Finished May 28 02:27:26 PM PDT 24
Peak memory 201844 kb
Host smart-f17868eb-c471-47f7-88bf-34e419ea6f6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361759169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3361759169
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.4214375689
Short name T606
Test name
Test status
Simulation time 163723414320 ps
CPU time 391.56 seconds
Started May 28 02:23:49 PM PDT 24
Finished May 28 02:30:22 PM PDT 24
Peak memory 201832 kb
Host smart-d58af526-26df-48cb-8cf5-153a0de13d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214375689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.4214375689
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3172483867
Short name T423
Test name
Test status
Simulation time 323443943762 ps
CPU time 209.31 seconds
Started May 28 02:23:47 PM PDT 24
Finished May 28 02:27:18 PM PDT 24
Peak memory 201828 kb
Host smart-e794867e-ff11-4000-980a-8047f1004639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172483867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3172483867
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.634542857
Short name T780
Test name
Test status
Simulation time 492617480438 ps
CPU time 1158.94 seconds
Started May 28 02:23:48 PM PDT 24
Finished May 28 02:43:08 PM PDT 24
Peak memory 201856 kb
Host smart-e1caeaaa-c1e0-4eb6-92fd-631bd449cd6c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=634542857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.634542857
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.936557497
Short name T388
Test name
Test status
Simulation time 325160874348 ps
CPU time 196.07 seconds
Started May 28 02:23:53 PM PDT 24
Finished May 28 02:27:10 PM PDT 24
Peak memory 201856 kb
Host smart-650e9984-80ae-46a4-b0bc-076754e40694
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=936557497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.936557497
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2987992864
Short name T761
Test name
Test status
Simulation time 583679718861 ps
CPU time 1440.62 seconds
Started May 28 02:23:48 PM PDT 24
Finished May 28 02:47:50 PM PDT 24
Peak memory 201836 kb
Host smart-6c95350c-2630-409c-8b21-30f7cdab10b4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987992864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2987992864
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1066559404
Short name T57
Test name
Test status
Simulation time 103144695435 ps
CPU time 390.88 seconds
Started May 28 02:23:49 PM PDT 24
Finished May 28 02:30:21 PM PDT 24
Peak memory 202152 kb
Host smart-615d5381-4bdd-4548-9769-f5b74adb817d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066559404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1066559404
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.839269314
Short name T393
Test name
Test status
Simulation time 32371808100 ps
CPU time 37.25 seconds
Started May 28 02:23:49 PM PDT 24
Finished May 28 02:24:27 PM PDT 24
Peak memory 201648 kb
Host smart-4fc66c6a-947f-4272-b1ed-da60f80b990a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839269314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.839269314
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.424044306
Short name T362
Test name
Test status
Simulation time 3236583535 ps
CPU time 1.79 seconds
Started May 28 02:23:48 PM PDT 24
Finished May 28 02:23:51 PM PDT 24
Peak memory 201572 kb
Host smart-4b427f91-e066-45e2-bd58-af33a182f79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424044306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.424044306
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3944398321
Short name T623
Test name
Test status
Simulation time 5667556389 ps
CPU time 14.06 seconds
Started May 28 02:23:49 PM PDT 24
Finished May 28 02:24:04 PM PDT 24
Peak memory 201676 kb
Host smart-3216f576-4890-4e25-8844-6191c0737a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944398321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3944398321
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1342528988
Short name T589
Test name
Test status
Simulation time 264775495847 ps
CPU time 683.6 seconds
Started May 28 02:23:49 PM PDT 24
Finished May 28 02:35:13 PM PDT 24
Peak memory 210368 kb
Host smart-3ad63d72-35fd-44a2-90f2-b5e6b3d63699
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342528988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1342528988
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.481561292
Short name T436
Test name
Test status
Simulation time 58493319209 ps
CPU time 153.24 seconds
Started May 28 02:23:54 PM PDT 24
Finished May 28 02:26:28 PM PDT 24
Peak memory 211508 kb
Host smart-0d398765-aba8-45ef-869e-bdf6065f94ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481561292 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.481561292
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1844524350
Short name T78
Test name
Test status
Simulation time 434502211 ps
CPU time 1.69 seconds
Started May 28 02:24:13 PM PDT 24
Finished May 28 02:24:15 PM PDT 24
Peak memory 201548 kb
Host smart-1f678826-440e-4707-8c20-6da0a93660d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844524350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1844524350
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.4185286873
Short name T246
Test name
Test status
Simulation time 162727011750 ps
CPU time 379.32 seconds
Started May 28 02:24:00 PM PDT 24
Finished May 28 02:30:20 PM PDT 24
Peak memory 201700 kb
Host smart-630094b7-dc5b-44c1-9488-37da810eaf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185286873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.4185286873
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1403989655
Short name T535
Test name
Test status
Simulation time 162911300681 ps
CPU time 42.62 seconds
Started May 28 02:24:00 PM PDT 24
Finished May 28 02:24:44 PM PDT 24
Peak memory 201928 kb
Host smart-f73cef0c-cfba-4097-949c-2371b7c1e060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403989655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1403989655
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.316621155
Short name T271
Test name
Test status
Simulation time 325608330285 ps
CPU time 435.76 seconds
Started May 28 02:23:59 PM PDT 24
Finished May 28 02:31:15 PM PDT 24
Peak memory 201836 kb
Host smart-5e04f89d-b95e-4f43-a604-e1fb63d148b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=316621155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.316621155
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.1500602374
Short name T771
Test name
Test status
Simulation time 495221961078 ps
CPU time 287.85 seconds
Started May 28 02:23:58 PM PDT 24
Finished May 28 02:28:47 PM PDT 24
Peak memory 201824 kb
Host smart-2e12b0c8-af24-4b62-8144-53f88bdf444c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500602374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1500602374
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1692026209
Short name T47
Test name
Test status
Simulation time 494875076429 ps
CPU time 1239.57 seconds
Started May 28 02:23:59 PM PDT 24
Finished May 28 02:44:39 PM PDT 24
Peak memory 201812 kb
Host smart-fb761a57-6b89-495e-ac2e-2923715df56a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692026209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1692026209
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1988212981
Short name T314
Test name
Test status
Simulation time 455528115256 ps
CPU time 181.56 seconds
Started May 28 02:24:00 PM PDT 24
Finished May 28 02:27:02 PM PDT 24
Peak memory 201704 kb
Host smart-fc120d14-2aa4-4c30-bbfc-6695f23f9a4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988212981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1988212981
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1964124046
Short name T365
Test name
Test status
Simulation time 200382073144 ps
CPU time 118.1 seconds
Started May 28 02:23:59 PM PDT 24
Finished May 28 02:25:58 PM PDT 24
Peak memory 201860 kb
Host smart-71acd51c-4d74-4403-ab64-9c6f9a6551f8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964124046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1964124046
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3866819885
Short name T330
Test name
Test status
Simulation time 99191417047 ps
CPU time 561.26 seconds
Started May 28 02:24:11 PM PDT 24
Finished May 28 02:33:34 PM PDT 24
Peak memory 202168 kb
Host smart-76c89cfb-6ba2-4181-b3f1-5cbe5eab0e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866819885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3866819885
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1001879767
Short name T98
Test name
Test status
Simulation time 27443296507 ps
CPU time 59.28 seconds
Started May 28 02:24:12 PM PDT 24
Finished May 28 02:25:12 PM PDT 24
Peak memory 201684 kb
Host smart-13027403-0634-4995-add2-0eaa9e8d6bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001879767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1001879767
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2188856769
Short name T594
Test name
Test status
Simulation time 4830837970 ps
CPU time 2.51 seconds
Started May 28 02:24:10 PM PDT 24
Finished May 28 02:24:14 PM PDT 24
Peak memory 201900 kb
Host smart-94a1b0ec-f418-4a59-8f94-e9e2380ee03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188856769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2188856769
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.370043369
Short name T543
Test name
Test status
Simulation time 5931583125 ps
CPU time 3.99 seconds
Started May 28 02:23:59 PM PDT 24
Finished May 28 02:24:04 PM PDT 24
Peak memory 201668 kb
Host smart-6da37e17-e672-491f-8a4a-544092471670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370043369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.370043369
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.4179025506
Short name T708
Test name
Test status
Simulation time 4893149771 ps
CPU time 3.59 seconds
Started May 28 02:24:11 PM PDT 24
Finished May 28 02:24:15 PM PDT 24
Peak memory 201644 kb
Host smart-683f8736-8f3d-4541-8cd2-3fd454d81232
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179025506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.4179025506
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.311253016
Short name T15
Test name
Test status
Simulation time 119697889879 ps
CPU time 81.45 seconds
Started May 28 02:24:10 PM PDT 24
Finished May 28 02:25:33 PM PDT 24
Peak memory 210548 kb
Host smart-d4185bd5-2bd5-4376-9e1f-4bdf98c59376
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311253016 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.311253016
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1923884942
Short name T539
Test name
Test status
Simulation time 529778520 ps
CPU time 1.73 seconds
Started May 28 02:24:23 PM PDT 24
Finished May 28 02:24:26 PM PDT 24
Peak memory 201548 kb
Host smart-d7744c9e-8cee-4767-b1ed-3498f60dfd2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923884942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1923884942
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.982969514
Short name T244
Test name
Test status
Simulation time 539258708421 ps
CPU time 336.15 seconds
Started May 28 02:24:15 PM PDT 24
Finished May 28 02:29:52 PM PDT 24
Peak memory 201936 kb
Host smart-86b03aa4-4dbc-4d45-9a20-1abeac4ef459
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982969514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.982969514
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2271425240
Short name T774
Test name
Test status
Simulation time 347384088134 ps
CPU time 434.27 seconds
Started May 28 02:24:13 PM PDT 24
Finished May 28 02:31:28 PM PDT 24
Peak memory 201856 kb
Host smart-d551285c-eb92-4645-8c1d-cdadd48855ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271425240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2271425240
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3893439579
Short name T284
Test name
Test status
Simulation time 159243248025 ps
CPU time 388.13 seconds
Started May 28 02:24:13 PM PDT 24
Finished May 28 02:30:41 PM PDT 24
Peak memory 201816 kb
Host smart-2e37f6c5-8e21-449b-a89b-cf61baa51c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893439579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3893439579
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.1954564154
Short name T677
Test name
Test status
Simulation time 324899810382 ps
CPU time 769.24 seconds
Started May 28 02:24:10 PM PDT 24
Finished May 28 02:37:01 PM PDT 24
Peak memory 201844 kb
Host smart-53c55032-9a31-4d3d-8885-6a95695b9b86
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954564154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.1954564154
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.614225365
Short name T557
Test name
Test status
Simulation time 158151632287 ps
CPU time 94.4 seconds
Started May 28 02:24:11 PM PDT 24
Finished May 28 02:25:46 PM PDT 24
Peak memory 201920 kb
Host smart-8c51f865-0efe-43ec-b104-b8214238f461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614225365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.614225365
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1670091814
Short name T424
Test name
Test status
Simulation time 337045368553 ps
CPU time 86.42 seconds
Started May 28 02:24:11 PM PDT 24
Finished May 28 02:25:38 PM PDT 24
Peak memory 201876 kb
Host smart-fc3d95a6-2c50-4c6a-9548-e71183e664b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670091814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1670091814
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2911860473
Short name T282
Test name
Test status
Simulation time 371974970135 ps
CPU time 542.25 seconds
Started May 28 02:24:12 PM PDT 24
Finished May 28 02:33:15 PM PDT 24
Peak memory 201880 kb
Host smart-272c47b6-026a-40a4-b5bc-3832b851b9aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911860473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2911860473
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.4240352272
Short name T565
Test name
Test status
Simulation time 399645624339 ps
CPU time 468.44 seconds
Started May 28 02:24:11 PM PDT 24
Finished May 28 02:32:01 PM PDT 24
Peak memory 201856 kb
Host smart-5da55e8d-d822-4253-bf43-5817a2e755c1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240352272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.4240352272
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1061072655
Short name T195
Test name
Test status
Simulation time 145354648870 ps
CPU time 547.75 seconds
Started May 28 02:24:21 PM PDT 24
Finished May 28 02:33:30 PM PDT 24
Peak memory 202132 kb
Host smart-bec9fe1f-8f5c-48f4-9173-fcaaf1df3f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061072655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1061072655
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.4283552991
Short name T345
Test name
Test status
Simulation time 25054368011 ps
CPU time 60.59 seconds
Started May 28 02:24:23 PM PDT 24
Finished May 28 02:25:25 PM PDT 24
Peak memory 201688 kb
Host smart-ef9bd175-b3a3-41ec-ab16-b66fb35e3e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283552991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.4283552991
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2895259781
Short name T546
Test name
Test status
Simulation time 2737678707 ps
CPU time 2.47 seconds
Started May 28 02:24:11 PM PDT 24
Finished May 28 02:24:14 PM PDT 24
Peak memory 201420 kb
Host smart-5773deae-ad75-4f5f-9cbe-7844f75c31a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895259781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2895259781
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.329396043
Short name T739
Test name
Test status
Simulation time 5760274928 ps
CPU time 2.09 seconds
Started May 28 02:24:12 PM PDT 24
Finished May 28 02:24:15 PM PDT 24
Peak memory 201684 kb
Host smart-63e8c804-0a55-4ad2-88aa-18a60a8d7d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329396043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.329396043
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.8981070
Short name T190
Test name
Test status
Simulation time 217108457211 ps
CPU time 233.5 seconds
Started May 28 02:24:21 PM PDT 24
Finished May 28 02:28:15 PM PDT 24
Peak memory 201852 kb
Host smart-a54e8442-dfcc-4c1b-94a6-538103a243b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8981070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.8981070
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2939125655
Short name T37
Test name
Test status
Simulation time 45072569521 ps
CPU time 48.78 seconds
Started May 28 02:24:22 PM PDT 24
Finished May 28 02:25:12 PM PDT 24
Peak memory 202008 kb
Host smart-8e07617a-e328-44a8-bcc6-d2611e320ab3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939125655 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2939125655
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.694877718
Short name T655
Test name
Test status
Simulation time 491583491 ps
CPU time 0.89 seconds
Started May 28 02:24:32 PM PDT 24
Finished May 28 02:24:34 PM PDT 24
Peak memory 201552 kb
Host smart-034edb68-7ecd-45f3-9291-991757d99946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694877718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.694877718
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3015379182
Short name T250
Test name
Test status
Simulation time 461850270710 ps
CPU time 723.85 seconds
Started May 28 02:24:33 PM PDT 24
Finished May 28 02:36:38 PM PDT 24
Peak memory 201884 kb
Host smart-34de8740-a401-443f-a4de-aa2f535c1819
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015379182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3015379182
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1373446514
Short name T306
Test name
Test status
Simulation time 160280879681 ps
CPU time 113.44 seconds
Started May 28 02:24:32 PM PDT 24
Finished May 28 02:26:26 PM PDT 24
Peak memory 201848 kb
Host smart-52d6b98d-02a5-44f0-b51c-164039ef41aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373446514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1373446514
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.69137303
Short name T144
Test name
Test status
Simulation time 498133887467 ps
CPU time 88.07 seconds
Started May 28 02:24:21 PM PDT 24
Finished May 28 02:25:50 PM PDT 24
Peak memory 201856 kb
Host smart-7c34356b-9d67-4d3a-a2bf-99240971107c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69137303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.69137303
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.4159626390
Short name T607
Test name
Test status
Simulation time 164042629811 ps
CPU time 103.46 seconds
Started May 28 02:24:20 PM PDT 24
Finished May 28 02:26:05 PM PDT 24
Peak memory 201828 kb
Host smart-f461f309-d537-4575-8194-4e3e886b837d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159626390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.4159626390
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.985030433
Short name T2
Test name
Test status
Simulation time 161386732610 ps
CPU time 96.51 seconds
Started May 28 02:24:20 PM PDT 24
Finished May 28 02:25:58 PM PDT 24
Peak memory 201844 kb
Host smart-0858c3ee-48b0-4740-b438-f4254a9d27f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985030433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.985030433
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.676270446
Short name T449
Test name
Test status
Simulation time 161843833658 ps
CPU time 355.85 seconds
Started May 28 02:24:21 PM PDT 24
Finished May 28 02:30:18 PM PDT 24
Peak memory 201844 kb
Host smart-74fd00b7-5771-4b82-9f45-f8e30a7bd9fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=676270446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.676270446
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3196138106
Short name T791
Test name
Test status
Simulation time 608996938549 ps
CPU time 375.78 seconds
Started May 28 02:24:21 PM PDT 24
Finished May 28 02:30:38 PM PDT 24
Peak memory 201848 kb
Host smart-f6dac9c5-e3a3-415f-8905-19da4db655f4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196138106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3196138106
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.4202918721
Short name T435
Test name
Test status
Simulation time 80604387684 ps
CPU time 375.75 seconds
Started May 28 02:24:33 PM PDT 24
Finished May 28 02:30:50 PM PDT 24
Peak memory 202172 kb
Host smart-c2828f9d-e5a7-4cd8-9f8d-db9d2c1db48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202918721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.4202918721
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3903428462
Short name T678
Test name
Test status
Simulation time 38563189242 ps
CPU time 44.93 seconds
Started May 28 02:24:32 PM PDT 24
Finished May 28 02:25:17 PM PDT 24
Peak memory 201652 kb
Host smart-b43ff6d4-4002-4109-9a93-72533979d32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903428462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3903428462
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3543474610
Short name T104
Test name
Test status
Simulation time 4909920859 ps
CPU time 7.38 seconds
Started May 28 02:24:34 PM PDT 24
Finished May 28 02:24:43 PM PDT 24
Peak memory 201668 kb
Host smart-4bf5fba8-be37-477d-ac2d-54cc1ca757d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543474610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3543474610
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1412973397
Short name T508
Test name
Test status
Simulation time 6003402781 ps
CPU time 7.77 seconds
Started May 28 02:24:20 PM PDT 24
Finished May 28 02:24:29 PM PDT 24
Peak memory 201648 kb
Host smart-ac3075b8-d950-4332-8935-2ed710b5fb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412973397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1412973397
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.2674056965
Short name T670
Test name
Test status
Simulation time 336170769400 ps
CPU time 170.32 seconds
Started May 28 02:24:34 PM PDT 24
Finished May 28 02:27:25 PM PDT 24
Peak memory 201896 kb
Host smart-f332cc6c-0256-4239-ad99-962756203143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674056965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.2674056965
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.4074173753
Short name T767
Test name
Test status
Simulation time 276569993953 ps
CPU time 170.93 seconds
Started May 28 02:24:33 PM PDT 24
Finished May 28 02:27:25 PM PDT 24
Peak memory 212488 kb
Host smart-bb237350-4b77-41ba-a5f4-e78267687a55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074173753 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.4074173753
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3896293932
Short name T367
Test name
Test status
Simulation time 284034430 ps
CPU time 1.29 seconds
Started May 28 02:24:46 PM PDT 24
Finished May 28 02:24:49 PM PDT 24
Peak memory 201548 kb
Host smart-005a5419-ad4a-4c66-bc79-325863a2b69a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896293932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3896293932
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.889657722
Short name T554
Test name
Test status
Simulation time 171680831562 ps
CPU time 112.21 seconds
Started May 28 02:24:46 PM PDT 24
Finished May 28 02:26:39 PM PDT 24
Peak memory 201944 kb
Host smart-483e31a9-9834-47c9-9407-f7cfc861dd0f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889657722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.889657722
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2762090297
Short name T621
Test name
Test status
Simulation time 509246690668 ps
CPU time 645.02 seconds
Started May 28 02:24:46 PM PDT 24
Finished May 28 02:35:32 PM PDT 24
Peak memory 201844 kb
Host smart-757393bd-59f3-42b0-8004-09661fb16ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762090297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2762090297
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.905415922
Short name T785
Test name
Test status
Simulation time 492374373132 ps
CPU time 592.59 seconds
Started May 28 02:24:33 PM PDT 24
Finished May 28 02:34:27 PM PDT 24
Peak memory 201912 kb
Host smart-c68a3d76-3d5a-4908-9634-4584d0eeb343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905415922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.905415922
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.630857847
Short name T653
Test name
Test status
Simulation time 320265685241 ps
CPU time 784.54 seconds
Started May 28 02:24:33 PM PDT 24
Finished May 28 02:37:39 PM PDT 24
Peak memory 201784 kb
Host smart-42728d1e-4c27-453c-93c4-92e6bfae38c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=630857847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.630857847
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.4130493624
Short name T556
Test name
Test status
Simulation time 162285998700 ps
CPU time 395.13 seconds
Started May 28 02:24:34 PM PDT 24
Finished May 28 02:31:10 PM PDT 24
Peak memory 201888 kb
Host smart-931fa35e-defe-44e3-958f-04d5364ee366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130493624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.4130493624
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1140983991
Short name T360
Test name
Test status
Simulation time 170661508536 ps
CPU time 184.07 seconds
Started May 28 02:24:31 PM PDT 24
Finished May 28 02:27:36 PM PDT 24
Peak memory 202144 kb
Host smart-d50b2dec-2940-4974-a2ab-e34facc32825
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140983991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1140983991
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2404268656
Short name T208
Test name
Test status
Simulation time 583517631966 ps
CPU time 1305.92 seconds
Started May 28 02:24:33 PM PDT 24
Finished May 28 02:46:20 PM PDT 24
Peak memory 201908 kb
Host smart-c6460c21-9bd5-4eef-a9d0-8b878fbc8134
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404268656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2404268656
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3948129733
Short name T775
Test name
Test status
Simulation time 579389460047 ps
CPU time 720.95 seconds
Started May 28 02:24:34 PM PDT 24
Finished May 28 02:36:36 PM PDT 24
Peak memory 201832 kb
Host smart-6ee59c92-313f-4ebe-a618-48eef85dfe3d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948129733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3948129733
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3751872403
Short name T194
Test name
Test status
Simulation time 101016187161 ps
CPU time 453.22 seconds
Started May 28 02:24:45 PM PDT 24
Finished May 28 02:32:20 PM PDT 24
Peak memory 202152 kb
Host smart-071d171d-7128-4327-a434-f3fdbe4091e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751872403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3751872403
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3239929417
Short name T403
Test name
Test status
Simulation time 28222888594 ps
CPU time 66.59 seconds
Started May 28 02:24:45 PM PDT 24
Finished May 28 02:25:54 PM PDT 24
Peak memory 201684 kb
Host smart-5773316c-cf42-45e9-add6-bffc152406c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239929417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3239929417
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3235152240
Short name T596
Test name
Test status
Simulation time 4744421591 ps
CPU time 5.73 seconds
Started May 28 02:24:45 PM PDT 24
Finished May 28 02:24:53 PM PDT 24
Peak memory 201652 kb
Host smart-b7e5c1d7-e337-4c41-9119-e96ecadde052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235152240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3235152240
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.4194434671
Short name T340
Test name
Test status
Simulation time 6047394488 ps
CPU time 8.16 seconds
Started May 28 02:24:32 PM PDT 24
Finished May 28 02:24:41 PM PDT 24
Peak memory 201684 kb
Host smart-6cb6ee56-78d4-452c-a43f-fe43da439459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194434671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.4194434671
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2859480260
Short name T609
Test name
Test status
Simulation time 278537597876 ps
CPU time 741.94 seconds
Started May 28 02:24:45 PM PDT 24
Finished May 28 02:37:08 PM PDT 24
Peak memory 210532 kb
Host smart-09eabc1f-00d0-4f90-b254-33a79d2f9119
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859480260 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2859480260
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2622117807
Short name T625
Test name
Test status
Simulation time 459829011 ps
CPU time 0.9 seconds
Started May 28 02:25:01 PM PDT 24
Finished May 28 02:25:03 PM PDT 24
Peak memory 201540 kb
Host smart-22c74820-55de-4f0d-bc97-82448afb975c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622117807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2622117807
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.4259506118
Short name T413
Test name
Test status
Simulation time 496533152750 ps
CPU time 1044.29 seconds
Started May 28 02:24:46 PM PDT 24
Finished May 28 02:42:12 PM PDT 24
Peak memory 201848 kb
Host smart-d548bcb4-cb76-463f-93bb-5b57c938ff22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259506118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.4259506118
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2889862339
Short name T338
Test name
Test status
Simulation time 328607789928 ps
CPU time 798.2 seconds
Started May 28 02:24:47 PM PDT 24
Finished May 28 02:38:06 PM PDT 24
Peak memory 201824 kb
Host smart-1ffba5db-69c0-4040-af01-4215a91276d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889862339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2889862339
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1976863111
Short name T257
Test name
Test status
Simulation time 159702862978 ps
CPU time 345.28 seconds
Started May 28 02:24:44 PM PDT 24
Finished May 28 02:30:31 PM PDT 24
Peak memory 201832 kb
Host smart-07518f82-cc87-4a56-a6b4-c667c1cab81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976863111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1976863111
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1196394402
Short name T173
Test name
Test status
Simulation time 488383740225 ps
CPU time 1245.24 seconds
Started May 28 02:24:45 PM PDT 24
Finished May 28 02:45:32 PM PDT 24
Peak memory 201940 kb
Host smart-c9c87459-ef71-43b1-b7fe-e4cca4fb21d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196394402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1196394402
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1419180865
Short name T665
Test name
Test status
Simulation time 392790297424 ps
CPU time 912.96 seconds
Started May 28 02:24:58 PM PDT 24
Finished May 28 02:40:12 PM PDT 24
Peak memory 201816 kb
Host smart-d0cf0302-9b70-4050-8667-935d9b483195
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419180865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1419180865
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3786198752
Short name T430
Test name
Test status
Simulation time 145165911058 ps
CPU time 484.09 seconds
Started May 28 02:25:00 PM PDT 24
Finished May 28 02:33:05 PM PDT 24
Peak memory 202220 kb
Host smart-a249c174-990c-4677-b60e-30b744800c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786198752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3786198752
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3316244966
Short name T694
Test name
Test status
Simulation time 22073211986 ps
CPU time 53.87 seconds
Started May 28 02:24:57 PM PDT 24
Finished May 28 02:25:52 PM PDT 24
Peak memory 201924 kb
Host smart-de496a78-ad95-43f8-82a9-f37dc243d686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316244966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3316244966
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.994774003
Short name T765
Test name
Test status
Simulation time 4519115989 ps
CPU time 7.08 seconds
Started May 28 02:25:00 PM PDT 24
Finished May 28 02:25:08 PM PDT 24
Peak memory 201672 kb
Host smart-f510d18d-d361-48fe-8ce8-6b3fcf65dd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994774003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.994774003
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.370453583
Short name T769
Test name
Test status
Simulation time 5965961362 ps
CPU time 4.18 seconds
Started May 28 02:24:46 PM PDT 24
Finished May 28 02:24:52 PM PDT 24
Peak memory 201696 kb
Host smart-81fb3908-d777-4417-beee-18c0355ad9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370453583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.370453583
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2525197958
Short name T745
Test name
Test status
Simulation time 73926493573 ps
CPU time 84.78 seconds
Started May 28 02:25:00 PM PDT 24
Finished May 28 02:26:26 PM PDT 24
Peak memory 201652 kb
Host smart-8a1e5afc-59ec-49c4-8f3f-3ccf42c4e389
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525197958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2525197958
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.346256424
Short name T217
Test name
Test status
Simulation time 128299404975 ps
CPU time 76.68 seconds
Started May 28 02:24:59 PM PDT 24
Finished May 28 02:26:17 PM PDT 24
Peak memory 210144 kb
Host smart-b7468530-7f40-43eb-8134-b9bb6b77f28b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346256424 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.346256424
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2609793466
Short name T399
Test name
Test status
Simulation time 433382911 ps
CPU time 1.1 seconds
Started May 28 02:25:11 PM PDT 24
Finished May 28 02:25:14 PM PDT 24
Peak memory 201556 kb
Host smart-059dea96-d89e-4393-86a2-630e9e427510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609793466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2609793466
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1653191789
Short name T318
Test name
Test status
Simulation time 356432115270 ps
CPU time 418.74 seconds
Started May 28 02:25:10 PM PDT 24
Finished May 28 02:32:11 PM PDT 24
Peak memory 201848 kb
Host smart-cdf936f5-0816-4178-be5a-d8efeedecf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653191789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1653191789
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.18306868
Short name T716
Test name
Test status
Simulation time 494304108535 ps
CPU time 1092.88 seconds
Started May 28 02:24:59 PM PDT 24
Finished May 28 02:43:13 PM PDT 24
Peak memory 201848 kb
Host smart-1f9d48e6-6fa2-4123-8708-b3b328dccb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18306868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.18306868
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2087822978
Short name T592
Test name
Test status
Simulation time 328558051919 ps
CPU time 789.05 seconds
Started May 28 02:25:00 PM PDT 24
Finished May 28 02:38:10 PM PDT 24
Peak memory 201900 kb
Host smart-41c7a4de-06b3-45ca-9138-6878740bd07e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087822978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2087822978
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1196806137
Short name T147
Test name
Test status
Simulation time 333751314919 ps
CPU time 185.77 seconds
Started May 28 02:24:59 PM PDT 24
Finished May 28 02:28:05 PM PDT 24
Peak memory 201804 kb
Host smart-18ad3fc6-d45b-4dd0-924b-9813adb7f66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196806137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1196806137
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2806054261
Short name T416
Test name
Test status
Simulation time 486622776111 ps
CPU time 276.66 seconds
Started May 28 02:25:00 PM PDT 24
Finished May 28 02:29:38 PM PDT 24
Peak memory 201832 kb
Host smart-b88b58ab-4896-48e9-b166-e5f343615d2b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806054261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2806054261
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.559202262
Short name T636
Test name
Test status
Simulation time 175262743884 ps
CPU time 221.82 seconds
Started May 28 02:25:10 PM PDT 24
Finished May 28 02:28:54 PM PDT 24
Peak memory 201880 kb
Host smart-07be46aa-99b5-4b2d-8856-27d811161196
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559202262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.559202262
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.264327033
Short name T545
Test name
Test status
Simulation time 405285662660 ps
CPU time 844.88 seconds
Started May 28 02:25:11 PM PDT 24
Finished May 28 02:39:17 PM PDT 24
Peak memory 201860 kb
Host smart-82b14bff-f3b9-4108-a175-15a3a465c54e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264327033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.264327033
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2227264384
Short name T178
Test name
Test status
Simulation time 114938522583 ps
CPU time 447.22 seconds
Started May 28 02:25:09 PM PDT 24
Finished May 28 02:32:37 PM PDT 24
Peak memory 202216 kb
Host smart-d4f2a017-ffea-48a0-bfe5-0a176c246f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227264384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2227264384
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.2085627882
Short name T182
Test name
Test status
Simulation time 27781534444 ps
CPU time 16.22 seconds
Started May 28 02:25:10 PM PDT 24
Finished May 28 02:25:28 PM PDT 24
Peak memory 201536 kb
Host smart-600a7813-9a70-4bb7-bfe3-5a8cebef2663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085627882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.2085627882
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2451259230
Short name T101
Test name
Test status
Simulation time 4957424398 ps
CPU time 4.13 seconds
Started May 28 02:25:11 PM PDT 24
Finished May 28 02:25:16 PM PDT 24
Peak memory 201668 kb
Host smart-1f52acb6-4b21-40fd-a563-84eeb4e24573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451259230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2451259230
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2939424962
Short name T615
Test name
Test status
Simulation time 6167253899 ps
CPU time 7.96 seconds
Started May 28 02:25:01 PM PDT 24
Finished May 28 02:25:10 PM PDT 24
Peak memory 201488 kb
Host smart-23ce79a3-34e0-4f81-b5b6-f5aff35cdee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939424962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2939424962
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1171348156
Short name T649
Test name
Test status
Simulation time 4502963933692 ps
CPU time 3002.61 seconds
Started May 28 02:25:11 PM PDT 24
Finished May 28 03:15:15 PM PDT 24
Peak memory 202148 kb
Host smart-d9754cdd-9f50-42fb-9e03-aa50bf7c5fe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171348156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1171348156
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1782321095
Short name T762
Test name
Test status
Simulation time 26427453912 ps
CPU time 63.24 seconds
Started May 28 02:25:10 PM PDT 24
Finished May 28 02:26:15 PM PDT 24
Peak memory 210128 kb
Host smart-e60a96f6-19b3-41f7-b7b5-0e77829d56c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782321095 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1782321095
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.2821929784
Short name T529
Test name
Test status
Simulation time 513289491 ps
CPU time 1.79 seconds
Started May 28 02:25:24 PM PDT 24
Finished May 28 02:25:28 PM PDT 24
Peak memory 201556 kb
Host smart-50f7bfab-a3a8-4292-a932-3e71d0c30c61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821929784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.2821929784
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1896771438
Short name T310
Test name
Test status
Simulation time 164648966502 ps
CPU time 82.71 seconds
Started May 28 02:25:24 PM PDT 24
Finished May 28 02:26:48 PM PDT 24
Peak memory 201924 kb
Host smart-58ddb5d9-0846-48da-acd3-1ff34e73c3bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896771438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1896771438
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.232239380
Short name T179
Test name
Test status
Simulation time 499245803771 ps
CPU time 276.89 seconds
Started May 28 02:25:11 PM PDT 24
Finished May 28 02:29:49 PM PDT 24
Peak memory 201928 kb
Host smart-fb5b7926-668d-40ec-9491-cbd6bd745986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232239380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.232239380
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.107008243
Short name T28
Test name
Test status
Simulation time 165122829130 ps
CPU time 90.82 seconds
Started May 28 02:25:10 PM PDT 24
Finished May 28 02:26:42 PM PDT 24
Peak memory 201832 kb
Host smart-44191970-6c00-40aa-952a-926cac2e574e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=107008243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrup
t_fixed.107008243
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.848801820
Short name T634
Test name
Test status
Simulation time 492877882111 ps
CPU time 284.16 seconds
Started May 28 02:25:11 PM PDT 24
Finished May 28 02:29:57 PM PDT 24
Peak memory 201868 kb
Host smart-e89341b3-2167-4926-a09d-94d1cdd19105
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=848801820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.848801820
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.177264779
Short name T169
Test name
Test status
Simulation time 648276155529 ps
CPU time 194.78 seconds
Started May 28 02:25:23 PM PDT 24
Finished May 28 02:28:39 PM PDT 24
Peak memory 201924 kb
Host smart-63d5896c-d116-46c6-9db2-c99c5c2d1add
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177264779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.177264779
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1649795024
Short name T642
Test name
Test status
Simulation time 406743749622 ps
CPU time 242.41 seconds
Started May 28 02:25:23 PM PDT 24
Finished May 28 02:29:27 PM PDT 24
Peak memory 201892 kb
Host smart-0cee9180-9106-478a-b29f-aeefd0a03e83
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649795024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1649795024
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.4017522214
Short name T732
Test name
Test status
Simulation time 135502162633 ps
CPU time 476.84 seconds
Started May 28 02:25:24 PM PDT 24
Finished May 28 02:33:22 PM PDT 24
Peak memory 202128 kb
Host smart-201e1d68-2a7a-4165-b167-3addaab94576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017522214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.4017522214
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.4038167727
Short name T411
Test name
Test status
Simulation time 24267090452 ps
CPU time 52.49 seconds
Started May 28 02:25:25 PM PDT 24
Finished May 28 02:26:19 PM PDT 24
Peak memory 201680 kb
Host smart-fc39c391-6269-4845-aeba-356a581e4a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038167727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.4038167727
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.2055180171
Short name T507
Test name
Test status
Simulation time 4518138790 ps
CPU time 11.23 seconds
Started May 28 02:25:24 PM PDT 24
Finished May 28 02:25:36 PM PDT 24
Peak memory 201668 kb
Host smart-fc259d91-758c-4ff9-9093-1fc72998d7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055180171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2055180171
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.500363773
Short name T378
Test name
Test status
Simulation time 6108980975 ps
CPU time 4.76 seconds
Started May 28 02:25:11 PM PDT 24
Finished May 28 02:25:17 PM PDT 24
Peak memory 201684 kb
Host smart-34e8bd24-063e-4060-8b39-b2185d4356a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500363773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.500363773
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3373045050
Short name T51
Test name
Test status
Simulation time 52082333043 ps
CPU time 126.72 seconds
Started May 28 02:25:23 PM PDT 24
Finished May 28 02:27:30 PM PDT 24
Peak memory 210476 kb
Host smart-b9d1827a-9add-450d-9b76-f413558b3fdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373045050 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3373045050
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3281165741
Short name T658
Test name
Test status
Simulation time 302975370 ps
CPU time 1.04 seconds
Started May 28 02:20:13 PM PDT 24
Finished May 28 02:20:15 PM PDT 24
Peak memory 201540 kb
Host smart-810b8148-dee1-4e25-81eb-caba6ac430a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281165741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3281165741
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1297933185
Short name T488
Test name
Test status
Simulation time 325630985848 ps
CPU time 160.41 seconds
Started May 28 02:20:14 PM PDT 24
Finished May 28 02:22:56 PM PDT 24
Peak memory 201852 kb
Host smart-8d3fb94f-262f-48c2-a125-7cc67a4a4397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297933185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1297933185
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2602348808
Short name T666
Test name
Test status
Simulation time 502477942783 ps
CPU time 1199.03 seconds
Started May 28 02:20:12 PM PDT 24
Finished May 28 02:40:12 PM PDT 24
Peak memory 201840 kb
Host smart-2152db06-aca9-4d3c-98ba-0635efc2d067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602348808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2602348808
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3612820910
Short name T583
Test name
Test status
Simulation time 501932407850 ps
CPU time 1094.58 seconds
Started May 28 02:20:16 PM PDT 24
Finished May 28 02:38:32 PM PDT 24
Peak memory 201856 kb
Host smart-0032cd8e-f99c-44da-9e87-db872d5b0928
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612820910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3612820910
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.880815121
Short name T541
Test name
Test status
Simulation time 334075537967 ps
CPU time 827.15 seconds
Started May 28 02:19:57 PM PDT 24
Finished May 28 02:33:46 PM PDT 24
Peak memory 201844 kb
Host smart-d5a40c92-8e89-4bad-8cda-5c830f349309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880815121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.880815121
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3894215745
Short name T472
Test name
Test status
Simulation time 325410824539 ps
CPU time 195.1 seconds
Started May 28 02:19:57 PM PDT 24
Finished May 28 02:23:13 PM PDT 24
Peak memory 201868 kb
Host smart-c8a34632-1db2-4e82-8787-cad676b81f68
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894215745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3894215745
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3729813025
Short name T688
Test name
Test status
Simulation time 353136469264 ps
CPU time 813.62 seconds
Started May 28 02:20:13 PM PDT 24
Finished May 28 02:33:49 PM PDT 24
Peak memory 201940 kb
Host smart-568a82a9-0058-41e9-8248-263a0f624adf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729813025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3729813025
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1804725399
Short name T425
Test name
Test status
Simulation time 580450804347 ps
CPU time 352.02 seconds
Started May 28 02:20:12 PM PDT 24
Finished May 28 02:26:05 PM PDT 24
Peak memory 201816 kb
Host smart-f4d79dd2-a4d2-4494-bcad-fe9ec0dc6a34
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804725399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1804725399
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2076445581
Short name T381
Test name
Test status
Simulation time 23729994815 ps
CPU time 5.95 seconds
Started May 28 02:20:14 PM PDT 24
Finished May 28 02:20:21 PM PDT 24
Peak memory 201652 kb
Host smart-32176246-846e-4ea3-a175-d93f4db0a3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076445581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2076445581
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.148286067
Short name T447
Test name
Test status
Simulation time 3241761024 ps
CPU time 2.71 seconds
Started May 28 02:20:14 PM PDT 24
Finished May 28 02:20:19 PM PDT 24
Peak memory 201584 kb
Host smart-09d38c2a-9496-4057-887d-8286fc5fe405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148286067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.148286067
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3150712388
Short name T71
Test name
Test status
Simulation time 4692799988 ps
CPU time 3.65 seconds
Started May 28 02:20:13 PM PDT 24
Finished May 28 02:20:17 PM PDT 24
Peak memory 217352 kb
Host smart-2fb6375c-a3b5-4dd3-9f55-ae6c3e0ef4c0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150712388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3150712388
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3748900907
Short name T177
Test name
Test status
Simulation time 5479427452 ps
CPU time 2.41 seconds
Started May 28 02:19:57 PM PDT 24
Finished May 28 02:20:02 PM PDT 24
Peak memory 201652 kb
Host smart-96410ca9-941e-4e47-a426-777b4d0422b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748900907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3748900907
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2420443008
Short name T776
Test name
Test status
Simulation time 40215478966 ps
CPU time 42.19 seconds
Started May 28 02:20:15 PM PDT 24
Finished May 28 02:20:58 PM PDT 24
Peak memory 201928 kb
Host smart-979b40a7-d3aa-4ea0-9e57-82bd195e854c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420443008 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2420443008
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1538020540
Short name T348
Test name
Test status
Simulation time 323107118 ps
CPU time 0.82 seconds
Started May 28 02:25:34 PM PDT 24
Finished May 28 02:25:35 PM PDT 24
Peak memory 201528 kb
Host smart-71fbf37d-e353-415d-b9b5-87742ed35d50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538020540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1538020540
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1117518325
Short name T188
Test name
Test status
Simulation time 489614524800 ps
CPU time 612.09 seconds
Started May 28 02:25:35 PM PDT 24
Finished May 28 02:35:48 PM PDT 24
Peak memory 201832 kb
Host smart-27d6e826-9f83-4e49-a3ad-23e68f4f8885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117518325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1117518325
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.963155588
Short name T782
Test name
Test status
Simulation time 336019312426 ps
CPU time 760.77 seconds
Started May 28 02:25:24 PM PDT 24
Finished May 28 02:38:06 PM PDT 24
Peak memory 201916 kb
Host smart-5b08bf52-eaa5-4d87-8cff-7836d7b3b0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963155588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.963155588
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.4063880397
Short name T337
Test name
Test status
Simulation time 331268155184 ps
CPU time 224.32 seconds
Started May 28 02:25:25 PM PDT 24
Finished May 28 02:29:11 PM PDT 24
Peak memory 201844 kb
Host smart-0fe529f0-bd3e-4ee3-8e9a-3e4d08d91790
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063880397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.4063880397
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3499352032
Short name T466
Test name
Test status
Simulation time 162545046126 ps
CPU time 113.3 seconds
Started May 28 02:25:24 PM PDT 24
Finished May 28 02:27:19 PM PDT 24
Peak memory 201816 kb
Host smart-d93c515a-8146-4df6-9d63-97005eec2426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499352032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3499352032
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.426609017
Short name T661
Test name
Test status
Simulation time 496633559586 ps
CPU time 1108.47 seconds
Started May 28 02:25:25 PM PDT 24
Finished May 28 02:43:55 PM PDT 24
Peak memory 201932 kb
Host smart-7f8cbbc4-d9cf-4bba-87ce-7ad3922ea686
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=426609017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.426609017
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3645935678
Short name T228
Test name
Test status
Simulation time 182979324049 ps
CPU time 111.21 seconds
Started May 28 02:25:35 PM PDT 24
Finished May 28 02:27:27 PM PDT 24
Peak memory 201868 kb
Host smart-d39a8e59-0a21-456a-9480-21b1e5c3f026
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645935678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3645935678
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3582681513
Short name T616
Test name
Test status
Simulation time 612786362296 ps
CPU time 788.83 seconds
Started May 28 02:25:35 PM PDT 24
Finished May 28 02:38:45 PM PDT 24
Peak memory 201840 kb
Host smart-176e5959-63c7-4506-adcb-005fee472e5a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582681513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3582681513
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.4175054197
Short name T534
Test name
Test status
Simulation time 65913152290 ps
CPU time 254.84 seconds
Started May 28 02:25:36 PM PDT 24
Finished May 28 02:29:52 PM PDT 24
Peak memory 202036 kb
Host smart-a2187674-6fc2-4457-8a15-684b903efb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175054197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.4175054197
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1560683256
Short name T786
Test name
Test status
Simulation time 42637728174 ps
CPU time 24.21 seconds
Started May 28 02:25:34 PM PDT 24
Finished May 28 02:25:59 PM PDT 24
Peak memory 201688 kb
Host smart-ba1a2daf-f279-44c6-923e-26e0fd855b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560683256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1560683256
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1615382596
Short name T467
Test name
Test status
Simulation time 4277063527 ps
CPU time 10.23 seconds
Started May 28 02:25:35 PM PDT 24
Finished May 28 02:25:47 PM PDT 24
Peak memory 201576 kb
Host smart-827e87df-4f67-4cd6-a486-fe46005d23be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615382596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1615382596
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3318062444
Short name T382
Test name
Test status
Simulation time 5929602131 ps
CPU time 15.33 seconds
Started May 28 02:25:23 PM PDT 24
Finished May 28 02:25:39 PM PDT 24
Peak memory 201672 kb
Host smart-d4fafac5-cb42-4731-93ee-4a1552d0dd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318062444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3318062444
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.4239681758
Short name T683
Test name
Test status
Simulation time 24628517169 ps
CPU time 72.58 seconds
Started May 28 02:25:36 PM PDT 24
Finished May 28 02:26:50 PM PDT 24
Peak memory 210468 kb
Host smart-472e4583-ab20-445f-a66b-bee264b77d78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239681758 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.4239681758
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.617391027
Short name T380
Test name
Test status
Simulation time 293094475 ps
CPU time 0.8 seconds
Started May 28 02:26:00 PM PDT 24
Finished May 28 02:26:03 PM PDT 24
Peak memory 201572 kb
Host smart-593a4b3c-93bf-465b-b1aa-ed366acc648e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617391027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.617391027
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.570206937
Short name T233
Test name
Test status
Simulation time 372765244258 ps
CPU time 509.62 seconds
Started May 28 02:25:48 PM PDT 24
Finished May 28 02:34:19 PM PDT 24
Peak memory 201932 kb
Host smart-854bb95a-e65b-4395-948f-8e4bb715f0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570206937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.570206937
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.3790383387
Short name T295
Test name
Test status
Simulation time 488364091105 ps
CPU time 315.9 seconds
Started May 28 02:25:47 PM PDT 24
Finished May 28 02:31:04 PM PDT 24
Peak memory 201852 kb
Host smart-2e4a3902-6d37-4e3a-9713-96a150e83857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790383387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3790383387
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.4272251748
Short name T30
Test name
Test status
Simulation time 492265837916 ps
CPU time 290.17 seconds
Started May 28 02:25:53 PM PDT 24
Finished May 28 02:30:44 PM PDT 24
Peak memory 201832 kb
Host smart-e6268b5d-a2fb-4143-851a-23dae9e9b9d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272251748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.4272251748
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1388321801
Short name T24
Test name
Test status
Simulation time 498614830624 ps
CPU time 294.45 seconds
Started May 28 02:25:49 PM PDT 24
Finished May 28 02:30:44 PM PDT 24
Peak memory 201824 kb
Host smart-eb49409c-9893-45a8-9fae-0f8c709112f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388321801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1388321801
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1080799412
Short name T355
Test name
Test status
Simulation time 322959602804 ps
CPU time 720.46 seconds
Started May 28 02:25:48 PM PDT 24
Finished May 28 02:37:50 PM PDT 24
Peak memory 201848 kb
Host smart-9ccab87e-0960-42fe-a5b6-1c5432fc8a31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080799412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.1080799412
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2320940600
Short name T478
Test name
Test status
Simulation time 618332711079 ps
CPU time 737.74 seconds
Started May 28 02:25:53 PM PDT 24
Finished May 28 02:38:12 PM PDT 24
Peak memory 201916 kb
Host smart-492ff460-1772-46cd-acf8-2c44fdb65cb4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320940600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2320940600
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3337440944
Short name T728
Test name
Test status
Simulation time 612820074640 ps
CPU time 682.28 seconds
Started May 28 02:25:48 PM PDT 24
Finished May 28 02:37:12 PM PDT 24
Peak memory 201856 kb
Host smart-fb1a6f98-3f61-496e-bc7f-8574bbc0a45c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337440944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3337440944
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.697752695
Short name T432
Test name
Test status
Simulation time 77916885646 ps
CPU time 440.32 seconds
Started May 28 02:26:00 PM PDT 24
Finished May 28 02:33:22 PM PDT 24
Peak memory 202236 kb
Host smart-281dbaa8-628d-4474-b8a1-bc8b87a98734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697752695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.697752695
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2435032330
Short name T659
Test name
Test status
Simulation time 40578678847 ps
CPU time 17.74 seconds
Started May 28 02:25:55 PM PDT 24
Finished May 28 02:26:13 PM PDT 24
Peak memory 201672 kb
Host smart-45f64147-cfbb-4d7c-88ce-ef0638980f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435032330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2435032330
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3600784926
Short name T460
Test name
Test status
Simulation time 4086286702 ps
CPU time 3.57 seconds
Started May 28 02:25:48 PM PDT 24
Finished May 28 02:25:53 PM PDT 24
Peak memory 201616 kb
Host smart-136dd77a-bc33-4da3-b825-afc1a909da1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600784926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3600784926
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1492401709
Short name T86
Test name
Test status
Simulation time 5847472757 ps
CPU time 13.26 seconds
Started May 28 02:25:48 PM PDT 24
Finished May 28 02:26:03 PM PDT 24
Peak memory 201488 kb
Host smart-d8642225-373e-496a-a669-2e1acbf2d704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492401709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1492401709
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3149664400
Short name T35
Test name
Test status
Simulation time 446272184566 ps
CPU time 1019.08 seconds
Started May 28 02:26:00 PM PDT 24
Finished May 28 02:43:00 PM PDT 24
Peak memory 201840 kb
Host smart-54fe04cb-5d0b-4d77-b622-f4a2d7cd6804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149664400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3149664400
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1678239827
Short name T749
Test name
Test status
Simulation time 352960565 ps
CPU time 0.72 seconds
Started May 28 02:25:59 PM PDT 24
Finished May 28 02:26:00 PM PDT 24
Peak memory 201528 kb
Host smart-1f42218a-5d19-4d64-8779-ae25ab91dbda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678239827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1678239827
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.1802787626
Short name T305
Test name
Test status
Simulation time 168269327030 ps
CPU time 415.58 seconds
Started May 28 02:25:59 PM PDT 24
Finished May 28 02:32:56 PM PDT 24
Peak memory 201924 kb
Host smart-bc815f7f-566e-4492-8e2b-ceec217fbaf6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802787626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.1802787626
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2584809252
Short name T214
Test name
Test status
Simulation time 505641204899 ps
CPU time 291.83 seconds
Started May 28 02:26:08 PM PDT 24
Finished May 28 02:31:01 PM PDT 24
Peak memory 201700 kb
Host smart-b7d7e448-6fbb-44c8-b95a-66078e9f2a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584809252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2584809252
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2716953807
Short name T317
Test name
Test status
Simulation time 164288763820 ps
CPU time 372.49 seconds
Started May 28 02:25:59 PM PDT 24
Finished May 28 02:32:12 PM PDT 24
Peak memory 201844 kb
Host smart-b807dbe5-d100-4277-9f2f-513d06cb6c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716953807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2716953807
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2446543739
Short name T439
Test name
Test status
Simulation time 164087135485 ps
CPU time 202.4 seconds
Started May 28 02:26:00 PM PDT 24
Finished May 28 02:29:24 PM PDT 24
Peak memory 201804 kb
Host smart-8b8340d8-eb73-4fb6-b359-5cf9c040f018
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446543739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2446543739
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1820032766
Short name T272
Test name
Test status
Simulation time 490419951699 ps
CPU time 1097.21 seconds
Started May 28 02:26:07 PM PDT 24
Finished May 28 02:44:25 PM PDT 24
Peak memory 201708 kb
Host smart-9f4831f3-b292-4d95-8307-09a5693fabf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820032766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1820032766
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3295258369
Short name T487
Test name
Test status
Simulation time 165723442198 ps
CPU time 408.42 seconds
Started May 28 02:26:01 PM PDT 24
Finished May 28 02:32:51 PM PDT 24
Peak memory 201820 kb
Host smart-a924e675-c794-4a4c-952d-e2d2791b68e7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295258369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3295258369
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.424428262
Short name T6
Test name
Test status
Simulation time 192593672682 ps
CPU time 410.69 seconds
Started May 28 02:26:01 PM PDT 24
Finished May 28 02:32:53 PM PDT 24
Peak memory 201936 kb
Host smart-d0c2b6b5-e619-483d-8d5d-6a0c58822e30
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424428262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.424428262
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.4205049775
Short name T525
Test name
Test status
Simulation time 397675763704 ps
CPU time 918.15 seconds
Started May 28 02:26:01 PM PDT 24
Finished May 28 02:41:20 PM PDT 24
Peak memory 201904 kb
Host smart-1a919255-d4d3-44ca-b34b-5629da26e51e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205049775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.4205049775
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.543522757
Short name T328
Test name
Test status
Simulation time 121132027204 ps
CPU time 384.84 seconds
Started May 28 02:26:00 PM PDT 24
Finished May 28 02:32:26 PM PDT 24
Peak memory 202144 kb
Host smart-68e8b35e-7bf4-490a-b341-04ca636849f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543522757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.543522757
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.516263110
Short name T768
Test name
Test status
Simulation time 29364389175 ps
CPU time 6.63 seconds
Started May 28 02:26:01 PM PDT 24
Finished May 28 02:26:09 PM PDT 24
Peak memory 201676 kb
Host smart-0fcff74b-62aa-4875-b117-911e8414ad9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516263110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.516263110
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.962531833
Short name T32
Test name
Test status
Simulation time 3388791917 ps
CPU time 8.32 seconds
Started May 28 02:26:08 PM PDT 24
Finished May 28 02:26:17 PM PDT 24
Peak memory 201444 kb
Host smart-1725d771-0a73-41a6-acf8-42a4d9f8c7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962531833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.962531833
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.195253225
Short name T343
Test name
Test status
Simulation time 5999826131 ps
CPU time 4.38 seconds
Started May 28 02:26:00 PM PDT 24
Finished May 28 02:26:06 PM PDT 24
Peak memory 201920 kb
Host smart-38309ce4-87bb-4a0c-bbe5-b87e3d3f79d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195253225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.195253225
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.4260961236
Short name T235
Test name
Test status
Simulation time 578166194899 ps
CPU time 1333.24 seconds
Started May 28 02:26:06 PM PDT 24
Finished May 28 02:48:20 PM PDT 24
Peak memory 201776 kb
Host smart-2909ce5b-0d56-4a75-861c-27cf7e30580a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260961236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.4260961236
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1048869160
Short name T605
Test name
Test status
Simulation time 459026884 ps
CPU time 0.91 seconds
Started May 28 02:26:23 PM PDT 24
Finished May 28 02:26:25 PM PDT 24
Peak memory 201536 kb
Host smart-448b9245-148b-494a-b36a-7f8fa0b71c3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048869160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1048869160
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.249075641
Short name T249
Test name
Test status
Simulation time 487323032477 ps
CPU time 291.69 seconds
Started May 28 02:26:16 PM PDT 24
Finished May 28 02:31:09 PM PDT 24
Peak memory 201716 kb
Host smart-42683dd4-0609-4688-a34a-fc61de9a22de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249075641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.249075641
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.709155504
Short name T789
Test name
Test status
Simulation time 158865626618 ps
CPU time 53.71 seconds
Started May 28 02:26:13 PM PDT 24
Finished May 28 02:27:08 PM PDT 24
Peak memory 201852 kb
Host smart-ccfa81df-dc28-4271-91fd-265945f10b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709155504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.709155504
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.4028379311
Short name T293
Test name
Test status
Simulation time 164875082121 ps
CPU time 405.07 seconds
Started May 28 02:26:11 PM PDT 24
Finished May 28 02:32:57 PM PDT 24
Peak memory 201920 kb
Host smart-e18597fe-d107-4033-b1f8-7d6a7686fdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028379311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.4028379311
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2575578019
Short name T453
Test name
Test status
Simulation time 491434771974 ps
CPU time 604.47 seconds
Started May 28 02:26:12 PM PDT 24
Finished May 28 02:36:17 PM PDT 24
Peak memory 201836 kb
Host smart-49f24512-eb55-4c9d-9bfa-24e0798f02e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575578019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2575578019
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1693590963
Short name T414
Test name
Test status
Simulation time 496142751361 ps
CPU time 193.21 seconds
Started May 28 02:25:59 PM PDT 24
Finished May 28 02:29:14 PM PDT 24
Peak memory 201840 kb
Host smart-61b73e54-4d41-4447-93e0-a2cb53ee524d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693590963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1693590963
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3736399299
Short name T434
Test name
Test status
Simulation time 163801624653 ps
CPU time 383.66 seconds
Started May 28 02:26:02 PM PDT 24
Finished May 28 02:32:27 PM PDT 24
Peak memory 201824 kb
Host smart-a576db72-9b7c-422f-b73b-fd95100d5e22
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736399299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3736399299
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2685369253
Short name T281
Test name
Test status
Simulation time 519372463501 ps
CPU time 1110.07 seconds
Started May 28 02:26:13 PM PDT 24
Finished May 28 02:44:44 PM PDT 24
Peak memory 201848 kb
Host smart-d7d2feb6-7296-4c15-a47d-22e920573565
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685369253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2685369253
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.588716356
Short name T371
Test name
Test status
Simulation time 604106913118 ps
CPU time 1292.63 seconds
Started May 28 02:26:13 PM PDT 24
Finished May 28 02:47:46 PM PDT 24
Peak memory 201932 kb
Host smart-3e27deb1-1ce7-460f-9400-525ce349d040
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588716356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.588716356
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2378717648
Short name T193
Test name
Test status
Simulation time 114825910168 ps
CPU time 404.55 seconds
Started May 28 02:26:12 PM PDT 24
Finished May 28 02:32:58 PM PDT 24
Peak memory 202224 kb
Host smart-23138490-4448-46ba-b24a-0339d42543a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378717648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2378717648
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3066383059
Short name T523
Test name
Test status
Simulation time 46350716783 ps
CPU time 106.51 seconds
Started May 28 02:26:12 PM PDT 24
Finished May 28 02:27:59 PM PDT 24
Peak memory 201684 kb
Host smart-80ccc239-d42e-4ecd-a050-14fd19c3c6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066383059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3066383059
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3898637468
Short name T468
Test name
Test status
Simulation time 3365631677 ps
CPU time 8.88 seconds
Started May 28 02:26:12 PM PDT 24
Finished May 28 02:26:22 PM PDT 24
Peak memory 201600 kb
Host smart-61022103-a701-485c-aedf-8386d3114b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898637468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3898637468
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1671215159
Short name T582
Test name
Test status
Simulation time 5774317644 ps
CPU time 14.88 seconds
Started May 28 02:26:01 PM PDT 24
Finished May 28 02:26:17 PM PDT 24
Peak memory 201672 kb
Host smart-bcad897a-d0bc-4ff7-890c-ea35fc24442b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671215159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1671215159
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1737206098
Short name T258
Test name
Test status
Simulation time 562672094938 ps
CPU time 383.9 seconds
Started May 28 02:26:23 PM PDT 24
Finished May 28 02:32:48 PM PDT 24
Peak memory 201852 kb
Host smart-1caa3427-0295-4079-a477-ffc68edf2bf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737206098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1737206098
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3082436219
Short name T21
Test name
Test status
Simulation time 57118483139 ps
CPU time 130.55 seconds
Started May 28 02:26:10 PM PDT 24
Finished May 28 02:28:22 PM PDT 24
Peak memory 218412 kb
Host smart-b85823a1-2823-488c-a14f-8d8401d9bb98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082436219 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3082436219
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2484613901
Short name T517
Test name
Test status
Simulation time 337631047 ps
CPU time 0.81 seconds
Started May 28 02:26:36 PM PDT 24
Finished May 28 02:26:38 PM PDT 24
Peak memory 201544 kb
Host smart-c0e9d3c3-b596-4216-9f7c-3c4a6171fa79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484613901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2484613901
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3560383737
Short name T727
Test name
Test status
Simulation time 163282645089 ps
CPU time 195 seconds
Started May 28 02:26:23 PM PDT 24
Finished May 28 02:29:40 PM PDT 24
Peak memory 201912 kb
Host smart-1522e191-16de-4f48-978e-3ef5a95b6ba9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560383737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3560383737
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1032729577
Short name T131
Test name
Test status
Simulation time 581572053387 ps
CPU time 1460.29 seconds
Started May 28 02:26:24 PM PDT 24
Finished May 28 02:50:47 PM PDT 24
Peak memory 201700 kb
Host smart-f3951643-06ba-4b36-b310-3c6169f5ca45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032729577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1032729577
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.166911251
Short name T664
Test name
Test status
Simulation time 163629022573 ps
CPU time 381.73 seconds
Started May 28 02:26:25 PM PDT 24
Finished May 28 02:32:49 PM PDT 24
Peak memory 201856 kb
Host smart-92fb102a-a36a-472c-911f-89731ca17560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166911251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.166911251
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3007029908
Short name T709
Test name
Test status
Simulation time 327006547832 ps
CPU time 190.41 seconds
Started May 28 02:26:22 PM PDT 24
Finished May 28 02:29:33 PM PDT 24
Peak memory 201824 kb
Host smart-5490df71-c78e-45b4-af04-075bb92ba353
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007029908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3007029908
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1438022559
Short name T704
Test name
Test status
Simulation time 164309584810 ps
CPU time 186.12 seconds
Started May 28 02:26:24 PM PDT 24
Finished May 28 02:29:32 PM PDT 24
Peak memory 201868 kb
Host smart-e96a0477-0b47-4e6d-9796-b1c341f20aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438022559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1438022559
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3531558226
Short name T445
Test name
Test status
Simulation time 489264474117 ps
CPU time 251.24 seconds
Started May 28 02:26:25 PM PDT 24
Finished May 28 02:30:38 PM PDT 24
Peak memory 201848 kb
Host smart-77ff8a61-a6fc-43f8-8e90-2992eba8ebb9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531558226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3531558226
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.245937613
Short name T540
Test name
Test status
Simulation time 212551468528 ps
CPU time 443.14 seconds
Started May 28 02:26:24 PM PDT 24
Finished May 28 02:33:49 PM PDT 24
Peak memory 201852 kb
Host smart-acb8e491-994a-40e3-8c7b-d6b4f266d6f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245937613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.245937613
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1795261841
Short name T356
Test name
Test status
Simulation time 585947360816 ps
CPU time 306.68 seconds
Started May 28 02:26:23 PM PDT 24
Finished May 28 02:31:31 PM PDT 24
Peak memory 201924 kb
Host smart-53a566c4-145c-4d30-b500-b7fba1e760c0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795261841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1795261841
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3689284869
Short name T327
Test name
Test status
Simulation time 101629427938 ps
CPU time 505.77 seconds
Started May 28 02:26:24 PM PDT 24
Finished May 28 02:34:52 PM PDT 24
Peak memory 202156 kb
Host smart-ddc0468f-bb29-4b25-8cd9-a9217b7bcb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689284869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3689284869
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2094349045
Short name T470
Test name
Test status
Simulation time 24235785487 ps
CPU time 28.81 seconds
Started May 28 02:26:25 PM PDT 24
Finished May 28 02:26:56 PM PDT 24
Peak memory 201636 kb
Host smart-af3590ab-cc51-4923-bf45-4c1473d65873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094349045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2094349045
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2658610135
Short name T176
Test name
Test status
Simulation time 4798065008 ps
CPU time 3.24 seconds
Started May 28 02:26:24 PM PDT 24
Finished May 28 02:26:29 PM PDT 24
Peak memory 201660 kb
Host smart-3cfd3bce-06f1-4423-95e0-908ebc151e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658610135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2658610135
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.103832121
Short name T698
Test name
Test status
Simulation time 6069785320 ps
CPU time 14.39 seconds
Started May 28 02:26:23 PM PDT 24
Finished May 28 02:26:39 PM PDT 24
Peak memory 201688 kb
Host smart-a5bb1c7b-4d7f-4a19-be99-033c05dbbb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103832121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.103832121
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2893503428
Short name T760
Test name
Test status
Simulation time 166628904956 ps
CPU time 152.96 seconds
Started May 28 02:26:23 PM PDT 24
Finished May 28 02:28:58 PM PDT 24
Peak memory 201848 kb
Host smart-4bc135b4-e95f-4803-9f8b-d9ce553ce9b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893503428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2893503428
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.829744989
Short name T777
Test name
Test status
Simulation time 81939656773 ps
CPU time 126.49 seconds
Started May 28 02:26:24 PM PDT 24
Finished May 28 02:28:32 PM PDT 24
Peak memory 210532 kb
Host smart-dc24c91e-17c1-4c6e-8057-95faa0271a0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829744989 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.829744989
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1550298197
Short name T491
Test name
Test status
Simulation time 551850769 ps
CPU time 0.83 seconds
Started May 28 02:26:45 PM PDT 24
Finished May 28 02:26:46 PM PDT 24
Peak memory 201556 kb
Host smart-3203f9f2-eac6-452e-aea7-fe6d489ba41d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550298197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1550298197
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1898690071
Short name T89
Test name
Test status
Simulation time 162227111086 ps
CPU time 99.16 seconds
Started May 28 02:26:37 PM PDT 24
Finished May 28 02:28:17 PM PDT 24
Peak memory 201820 kb
Host smart-8c2a785b-cc22-4fc5-ad61-0814cf9661d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898690071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1898690071
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3291383193
Short name T530
Test name
Test status
Simulation time 493303841640 ps
CPU time 337.07 seconds
Started May 28 02:26:34 PM PDT 24
Finished May 28 02:32:12 PM PDT 24
Peak memory 201840 kb
Host smart-382a7a8f-6640-4594-9294-8bfdd4fdbb43
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291383193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3291383193
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.712587300
Short name T584
Test name
Test status
Simulation time 485301981259 ps
CPU time 566.12 seconds
Started May 28 02:26:34 PM PDT 24
Finished May 28 02:36:01 PM PDT 24
Peak memory 201840 kb
Host smart-395edad2-b990-43c3-b44b-a084092276e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712587300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.712587300
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.797914235
Short name T473
Test name
Test status
Simulation time 321562696132 ps
CPU time 385.85 seconds
Started May 28 02:26:34 PM PDT 24
Finished May 28 02:33:01 PM PDT 24
Peak memory 201892 kb
Host smart-7b2696d6-ea45-458c-99d7-6192be94bc80
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=797914235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.797914235
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3068104868
Short name T296
Test name
Test status
Simulation time 344342561555 ps
CPU time 737.23 seconds
Started May 28 02:26:35 PM PDT 24
Finished May 28 02:38:53 PM PDT 24
Peak memory 201916 kb
Host smart-9e3cf0c8-c075-4a3b-b283-7e954604c128
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068104868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3068104868
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.787388457
Short name T637
Test name
Test status
Simulation time 595328725990 ps
CPU time 1278.23 seconds
Started May 28 02:26:36 PM PDT 24
Finished May 28 02:47:56 PM PDT 24
Peak memory 201860 kb
Host smart-e36ee7b6-7332-47de-84b3-83ad62e51d47
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787388457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.787388457
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2942170500
Short name T58
Test name
Test status
Simulation time 71990236724 ps
CPU time 393.55 seconds
Started May 28 02:26:46 PM PDT 24
Finished May 28 02:33:20 PM PDT 24
Peak memory 202220 kb
Host smart-1ee35937-80ec-44cc-9f84-68911cb184a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942170500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2942170500
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.791550210
Short name T392
Test name
Test status
Simulation time 29718182767 ps
CPU time 18.08 seconds
Started May 28 02:26:44 PM PDT 24
Finished May 28 02:27:03 PM PDT 24
Peak memory 201660 kb
Host smart-946bc43a-fd8b-4c91-ba4f-09f6538964f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791550210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.791550210
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1069962850
Short name T542
Test name
Test status
Simulation time 5116848223 ps
CPU time 6.78 seconds
Started May 28 02:26:35 PM PDT 24
Finished May 28 02:26:43 PM PDT 24
Peak memory 201656 kb
Host smart-81f3637c-c46e-46c6-b44a-396f9ca7b438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069962850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1069962850
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.333566441
Short name T734
Test name
Test status
Simulation time 5983686755 ps
CPU time 8.05 seconds
Started May 28 02:26:35 PM PDT 24
Finished May 28 02:26:44 PM PDT 24
Peak memory 201708 kb
Host smart-c783eadc-885e-4973-9cc1-480a6c972596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333566441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.333566441
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1583546595
Short name T278
Test name
Test status
Simulation time 173829197992 ps
CPU time 123.44 seconds
Started May 28 02:26:48 PM PDT 24
Finished May 28 02:28:52 PM PDT 24
Peak memory 202092 kb
Host smart-b64b6932-a3d8-42d8-b94c-bd2ac8281ef4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583546595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1583546595
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.633264012
Short name T687
Test name
Test status
Simulation time 1710623918170 ps
CPU time 548.77 seconds
Started May 28 02:26:46 PM PDT 24
Finished May 28 02:35:56 PM PDT 24
Peak memory 210524 kb
Host smart-70dcaf09-e947-40a2-a5ed-c4959247b3de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633264012 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.633264012
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3400630201
Short name T479
Test name
Test status
Simulation time 390404301 ps
CPU time 0.88 seconds
Started May 28 02:26:59 PM PDT 24
Finished May 28 02:27:01 PM PDT 24
Peak memory 201552 kb
Host smart-53446afe-4936-4b9a-8a0a-bd612063c881
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400630201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3400630201
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2782374939
Short name T297
Test name
Test status
Simulation time 326269572464 ps
CPU time 157.52 seconds
Started May 28 02:26:45 PM PDT 24
Finished May 28 02:29:24 PM PDT 24
Peak memory 201852 kb
Host smart-543adceb-9717-470c-bf6e-ec3ee22365b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782374939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2782374939
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3187378730
Short name T238
Test name
Test status
Simulation time 323750504978 ps
CPU time 178.53 seconds
Started May 28 02:26:46 PM PDT 24
Finished May 28 02:29:46 PM PDT 24
Peak memory 201896 kb
Host smart-ede7efa0-77d6-41db-b88e-b9d5d995ee1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187378730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3187378730
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2982612464
Short name T463
Test name
Test status
Simulation time 488211294107 ps
CPU time 623.62 seconds
Started May 28 02:26:45 PM PDT 24
Finished May 28 02:37:09 PM PDT 24
Peak memory 201840 kb
Host smart-216f33a3-c3f1-4f2a-9e0e-2c112c7535be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982612464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2982612464
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2558566538
Short name T477
Test name
Test status
Simulation time 486311944012 ps
CPU time 561.56 seconds
Started May 28 02:26:46 PM PDT 24
Finished May 28 02:36:09 PM PDT 24
Peak memory 202092 kb
Host smart-1884390f-d394-4464-93bf-4edda897c7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558566538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2558566538
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1604721000
Short name T374
Test name
Test status
Simulation time 490041238762 ps
CPU time 1146.4 seconds
Started May 28 02:26:47 PM PDT 24
Finished May 28 02:45:55 PM PDT 24
Peak memory 202140 kb
Host smart-d49cec3d-51dd-4ba3-956d-c0b89bba0993
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604721000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1604721000
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1926802840
Short name T280
Test name
Test status
Simulation time 431900423646 ps
CPU time 1061.23 seconds
Started May 28 02:26:45 PM PDT 24
Finished May 28 02:44:27 PM PDT 24
Peak memory 201848 kb
Host smart-6dc4e84c-2b58-44ff-afd1-8f701f078397
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926802840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1926802840
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.937199707
Short name T671
Test name
Test status
Simulation time 90294175941 ps
CPU time 370.13 seconds
Started May 28 02:26:46 PM PDT 24
Finished May 28 02:32:57 PM PDT 24
Peak memory 202204 kb
Host smart-3c8d298c-21ef-4296-96d1-09ba14f1d79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937199707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.937199707
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1051042968
Short name T787
Test name
Test status
Simulation time 29247538616 ps
CPU time 70.02 seconds
Started May 28 02:26:45 PM PDT 24
Finished May 28 02:27:56 PM PDT 24
Peak memory 201640 kb
Host smart-406639e0-57b3-408a-802a-fd8b974055fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051042968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1051042968
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2584584498
Short name T350
Test name
Test status
Simulation time 4649993308 ps
CPU time 2.28 seconds
Started May 28 02:26:44 PM PDT 24
Finished May 28 02:26:47 PM PDT 24
Peak memory 201472 kb
Host smart-be1c9e1a-1c3e-4f3b-9d2f-ed225dda25cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584584498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2584584498
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2387482486
Short name T654
Test name
Test status
Simulation time 5607823539 ps
CPU time 3.89 seconds
Started May 28 02:26:46 PM PDT 24
Finished May 28 02:26:51 PM PDT 24
Peak memory 201688 kb
Host smart-4b42ec1b-b669-4235-87aa-2db8ffc16287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387482486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2387482486
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2076722440
Short name T681
Test name
Test status
Simulation time 186839911852 ps
CPU time 219.01 seconds
Started May 28 02:26:49 PM PDT 24
Finished May 28 02:30:29 PM PDT 24
Peak memory 201860 kb
Host smart-cadc591f-7c34-4d2e-886a-7e4dee1273d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076722440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2076722440
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.137079307
Short name T795
Test name
Test status
Simulation time 375311796948 ps
CPU time 231.19 seconds
Started May 28 02:26:49 PM PDT 24
Finished May 28 02:30:41 PM PDT 24
Peak memory 210532 kb
Host smart-a5b0273d-020d-4754-abc4-86fdeaf17fbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137079307 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.137079307
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.411411255
Short name T548
Test name
Test status
Simulation time 338596900 ps
CPU time 1.3 seconds
Started May 28 02:27:12 PM PDT 24
Finished May 28 02:27:14 PM PDT 24
Peak memory 201552 kb
Host smart-b954c481-5635-4305-9bcb-9790596fddb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411411255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.411411255
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1209252250
Short name T234
Test name
Test status
Simulation time 177715523024 ps
CPU time 425.93 seconds
Started May 28 02:26:59 PM PDT 24
Finished May 28 02:34:06 PM PDT 24
Peak memory 201904 kb
Host smart-c2b38143-fec5-4c84-a375-2e0841b51fc0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209252250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1209252250
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1503497552
Short name T563
Test name
Test status
Simulation time 163434952535 ps
CPU time 390.7 seconds
Started May 28 02:26:59 PM PDT 24
Finished May 28 02:33:30 PM PDT 24
Peak memory 201824 kb
Host smart-60df4a63-780e-4132-942f-56a0eefa4bcf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503497552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1503497552
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3886266603
Short name T514
Test name
Test status
Simulation time 330558277215 ps
CPU time 781.68 seconds
Started May 28 02:27:02 PM PDT 24
Finished May 28 02:40:05 PM PDT 24
Peak memory 201840 kb
Host smart-160fd763-e647-4637-a853-251589cd3dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886266603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3886266603
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2853613332
Short name T401
Test name
Test status
Simulation time 486000835787 ps
CPU time 1203.43 seconds
Started May 28 02:26:59 PM PDT 24
Finished May 28 02:47:03 PM PDT 24
Peak memory 201828 kb
Host smart-43066035-a202-48ce-99ca-7b1be9d52bf5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853613332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2853613332
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2598053903
Short name T225
Test name
Test status
Simulation time 372726801551 ps
CPU time 880.61 seconds
Started May 28 02:26:59 PM PDT 24
Finished May 28 02:41:40 PM PDT 24
Peak memory 201852 kb
Host smart-bc6ec2f9-9ee2-479d-8e62-fbec0e91e1a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598053903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2598053903
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1825717181
Short name T575
Test name
Test status
Simulation time 408084764093 ps
CPU time 931.17 seconds
Started May 28 02:27:01 PM PDT 24
Finished May 28 02:42:33 PM PDT 24
Peak memory 201848 kb
Host smart-d81d3702-a93e-48d6-af19-acd0e70f853a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825717181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1825717181
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.252303539
Short name T56
Test name
Test status
Simulation time 81076030228 ps
CPU time 385.14 seconds
Started May 28 02:27:09 PM PDT 24
Finished May 28 02:33:35 PM PDT 24
Peak memory 202112 kb
Host smart-e9cefb9e-7a05-4d35-a47c-dc8c7f5eac04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252303539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.252303539
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3216468743
Short name T397
Test name
Test status
Simulation time 33716000535 ps
CPU time 70.77 seconds
Started May 28 02:27:12 PM PDT 24
Finished May 28 02:28:24 PM PDT 24
Peak memory 201692 kb
Host smart-69836ad0-254a-4787-8c64-9b4001d21527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216468743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3216468743
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3115471569
Short name T433
Test name
Test status
Simulation time 4367932233 ps
CPU time 3.33 seconds
Started May 28 02:27:11 PM PDT 24
Finished May 28 02:27:15 PM PDT 24
Peak memory 201696 kb
Host smart-755cf815-5591-4b9e-89e6-9b390043e298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115471569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3115471569
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3539553906
Short name T346
Test name
Test status
Simulation time 6159975036 ps
CPU time 4.42 seconds
Started May 28 02:27:00 PM PDT 24
Finished May 28 02:27:05 PM PDT 24
Peak memory 201676 kb
Host smart-559881e0-ab44-4965-aee5-9399c536fb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539553906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3539553906
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.235809838
Short name T106
Test name
Test status
Simulation time 334190831229 ps
CPU time 400.92 seconds
Started May 28 02:27:10 PM PDT 24
Finished May 28 02:33:52 PM PDT 24
Peak memory 201884 kb
Host smart-31c2b8eb-6e57-4dbd-8732-0b9e283d97ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235809838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
235809838
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2010391863
Short name T459
Test name
Test status
Simulation time 18664082130 ps
CPU time 42.78 seconds
Started May 28 02:27:09 PM PDT 24
Finished May 28 02:27:53 PM PDT 24
Peak memory 210440 kb
Host smart-51ec3d35-4d74-4a0c-b2c1-af44966c980f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010391863 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2010391863
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2482864802
Short name T349
Test name
Test status
Simulation time 512880577 ps
CPU time 1.78 seconds
Started May 28 02:27:21 PM PDT 24
Finished May 28 02:27:24 PM PDT 24
Peak memory 201556 kb
Host smart-46eeb627-9076-4cdf-9198-2ee694d073b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482864802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2482864802
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3865600202
Short name T220
Test name
Test status
Simulation time 508200423004 ps
CPU time 58.61 seconds
Started May 28 02:27:11 PM PDT 24
Finished May 28 02:28:11 PM PDT 24
Peak memory 201652 kb
Host smart-0faf064e-a17c-41c1-b328-1c2ef6e9de8e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865600202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3865600202
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2428050367
Short name T7
Test name
Test status
Simulation time 163127917712 ps
CPU time 105.69 seconds
Started May 28 02:27:10 PM PDT 24
Finished May 28 02:28:57 PM PDT 24
Peak memory 201852 kb
Host smart-b01ae116-71f1-49e2-a909-3f8dcb1149f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428050367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2428050367
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1585824402
Short name T342
Test name
Test status
Simulation time 478017630800 ps
CPU time 210.36 seconds
Started May 28 02:27:09 PM PDT 24
Finished May 28 02:30:41 PM PDT 24
Peak memory 202056 kb
Host smart-34f7becb-2ab2-4af8-a30f-b1dd7193063b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585824402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1585824402
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.2141601078
Short name T180
Test name
Test status
Simulation time 329849700903 ps
CPU time 149.62 seconds
Started May 28 02:27:09 PM PDT 24
Finished May 28 02:29:40 PM PDT 24
Peak memory 201916 kb
Host smart-3a06a748-455a-4595-952c-29e1a7251631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141601078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2141601078
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2163503872
Short name T454
Test name
Test status
Simulation time 330011452548 ps
CPU time 207.79 seconds
Started May 28 02:27:12 PM PDT 24
Finished May 28 02:30:41 PM PDT 24
Peak memory 201828 kb
Host smart-0162338c-4bf1-4f0e-96bd-7cab32af8395
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163503872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2163503872
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2916057867
Short name T660
Test name
Test status
Simulation time 404334067243 ps
CPU time 246.96 seconds
Started May 28 02:27:10 PM PDT 24
Finished May 28 02:31:19 PM PDT 24
Peak memory 201904 kb
Host smart-b7855f56-dc4c-4409-a54e-32824fe5842c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916057867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2916057867
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2055044506
Short name T581
Test name
Test status
Simulation time 112205760826 ps
CPU time 354.61 seconds
Started May 28 02:27:09 PM PDT 24
Finished May 28 02:33:05 PM PDT 24
Peak memory 202232 kb
Host smart-56b3bf55-ece6-4a00-b4b6-d915f107a95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055044506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2055044506
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2579656601
Short name T336
Test name
Test status
Simulation time 40849904104 ps
CPU time 94.7 seconds
Started May 28 02:27:09 PM PDT 24
Finished May 28 02:28:45 PM PDT 24
Peak memory 201672 kb
Host smart-984747c2-b323-4574-b6a7-a0eb18ae1068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579656601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2579656601
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1199719276
Short name T572
Test name
Test status
Simulation time 5083026933 ps
CPU time 3.93 seconds
Started May 28 02:27:09 PM PDT 24
Finished May 28 02:27:14 PM PDT 24
Peak memory 201676 kb
Host smart-c7af54f4-30bf-4d20-800c-90d992ecb215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199719276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1199719276
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2119098924
Short name T85
Test name
Test status
Simulation time 6004698800 ps
CPU time 15.08 seconds
Started May 28 02:27:10 PM PDT 24
Finished May 28 02:27:27 PM PDT 24
Peak memory 201688 kb
Host smart-a147a540-2f5d-468a-9f7e-49f5ca87a9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119098924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2119098924
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1487534783
Short name T538
Test name
Test status
Simulation time 136631434776 ps
CPU time 424.55 seconds
Started May 28 02:27:17 PM PDT 24
Finished May 28 02:34:22 PM PDT 24
Peak memory 211792 kb
Host smart-b917a63b-a330-4457-bd11-cc83cbe0ffe0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487534783 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1487534783
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2016575729
Short name T726
Test name
Test status
Simulation time 327270574 ps
CPU time 0.82 seconds
Started May 28 02:27:32 PM PDT 24
Finished May 28 02:27:35 PM PDT 24
Peak memory 201520 kb
Host smart-e1a3ed6a-e88e-4268-8931-5991407a9e6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016575729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2016575729
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2398802675
Short name T742
Test name
Test status
Simulation time 183266769540 ps
CPU time 438.27 seconds
Started May 28 02:27:33 PM PDT 24
Finished May 28 02:34:53 PM PDT 24
Peak memory 201852 kb
Host smart-2095515c-1159-4b16-9f12-25930be7b146
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398802675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2398802675
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3005043681
Short name T730
Test name
Test status
Simulation time 183224425836 ps
CPU time 228.83 seconds
Started May 28 02:27:33 PM PDT 24
Finished May 28 02:31:23 PM PDT 24
Peak memory 201652 kb
Host smart-a004eb4f-9db9-414e-acfe-783aba49a21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005043681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3005043681
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2952363092
Short name T87
Test name
Test status
Simulation time 321787365810 ps
CPU time 199.71 seconds
Started May 28 02:27:22 PM PDT 24
Finished May 28 02:30:43 PM PDT 24
Peak memory 201936 kb
Host smart-1b7ccb21-a777-4211-a608-854df3e1674f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952363092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2952363092
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1870669992
Short name T419
Test name
Test status
Simulation time 491905831481 ps
CPU time 1231.55 seconds
Started May 28 02:27:22 PM PDT 24
Finished May 28 02:47:55 PM PDT 24
Peak memory 201828 kb
Host smart-0fb5b403-6b4c-4dc5-af29-70c5ab6f875f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870669992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1870669992
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1516653402
Short name T4
Test name
Test status
Simulation time 336651872286 ps
CPU time 788.94 seconds
Started May 28 02:27:21 PM PDT 24
Finished May 28 02:40:32 PM PDT 24
Peak memory 201916 kb
Host smart-0dc1f2bb-a10d-48a8-8c7f-6d913191fd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516653402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1516653402
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.447430399
Short name T426
Test name
Test status
Simulation time 160623300911 ps
CPU time 178.76 seconds
Started May 28 02:27:20 PM PDT 24
Finished May 28 02:30:20 PM PDT 24
Peak memory 201872 kb
Host smart-fccc5d24-4fb1-4465-b6b5-5fb79d1d42b3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=447430399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.447430399
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2346014526
Short name T232
Test name
Test status
Simulation time 354673109187 ps
CPU time 758.66 seconds
Started May 28 02:27:23 PM PDT 24
Finished May 28 02:40:02 PM PDT 24
Peak memory 201936 kb
Host smart-e60dcb91-bdd8-4f95-a941-584949df3491
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346014526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2346014526
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2448562978
Short name T448
Test name
Test status
Simulation time 197533726880 ps
CPU time 122.58 seconds
Started May 28 02:27:32 PM PDT 24
Finished May 28 02:29:36 PM PDT 24
Peak memory 201896 kb
Host smart-52692237-bad4-4013-9aa8-46ceea2b4aef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448562978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2448562978
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.4187357583
Short name T325
Test name
Test status
Simulation time 66187564207 ps
CPU time 369.13 seconds
Started May 28 02:27:32 PM PDT 24
Finished May 28 02:33:42 PM PDT 24
Peak memory 202204 kb
Host smart-d21453b5-a0d5-4bd9-a99e-ef493b088723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187357583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.4187357583
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2278499995
Short name T693
Test name
Test status
Simulation time 25106465820 ps
CPU time 31.66 seconds
Started May 28 02:27:36 PM PDT 24
Finished May 28 02:28:08 PM PDT 24
Peak memory 201696 kb
Host smart-51797b58-61f8-423f-b711-29c236578e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278499995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2278499995
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2882277026
Short name T574
Test name
Test status
Simulation time 3493500635 ps
CPU time 2.76 seconds
Started May 28 02:27:32 PM PDT 24
Finished May 28 02:27:36 PM PDT 24
Peak memory 201600 kb
Host smart-a4a21916-0436-48ce-9bb9-b343de564f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882277026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2882277026
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.176552514
Short name T111
Test name
Test status
Simulation time 5847588299 ps
CPU time 3.79 seconds
Started May 28 02:27:21 PM PDT 24
Finished May 28 02:27:26 PM PDT 24
Peak memory 201684 kb
Host smart-8573a0f2-3227-467d-ad18-4f45a5e22f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176552514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.176552514
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2261251427
Short name T729
Test name
Test status
Simulation time 578412606474 ps
CPU time 543.43 seconds
Started May 28 02:27:32 PM PDT 24
Finished May 28 02:36:37 PM PDT 24
Peak memory 201860 kb
Host smart-821392c7-06f0-4afb-8c37-80d23f66c2b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261251427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2261251427
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.520287230
Short name T647
Test name
Test status
Simulation time 49268959406 ps
CPU time 138.8 seconds
Started May 28 02:27:35 PM PDT 24
Finished May 28 02:29:54 PM PDT 24
Peak memory 210528 kb
Host smart-875277d4-7a49-49db-91dd-46adb930d21f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520287230 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.520287230
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1614548268
Short name T184
Test name
Test status
Simulation time 398201146 ps
CPU time 1.13 seconds
Started May 28 02:20:26 PM PDT 24
Finished May 28 02:20:28 PM PDT 24
Peak memory 201536 kb
Host smart-1b5200d2-3228-45f7-99b8-61d423f7c7fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614548268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1614548268
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3385274741
Short name T720
Test name
Test status
Simulation time 490233094468 ps
CPU time 175.91 seconds
Started May 28 02:20:34 PM PDT 24
Finished May 28 02:23:31 PM PDT 24
Peak memory 201792 kb
Host smart-4abeb3cb-df15-4aad-a907-b39f7cb81bf1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385274741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3385274741
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.843480374
Short name T754
Test name
Test status
Simulation time 322313439813 ps
CPU time 398.62 seconds
Started May 28 02:20:24 PM PDT 24
Finished May 28 02:27:04 PM PDT 24
Peak memory 201880 kb
Host smart-430aa833-7047-4555-bcd0-23333a69fc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843480374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.843480374
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1036789188
Short name T757
Test name
Test status
Simulation time 491797368794 ps
CPU time 620.31 seconds
Started May 28 02:20:24 PM PDT 24
Finished May 28 02:30:46 PM PDT 24
Peak memory 201844 kb
Host smart-76d4acfd-4717-4c42-881f-00011f0a1b02
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036789188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1036789188
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1913797011
Short name T153
Test name
Test status
Simulation time 492399909649 ps
CPU time 110.09 seconds
Started May 28 02:20:24 PM PDT 24
Finished May 28 02:22:15 PM PDT 24
Peak memory 201920 kb
Host smart-2ccd29c1-34ac-4075-b1dc-6a222830599c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913797011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1913797011
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1375416714
Short name T561
Test name
Test status
Simulation time 486265881830 ps
CPU time 1129.85 seconds
Started May 28 02:20:31 PM PDT 24
Finished May 28 02:39:22 PM PDT 24
Peak memory 201816 kb
Host smart-24e7d388-0699-469f-9258-3ba70a175519
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375416714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1375416714
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2341455019
Short name T302
Test name
Test status
Simulation time 459323991896 ps
CPU time 304.7 seconds
Started May 28 02:20:21 PM PDT 24
Finished May 28 02:25:26 PM PDT 24
Peak memory 201924 kb
Host smart-b2dea407-d048-4aaa-8892-d0a610144dbf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341455019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2341455019
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1180342921
Short name T663
Test name
Test status
Simulation time 401212246906 ps
CPU time 190.19 seconds
Started May 28 02:20:33 PM PDT 24
Finished May 28 02:23:44 PM PDT 24
Peak memory 201848 kb
Host smart-b3a7ea39-9c0c-4d04-8e09-e8e866edfca2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180342921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.1180342921
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2829065479
Short name T691
Test name
Test status
Simulation time 77355041527 ps
CPU time 298.79 seconds
Started May 28 02:20:32 PM PDT 24
Finished May 28 02:25:31 PM PDT 24
Peak memory 202156 kb
Host smart-e277e9ad-d91f-4817-a5d5-c5decea072e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829065479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2829065479
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1064684785
Short name T601
Test name
Test status
Simulation time 24968289759 ps
CPU time 6.38 seconds
Started May 28 02:20:34 PM PDT 24
Finished May 28 02:20:42 PM PDT 24
Peak memory 201632 kb
Host smart-3e7795c9-8919-4ab6-828a-f147d92dad3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064684785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1064684785
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.2523437269
Short name T332
Test name
Test status
Simulation time 4085525093 ps
CPU time 5.46 seconds
Started May 28 02:20:32 PM PDT 24
Finished May 28 02:20:38 PM PDT 24
Peak memory 201416 kb
Host smart-e6ea9a2c-c376-4e09-ac4f-bcdf5e150f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523437269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2523437269
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.425782933
Short name T70
Test name
Test status
Simulation time 8111045825 ps
CPU time 9.98 seconds
Started May 28 02:20:30 PM PDT 24
Finished May 28 02:20:41 PM PDT 24
Peak memory 218580 kb
Host smart-9b46ed1f-e93e-4cde-aea4-a8343bf03c26
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425782933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.425782933
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1969247851
Short name T662
Test name
Test status
Simulation time 6020538517 ps
CPU time 8.07 seconds
Started May 28 02:20:26 PM PDT 24
Finished May 28 02:20:34 PM PDT 24
Peak memory 201660 kb
Host smart-a3c234d1-be01-443c-9044-38393d191d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969247851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1969247851
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2418098443
Short name T551
Test name
Test status
Simulation time 331972933269 ps
CPU time 189.87 seconds
Started May 28 02:20:35 PM PDT 24
Finished May 28 02:23:46 PM PDT 24
Peak memory 201840 kb
Host smart-986837ee-67f1-4432-a15c-1ede1e06167e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418098443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2418098443
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1851600382
Short name T240
Test name
Test status
Simulation time 51049193869 ps
CPU time 55.24 seconds
Started May 28 02:20:30 PM PDT 24
Finished May 28 02:21:27 PM PDT 24
Peak memory 210528 kb
Host smart-e699c698-0ae9-4622-ac61-6ef4ebdb247c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851600382 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1851600382
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3832526573
Short name T384
Test name
Test status
Simulation time 517410620 ps
CPU time 1.77 seconds
Started May 28 02:27:43 PM PDT 24
Finished May 28 02:27:47 PM PDT 24
Peak memory 201512 kb
Host smart-e275f661-9a14-4ff2-b57d-a9ff3f33a9f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832526573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3832526573
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.193804915
Short name T528
Test name
Test status
Simulation time 164164842114 ps
CPU time 218.17 seconds
Started May 28 02:27:31 PM PDT 24
Finished May 28 02:31:11 PM PDT 24
Peak memory 201844 kb
Host smart-ab352b1c-ec28-4b7f-bd9b-eaeb82437c13
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193804915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.193804915
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3428009347
Short name T312
Test name
Test status
Simulation time 498821373570 ps
CPU time 101.51 seconds
Started May 28 02:27:31 PM PDT 24
Finished May 28 02:29:14 PM PDT 24
Peak memory 201920 kb
Host smart-3261e387-decf-4ac3-bf19-c5ff2ca96340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428009347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3428009347
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3880870205
Short name T107
Test name
Test status
Simulation time 489188161792 ps
CPU time 318.45 seconds
Started May 28 02:27:32 PM PDT 24
Finished May 28 02:32:52 PM PDT 24
Peak memory 201852 kb
Host smart-48a4fa35-e201-4952-bd8e-ae26965492e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880870205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3880870205
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1924659310
Short name T486
Test name
Test status
Simulation time 164681304075 ps
CPU time 183.04 seconds
Started May 28 02:27:31 PM PDT 24
Finished May 28 02:30:36 PM PDT 24
Peak memory 201844 kb
Host smart-34acf2dd-dc3e-4b23-903a-3136fe98ecc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924659310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1924659310
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1327774265
Short name T779
Test name
Test status
Simulation time 333096774475 ps
CPU time 201.34 seconds
Started May 28 02:27:35 PM PDT 24
Finished May 28 02:30:57 PM PDT 24
Peak memory 201868 kb
Host smart-256c5796-6f55-4716-a55d-47aa117a9a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327774265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1327774265
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.1052668551
Short name T357
Test name
Test status
Simulation time 326273579620 ps
CPU time 687.18 seconds
Started May 28 02:27:31 PM PDT 24
Finished May 28 02:38:59 PM PDT 24
Peak memory 201824 kb
Host smart-b71e305b-08bd-4234-a417-27288c0db341
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052668551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.1052668551
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.81888102
Short name T723
Test name
Test status
Simulation time 379941516104 ps
CPU time 936.21 seconds
Started May 28 02:27:31 PM PDT 24
Finished May 28 02:43:08 PM PDT 24
Peak memory 201868 kb
Host smart-be61a510-2927-4d88-8c74-d1c77b29a2e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81888102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_w
akeup.81888102
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.649344641
Short name T685
Test name
Test status
Simulation time 397624906939 ps
CPU time 511.22 seconds
Started May 28 02:27:32 PM PDT 24
Finished May 28 02:36:05 PM PDT 24
Peak memory 201812 kb
Host smart-dd80bf2c-3382-4021-9223-2ffa06585e38
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649344641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.649344641
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.567706162
Short name T331
Test name
Test status
Simulation time 129785677668 ps
CPU time 673.64 seconds
Started May 28 02:27:43 PM PDT 24
Finished May 28 02:38:58 PM PDT 24
Peak memory 202156 kb
Host smart-cf6da06e-54bc-487f-93f3-8ca0650b88bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567706162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.567706162
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3252916754
Short name T755
Test name
Test status
Simulation time 30633597212 ps
CPU time 46.35 seconds
Started May 28 02:27:43 PM PDT 24
Finished May 28 02:28:31 PM PDT 24
Peak memory 201688 kb
Host smart-13beb7af-bd6b-49ae-90cd-f23cd2afd25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252916754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3252916754
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.713022193
Short name T603
Test name
Test status
Simulation time 5079293290 ps
CPU time 12 seconds
Started May 28 02:27:43 PM PDT 24
Finished May 28 02:27:57 PM PDT 24
Peak memory 201652 kb
Host smart-90d161f5-9abf-4443-a95c-ce7d16286d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713022193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.713022193
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1342560551
Short name T354
Test name
Test status
Simulation time 5643036168 ps
CPU time 7.86 seconds
Started May 28 02:27:32 PM PDT 24
Finished May 28 02:27:41 PM PDT 24
Peak memory 201632 kb
Host smart-8af999a8-6288-499a-8592-f8a815698f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342560551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1342560551
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3354170606
Short name T197
Test name
Test status
Simulation time 114573091987 ps
CPU time 608.07 seconds
Started May 28 02:27:44 PM PDT 24
Finished May 28 02:37:53 PM PDT 24
Peak memory 202168 kb
Host smart-f1c087fc-43cb-4793-b499-544fc6825972
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354170606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3354170606
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.557968770
Short name T158
Test name
Test status
Simulation time 73935393084 ps
CPU time 59.24 seconds
Started May 28 02:27:44 PM PDT 24
Finished May 28 02:28:45 PM PDT 24
Peak memory 210452 kb
Host smart-b266c117-d08c-43f3-a88d-9527dd794080
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557968770 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.557968770
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3980917500
Short name T651
Test name
Test status
Simulation time 468421375 ps
CPU time 1.69 seconds
Started May 28 02:27:52 PM PDT 24
Finished May 28 02:27:54 PM PDT 24
Peak memory 201528 kb
Host smart-3592a993-8388-4a22-a9aa-d8e88a40c81c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980917500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3980917500
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.4233744628
Short name T713
Test name
Test status
Simulation time 373348297465 ps
CPU time 839.85 seconds
Started May 28 02:27:43 PM PDT 24
Finished May 28 02:41:45 PM PDT 24
Peak memory 201776 kb
Host smart-fd2371b4-384e-4ec3-abc3-9e1b1ab350b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233744628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.4233744628
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3702461343
Short name T229
Test name
Test status
Simulation time 520377339080 ps
CPU time 546.56 seconds
Started May 28 02:27:43 PM PDT 24
Finished May 28 02:36:51 PM PDT 24
Peak memory 201852 kb
Host smart-896ff8a9-c620-4c88-ae7e-dfc653c97be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702461343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3702461343
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2329430104
Short name T640
Test name
Test status
Simulation time 158049573091 ps
CPU time 365.33 seconds
Started May 28 02:27:44 PM PDT 24
Finished May 28 02:33:50 PM PDT 24
Peak memory 201920 kb
Host smart-726f286f-d097-485f-8fd3-daf1e5080fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329430104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2329430104
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3265664086
Short name T493
Test name
Test status
Simulation time 165144773712 ps
CPU time 57.13 seconds
Started May 28 02:27:42 PM PDT 24
Finished May 28 02:28:40 PM PDT 24
Peak memory 201856 kb
Host smart-5aeb9f69-bba0-40df-9038-877cdb0934a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265664086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3265664086
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.4003870298
Short name T440
Test name
Test status
Simulation time 325802181942 ps
CPU time 727.84 seconds
Started May 28 02:27:43 PM PDT 24
Finished May 28 02:39:53 PM PDT 24
Peak memory 201916 kb
Host smart-2f997d3e-2359-456a-850f-d1b0bd2311b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003870298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.4003870298
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3339699384
Short name T532
Test name
Test status
Simulation time 167586830260 ps
CPU time 186.03 seconds
Started May 28 02:27:43 PM PDT 24
Finished May 28 02:30:51 PM PDT 24
Peak memory 201908 kb
Host smart-3fe114d2-0de2-4b9f-8060-963ca6184cd2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339699384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3339699384
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.858630477
Short name T165
Test name
Test status
Simulation time 571919991087 ps
CPU time 310.48 seconds
Started May 28 02:27:46 PM PDT 24
Finished May 28 02:32:57 PM PDT 24
Peak memory 201924 kb
Host smart-290b24bd-7d9f-4c67-abb1-623c6d01f792
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858630477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.858630477
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3408902925
Short name T675
Test name
Test status
Simulation time 384348693401 ps
CPU time 218.94 seconds
Started May 28 02:27:45 PM PDT 24
Finished May 28 02:31:25 PM PDT 24
Peak memory 201836 kb
Host smart-76c0f588-b076-4162-8106-15b4ded17f99
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408902925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3408902925
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.59492429
Short name T555
Test name
Test status
Simulation time 127357127665 ps
CPU time 681.1 seconds
Started May 28 02:27:54 PM PDT 24
Finished May 28 02:39:16 PM PDT 24
Peak memory 202224 kb
Host smart-68c3f736-ff70-46f6-96ea-c2805278beb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59492429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.59492429
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.865011273
Short name T185
Test name
Test status
Simulation time 26846482857 ps
CPU time 16.88 seconds
Started May 28 02:27:53 PM PDT 24
Finished May 28 02:28:11 PM PDT 24
Peak memory 201628 kb
Host smart-cc783016-4609-4e09-82b2-fed673ba8e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865011273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.865011273
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1056706245
Short name T547
Test name
Test status
Simulation time 3324115326 ps
CPU time 1.39 seconds
Started May 28 02:27:43 PM PDT 24
Finished May 28 02:27:46 PM PDT 24
Peak memory 201608 kb
Host smart-124afb17-1cbe-458c-9bba-a587e1be821c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056706245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1056706245
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1383078858
Short name T443
Test name
Test status
Simulation time 5772012593 ps
CPU time 15.77 seconds
Started May 28 02:27:42 PM PDT 24
Finished May 28 02:27:58 PM PDT 24
Peak memory 201680 kb
Host smart-10995802-776c-457c-aa60-c712e175dbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383078858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1383078858
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.165823216
Short name T673
Test name
Test status
Simulation time 445878842 ps
CPU time 1.69 seconds
Started May 28 02:28:07 PM PDT 24
Finished May 28 02:28:10 PM PDT 24
Peak memory 201560 kb
Host smart-a457fa0c-b9dc-459c-887e-fb7dbd60b732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165823216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.165823216
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1432735377
Short name T308
Test name
Test status
Simulation time 170360887190 ps
CPU time 406.24 seconds
Started May 28 02:27:53 PM PDT 24
Finished May 28 02:34:41 PM PDT 24
Peak memory 201832 kb
Host smart-6cf2617d-f2be-436e-bb01-9609afbecdb4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432735377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1432735377
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2166077411
Short name T275
Test name
Test status
Simulation time 347411166427 ps
CPU time 736.66 seconds
Started May 28 02:27:55 PM PDT 24
Finished May 28 02:40:13 PM PDT 24
Peak memory 201840 kb
Host smart-45f088e0-644b-4c48-8d2a-750bc3dab86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166077411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2166077411
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3193574979
Short name T386
Test name
Test status
Simulation time 158997872167 ps
CPU time 103.08 seconds
Started May 28 02:27:53 PM PDT 24
Finished May 28 02:29:37 PM PDT 24
Peak memory 201852 kb
Host smart-c7f9398c-6a7c-475f-95d8-671d06b99e20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193574979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3193574979
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3116898944
Short name T99
Test name
Test status
Simulation time 319592075417 ps
CPU time 677.66 seconds
Started May 28 02:27:52 PM PDT 24
Finished May 28 02:39:11 PM PDT 24
Peak memory 201812 kb
Host smart-16a906a8-44f0-450c-b229-16beb18a28b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116898944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3116898944
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.439166713
Short name T427
Test name
Test status
Simulation time 162018608578 ps
CPU time 190.47 seconds
Started May 28 02:27:53 PM PDT 24
Finished May 28 02:31:04 PM PDT 24
Peak memory 201816 kb
Host smart-483bf972-da1f-438c-907e-ada60017ada9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=439166713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.439166713
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3977010029
Short name T620
Test name
Test status
Simulation time 175711770398 ps
CPU time 105.48 seconds
Started May 28 02:27:54 PM PDT 24
Finished May 28 02:29:41 PM PDT 24
Peak memory 201868 kb
Host smart-e74ad76f-0d0d-4019-9663-a70ce5d231ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977010029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3977010029
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1601851722
Short name T674
Test name
Test status
Simulation time 201778805390 ps
CPU time 109.1 seconds
Started May 28 02:27:54 PM PDT 24
Finished May 28 02:29:44 PM PDT 24
Peak memory 201848 kb
Host smart-c7751f79-d8e3-4917-8d6d-40edea7339a1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601851722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1601851722
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1223883803
Short name T482
Test name
Test status
Simulation time 81578852614 ps
CPU time 351.33 seconds
Started May 28 02:28:08 PM PDT 24
Finished May 28 02:34:00 PM PDT 24
Peak memory 202156 kb
Host smart-838c8e03-d80b-4a94-937f-3a89cd5a6af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223883803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1223883803
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.522431186
Short name T552
Test name
Test status
Simulation time 45032105971 ps
CPU time 26.52 seconds
Started May 28 02:28:07 PM PDT 24
Finished May 28 02:28:34 PM PDT 24
Peak memory 201660 kb
Host smart-61ce4184-37de-406b-b82a-700c56ad5686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522431186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.522431186
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.848770283
Short name T512
Test name
Test status
Simulation time 3989035556 ps
CPU time 1.67 seconds
Started May 28 02:28:07 PM PDT 24
Finished May 28 02:28:10 PM PDT 24
Peak memory 201228 kb
Host smart-65c779c3-0d60-4528-ab1c-69e635b2a4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848770283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.848770283
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1538037220
Short name T395
Test name
Test status
Simulation time 5849101885 ps
CPU time 7.88 seconds
Started May 28 02:27:56 PM PDT 24
Finished May 28 02:28:04 PM PDT 24
Peak memory 201680 kb
Host smart-6a27c4b4-f04a-4bd3-8583-a5e281716fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538037220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1538037220
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2481148800
Short name T219
Test name
Test status
Simulation time 240735216211 ps
CPU time 133.84 seconds
Started May 28 02:28:09 PM PDT 24
Finished May 28 02:30:24 PM PDT 24
Peak memory 210160 kb
Host smart-d9ffc867-ffaa-41ab-834a-52981a33acd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481148800 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2481148800
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2503702147
Short name T31
Test name
Test status
Simulation time 402723696 ps
CPU time 1.49 seconds
Started May 28 02:28:18 PM PDT 24
Finished May 28 02:28:21 PM PDT 24
Peak memory 201156 kb
Host smart-4c963754-ebcf-4f58-a0ed-32f9c7e2e5ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503702147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2503702147
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3311692572
Short name T627
Test name
Test status
Simulation time 377257596761 ps
CPU time 373.24 seconds
Started May 28 02:28:09 PM PDT 24
Finished May 28 02:34:24 PM PDT 24
Peak memory 201924 kb
Host smart-2d954d6a-1cdf-41b8-85d6-346ca9d565e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311692572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3311692572
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3584607337
Short name T516
Test name
Test status
Simulation time 489878323272 ps
CPU time 299.4 seconds
Started May 28 02:28:08 PM PDT 24
Finished May 28 02:33:09 PM PDT 24
Peak memory 201852 kb
Host smart-5ca20db5-f6ec-48d5-96f4-2829b4b4871e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584607337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3584607337
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1790633258
Short name T428
Test name
Test status
Simulation time 328396301869 ps
CPU time 759.49 seconds
Started May 28 02:28:08 PM PDT 24
Finished May 28 02:40:49 PM PDT 24
Peak memory 201852 kb
Host smart-ea76150d-ee16-437b-80f6-9a9184606593
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790633258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1790633258
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2863368248
Short name T497
Test name
Test status
Simulation time 490823269308 ps
CPU time 646.41 seconds
Started May 28 02:28:08 PM PDT 24
Finished May 28 02:38:55 PM PDT 24
Peak memory 201828 kb
Host smart-316b3d0b-b77f-4bff-80e9-70a289046bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863368248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2863368248
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.828477445
Short name T398
Test name
Test status
Simulation time 485037913104 ps
CPU time 365.07 seconds
Started May 28 02:28:07 PM PDT 24
Finished May 28 02:34:14 PM PDT 24
Peak memory 201540 kb
Host smart-7727a0e2-b7ee-43ec-a4fc-76aa767ca3e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=828477445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.828477445
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.4288309450
Short name T526
Test name
Test status
Simulation time 528310183245 ps
CPU time 529.56 seconds
Started May 28 02:28:07 PM PDT 24
Finished May 28 02:36:58 PM PDT 24
Peak memory 201932 kb
Host smart-bbd12f54-0eda-4b92-8843-19962859d03f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288309450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.4288309450
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2400293906
Short name T452
Test name
Test status
Simulation time 595795222717 ps
CPU time 1234.14 seconds
Started May 28 02:28:09 PM PDT 24
Finished May 28 02:48:45 PM PDT 24
Peak memory 201852 kb
Host smart-a61f1f80-fc42-4f99-ae99-aa76e246da0a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400293906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2400293906
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.115915607
Short name T632
Test name
Test status
Simulation time 120868261093 ps
CPU time 497.28 seconds
Started May 28 02:28:17 PM PDT 24
Finished May 28 02:36:35 PM PDT 24
Peak memory 202104 kb
Host smart-d8fa1274-4cd8-4865-8b65-4d208459fbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115915607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.115915607
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.677843403
Short name T502
Test name
Test status
Simulation time 30400960656 ps
CPU time 66.32 seconds
Started May 28 02:28:19 PM PDT 24
Finished May 28 02:29:26 PM PDT 24
Peak memory 201652 kb
Host smart-65b5b235-6588-40ad-be98-2bca330fe28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677843403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.677843403
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.4176653187
Short name T25
Test name
Test status
Simulation time 4411864539 ps
CPU time 11.05 seconds
Started May 28 02:28:18 PM PDT 24
Finished May 28 02:28:31 PM PDT 24
Peak memory 201668 kb
Host smart-598c023a-025d-4a60-949a-67bb259a9b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176653187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.4176653187
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.956031843
Short name T408
Test name
Test status
Simulation time 5734274517 ps
CPU time 7.54 seconds
Started May 28 02:28:07 PM PDT 24
Finished May 28 02:28:15 PM PDT 24
Peak memory 201684 kb
Host smart-145ce381-d440-4552-b450-2dcb66dc7c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956031843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.956031843
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2423094613
Short name T210
Test name
Test status
Simulation time 165924788544 ps
CPU time 46.59 seconds
Started May 28 02:28:19 PM PDT 24
Finished May 28 02:29:07 PM PDT 24
Peak memory 201836 kb
Host smart-4b7974dd-053e-433e-93b5-a2e5dc26dccf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423094613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2423094613
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.580490915
Short name T490
Test name
Test status
Simulation time 523137887 ps
CPU time 1.8 seconds
Started May 28 02:28:28 PM PDT 24
Finished May 28 02:28:31 PM PDT 24
Peak memory 201536 kb
Host smart-76e28160-7f5d-4985-a603-de5ac8bcede7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580490915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.580490915
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2716791340
Short name T46
Test name
Test status
Simulation time 187334065983 ps
CPU time 109.83 seconds
Started May 28 02:28:17 PM PDT 24
Finished May 28 02:30:08 PM PDT 24
Peak memory 201908 kb
Host smart-6fd9057b-53ec-4f16-b485-a051faa7d9a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716791340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2716791340
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1253081462
Short name T91
Test name
Test status
Simulation time 331060931464 ps
CPU time 214.8 seconds
Started May 28 02:28:16 PM PDT 24
Finished May 28 02:31:52 PM PDT 24
Peak memory 202104 kb
Host smart-ebec9a43-6bda-448d-bbd5-972e0cc8ddfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253081462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1253081462
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2307441749
Short name T586
Test name
Test status
Simulation time 164668899143 ps
CPU time 97.06 seconds
Started May 28 02:28:15 PM PDT 24
Finished May 28 02:29:53 PM PDT 24
Peak memory 201900 kb
Host smart-215a865c-5ba2-467a-83f8-21b54bd24df1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307441749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2307441749
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1194306995
Short name T518
Test name
Test status
Simulation time 491857437666 ps
CPU time 1148.51 seconds
Started May 28 02:28:19 PM PDT 24
Finished May 28 02:47:28 PM PDT 24
Peak memory 201820 kb
Host smart-8e0460f3-926b-4071-972b-bb9f213aa836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194306995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1194306995
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.1444673512
Short name T635
Test name
Test status
Simulation time 317409980164 ps
CPU time 703.73 seconds
Started May 28 02:28:16 PM PDT 24
Finished May 28 02:40:01 PM PDT 24
Peak memory 201824 kb
Host smart-79b67142-950f-4571-ad75-6a85c2530d58
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444673512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.1444673512
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.751667378
Short name T136
Test name
Test status
Simulation time 387265212161 ps
CPU time 226.11 seconds
Started May 28 02:28:17 PM PDT 24
Finished May 28 02:32:04 PM PDT 24
Peak memory 201940 kb
Host smart-3d31075b-cb8b-4493-9750-284af466614c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751667378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_
wakeup.751667378
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3493490799
Short name T353
Test name
Test status
Simulation time 590291507644 ps
CPU time 1340.07 seconds
Started May 28 02:28:18 PM PDT 24
Finished May 28 02:50:39 PM PDT 24
Peak memory 201900 kb
Host smart-2408b642-8578-4d52-8499-76b58040b19f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493490799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3493490799
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1018699059
Short name T504
Test name
Test status
Simulation time 110869031329 ps
CPU time 343.13 seconds
Started May 28 02:28:27 PM PDT 24
Finished May 28 02:34:11 PM PDT 24
Peak memory 202104 kb
Host smart-4f13f505-4f69-44ca-8915-9a729064f421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018699059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1018699059
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.2418318863
Short name T441
Test name
Test status
Simulation time 34775199074 ps
CPU time 74.4 seconds
Started May 28 02:28:27 PM PDT 24
Finished May 28 02:29:42 PM PDT 24
Peak memory 201664 kb
Host smart-516e10f6-b399-4c9c-b11e-b3c8fe2c7743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418318863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2418318863
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1997977222
Short name T485
Test name
Test status
Simulation time 3667175406 ps
CPU time 2.66 seconds
Started May 28 02:28:27 PM PDT 24
Finished May 28 02:28:31 PM PDT 24
Peak memory 201620 kb
Host smart-e4b5ee7c-f0e6-4032-a0b9-54c4e93b15e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997977222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1997977222
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1663406368
Short name T593
Test name
Test status
Simulation time 5757155210 ps
CPU time 4.69 seconds
Started May 28 02:28:18 PM PDT 24
Finished May 28 02:28:24 PM PDT 24
Peak memory 201316 kb
Host smart-3009d392-f646-4a20-abe2-4c9661362ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663406368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1663406368
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1035242823
Short name T738
Test name
Test status
Simulation time 15765192212 ps
CPU time 20.47 seconds
Started May 28 02:28:26 PM PDT 24
Finished May 28 02:28:48 PM PDT 24
Peak memory 201824 kb
Host smart-49a9e8d8-115f-4866-9512-50357ee44bcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035242823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1035242823
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1422284567
Short name T20
Test name
Test status
Simulation time 236891130813 ps
CPU time 398.92 seconds
Started May 28 02:28:27 PM PDT 24
Finished May 28 02:35:07 PM PDT 24
Peak memory 210540 kb
Host smart-f0373893-5531-4580-b9ce-4e97477646c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422284567 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1422284567
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.4282523619
Short name T656
Test name
Test status
Simulation time 531776683 ps
CPU time 1.73 seconds
Started May 28 02:28:37 PM PDT 24
Finished May 28 02:28:39 PM PDT 24
Peak memory 201532 kb
Host smart-854491b1-cee7-4f61-bb0b-dd2181549f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282523619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.4282523619
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.872530058
Short name T216
Test name
Test status
Simulation time 515491800535 ps
CPU time 224.61 seconds
Started May 28 02:28:38 PM PDT 24
Finished May 28 02:32:25 PM PDT 24
Peak memory 201856 kb
Host smart-2e61e54c-6a7c-40f5-8137-f5f7bddddf6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872530058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.872530058
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.3351351862
Short name T567
Test name
Test status
Simulation time 167049791919 ps
CPU time 97.25 seconds
Started May 28 02:28:38 PM PDT 24
Finished May 28 02:30:17 PM PDT 24
Peak memory 201828 kb
Host smart-91dbf52c-a7cb-47b2-8b34-e5ce9f537c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351351862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3351351862
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3955010882
Short name T109
Test name
Test status
Simulation time 165213271576 ps
CPU time 405.99 seconds
Started May 28 02:28:37 PM PDT 24
Finished May 28 02:35:24 PM PDT 24
Peak memory 201844 kb
Host smart-251b0294-f1bd-469c-bf8b-37d242349e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955010882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3955010882
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.736456163
Short name T462
Test name
Test status
Simulation time 162718172060 ps
CPU time 213.79 seconds
Started May 28 02:28:37 PM PDT 24
Finished May 28 02:32:12 PM PDT 24
Peak memory 201816 kb
Host smart-8f563b2b-e11d-414f-9209-ff710bba3e28
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=736456163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrup
t_fixed.736456163
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1934455140
Short name T221
Test name
Test status
Simulation time 326021798337 ps
CPU time 363.55 seconds
Started May 28 02:28:27 PM PDT 24
Finished May 28 02:34:31 PM PDT 24
Peak memory 201796 kb
Host smart-0a3759c1-2158-48d2-a02a-850f1510ee98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934455140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1934455140
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1306916270
Short name T712
Test name
Test status
Simulation time 165513089752 ps
CPU time 284.39 seconds
Started May 28 02:28:27 PM PDT 24
Finished May 28 02:33:12 PM PDT 24
Peak memory 201828 kb
Host smart-06bc74ac-48ef-4865-a7a9-ba21064c15d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306916270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1306916270
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.859891968
Short name T143
Test name
Test status
Simulation time 453112838827 ps
CPU time 454.9 seconds
Started May 28 02:28:38 PM PDT 24
Finished May 28 02:36:15 PM PDT 24
Peak memory 201868 kb
Host smart-206a82cb-7796-4b13-9cd2-b4ce008fa2c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859891968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.859891968
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.363209174
Short name T696
Test name
Test status
Simulation time 602434080554 ps
CPU time 669.01 seconds
Started May 28 02:28:36 PM PDT 24
Finished May 28 02:39:46 PM PDT 24
Peak memory 201656 kb
Host smart-2447d1c5-1840-4d4f-8e67-3b237b6f8739
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363209174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.363209174
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2990188852
Short name T741
Test name
Test status
Simulation time 94620221760 ps
CPU time 356.78 seconds
Started May 28 02:28:37 PM PDT 24
Finished May 28 02:34:35 PM PDT 24
Peak memory 202208 kb
Host smart-f7e8f934-0035-4fe9-82c9-247f7b45e225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990188852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2990188852
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.869164166
Short name T347
Test name
Test status
Simulation time 42787374936 ps
CPU time 7.43 seconds
Started May 28 02:28:37 PM PDT 24
Finished May 28 02:28:45 PM PDT 24
Peak memory 201668 kb
Host smart-833fed5d-760c-43f0-82f8-d38840db9252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869164166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.869164166
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.483718131
Short name T700
Test name
Test status
Simulation time 3370937217 ps
CPU time 1.94 seconds
Started May 28 02:28:38 PM PDT 24
Finished May 28 02:28:42 PM PDT 24
Peak memory 201564 kb
Host smart-ba8c4e99-700d-48a8-a931-ecb33bc037a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483718131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.483718131
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3482107566
Short name T783
Test name
Test status
Simulation time 5708027502 ps
CPU time 7.83 seconds
Started May 28 02:28:25 PM PDT 24
Finished May 28 02:28:34 PM PDT 24
Peak memory 201684 kb
Host smart-1872da3f-bd93-4450-8eef-5174de533bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482107566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3482107566
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3490668596
Short name T33
Test name
Test status
Simulation time 350602008350 ps
CPU time 836.44 seconds
Started May 28 02:28:39 PM PDT 24
Finished May 28 02:42:37 PM PDT 24
Peak memory 210360 kb
Host smart-4578668a-cf2e-4c1f-964b-80be0cbe815a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490668596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3490668596
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.526628427
Short name T44
Test name
Test status
Simulation time 324191623 ps
CPU time 0.8 seconds
Started May 28 02:28:50 PM PDT 24
Finished May 28 02:28:52 PM PDT 24
Peak memory 201528 kb
Host smart-ed44fb90-a3d6-4adf-9b73-b2ec0ae79d46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526628427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.526628427
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2263482980
Short name T612
Test name
Test status
Simulation time 488517166071 ps
CPU time 124.69 seconds
Started May 28 02:28:48 PM PDT 24
Finished May 28 02:30:54 PM PDT 24
Peak memory 201916 kb
Host smart-1c75589b-c784-4e23-b329-52d2e5495a31
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263482980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2263482980
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.197892930
Short name T288
Test name
Test status
Simulation time 505451238088 ps
CPU time 294.37 seconds
Started May 28 02:28:49 PM PDT 24
Finished May 28 02:33:45 PM PDT 24
Peak memory 201836 kb
Host smart-49d79fe7-7776-4570-9b8c-19691f22c0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197892930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.197892930
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1304232811
Short name T181
Test name
Test status
Simulation time 484908698304 ps
CPU time 170.19 seconds
Started May 28 02:28:55 PM PDT 24
Finished May 28 02:31:46 PM PDT 24
Peak memory 201720 kb
Host smart-108f5b0e-5fc9-46fd-a915-9dcbea1e4fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304232811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1304232811
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.4161171238
Short name T494
Test name
Test status
Simulation time 330506927046 ps
CPU time 190.9 seconds
Started May 28 02:28:49 PM PDT 24
Finished May 28 02:32:01 PM PDT 24
Peak memory 201844 kb
Host smart-47da9f4b-0c9d-448d-94f3-66d90d206658
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161171238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.4161171238
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.1125150793
Short name T307
Test name
Test status
Simulation time 329866656120 ps
CPU time 213.24 seconds
Started May 28 02:28:42 PM PDT 24
Finished May 28 02:32:16 PM PDT 24
Peak memory 201880 kb
Host smart-a4061090-97ed-43c3-9369-f60ae130f6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125150793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1125150793
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.300217279
Short name T648
Test name
Test status
Simulation time 495396428575 ps
CPU time 1258.72 seconds
Started May 28 02:28:50 PM PDT 24
Finished May 28 02:49:50 PM PDT 24
Peak memory 201828 kb
Host smart-afb3e6a2-8e1d-4313-9a65-921a5ccd9ae4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=300217279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixe
d.300217279
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.595709354
Short name T702
Test name
Test status
Simulation time 192046411016 ps
CPU time 122.4 seconds
Started May 28 02:28:55 PM PDT 24
Finished May 28 02:30:58 PM PDT 24
Peak memory 201836 kb
Host smart-59062458-15dc-4ef8-a430-f5c209f61468
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595709354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.595709354
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1431521451
Short name T377
Test name
Test status
Simulation time 201498176415 ps
CPU time 233.97 seconds
Started May 28 02:28:50 PM PDT 24
Finished May 28 02:32:45 PM PDT 24
Peak memory 201840 kb
Host smart-91ae3edd-96c5-49e4-b80f-d351c9932833
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431521451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1431521451
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.108942646
Short name T469
Test name
Test status
Simulation time 124872116026 ps
CPU time 688.56 seconds
Started May 28 02:28:55 PM PDT 24
Finished May 28 02:40:24 PM PDT 24
Peak memory 202136 kb
Host smart-6c34993d-39f3-4bba-b18b-dd5c675adee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108942646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.108942646
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.121197997
Short name T591
Test name
Test status
Simulation time 44543853126 ps
CPU time 26.95 seconds
Started May 28 02:28:49 PM PDT 24
Finished May 28 02:29:17 PM PDT 24
Peak memory 201656 kb
Host smart-b2c0801d-e4ff-4cea-91ff-e056ffb4473b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121197997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.121197997
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2664101172
Short name T736
Test name
Test status
Simulation time 5432421161 ps
CPU time 13.02 seconds
Started May 28 02:28:55 PM PDT 24
Finished May 28 02:29:08 PM PDT 24
Peak memory 201632 kb
Host smart-76ee260d-e315-41d3-a9d3-16ff95810c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664101172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2664101172
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2393291248
Short name T465
Test name
Test status
Simulation time 5704980986 ps
CPU time 8.77 seconds
Started May 28 02:28:38 PM PDT 24
Finished May 28 02:28:49 PM PDT 24
Peak memory 201672 kb
Host smart-12b9f113-1428-4211-8420-dbc4272d85f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393291248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2393291248
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3504564970
Short name T279
Test name
Test status
Simulation time 497833286971 ps
CPU time 92.04 seconds
Started May 28 02:28:55 PM PDT 24
Finished May 28 02:30:28 PM PDT 24
Peak memory 201728 kb
Host smart-992efc1e-f272-43a4-9083-8d7c3ad90d82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504564970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3504564970
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2410051993
Short name T718
Test name
Test status
Simulation time 173384524228 ps
CPU time 59.15 seconds
Started May 28 02:28:48 PM PDT 24
Finished May 28 02:29:48 PM PDT 24
Peak memory 201964 kb
Host smart-1d5f5360-413a-4b2b-abcc-eba7c16b9232
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410051993 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2410051993
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3532406508
Short name T383
Test name
Test status
Simulation time 374869765 ps
CPU time 0.8 seconds
Started May 28 02:29:01 PM PDT 24
Finished May 28 02:29:03 PM PDT 24
Peak memory 201528 kb
Host smart-6dd7412a-9fa7-40bf-ad51-56496adedd4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532406508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3532406508
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3151756452
Short name T168
Test name
Test status
Simulation time 336187593693 ps
CPU time 202.96 seconds
Started May 28 02:29:00 PM PDT 24
Finished May 28 02:32:23 PM PDT 24
Peak memory 201852 kb
Host smart-7f1b43f7-e193-49c2-a04b-946cd3d869b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151756452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3151756452
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.249589573
Short name T253
Test name
Test status
Simulation time 163983801178 ps
CPU time 91.95 seconds
Started May 28 02:29:01 PM PDT 24
Finished May 28 02:30:34 PM PDT 24
Peak memory 201856 kb
Host smart-0a214700-9d6d-43e8-9403-813376557026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249589573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.249589573
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.4225637132
Short name T446
Test name
Test status
Simulation time 161835853034 ps
CPU time 396.41 seconds
Started May 28 02:29:00 PM PDT 24
Finished May 28 02:35:37 PM PDT 24
Peak memory 201848 kb
Host smart-83157f4f-5b14-414d-b314-092c6b922a40
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225637132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.4225637132
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1756825684
Short name T669
Test name
Test status
Simulation time 489643797709 ps
CPU time 1062.98 seconds
Started May 28 02:28:49 PM PDT 24
Finished May 28 02:46:34 PM PDT 24
Peak memory 201720 kb
Host smart-e662c570-3225-4f25-afff-a43fbc734409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756825684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1756825684
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.471645125
Short name T624
Test name
Test status
Simulation time 489965724667 ps
CPU time 297.73 seconds
Started May 28 02:29:01 PM PDT 24
Finished May 28 02:34:00 PM PDT 24
Peak memory 201864 kb
Host smart-bc7ea8bd-6caa-4ede-91a9-5902f4e05e55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=471645125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.471645125
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1345503387
Short name T680
Test name
Test status
Simulation time 590660579995 ps
CPU time 1357.43 seconds
Started May 28 02:29:01 PM PDT 24
Finished May 28 02:51:40 PM PDT 24
Peak memory 201848 kb
Host smart-992a8aa0-3b7f-4b58-b505-d8eab7486fab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345503387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1345503387
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.512856956
Short name T406
Test name
Test status
Simulation time 85769881408 ps
CPU time 293.53 seconds
Started May 28 02:29:00 PM PDT 24
Finished May 28 02:33:54 PM PDT 24
Peak memory 202132 kb
Host smart-020463b7-6197-4475-a798-cddca7da82c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512856956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.512856956
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.1323377785
Short name T619
Test name
Test status
Simulation time 38865740999 ps
CPU time 11.55 seconds
Started May 28 02:29:01 PM PDT 24
Finished May 28 02:29:14 PM PDT 24
Peak memory 201624 kb
Host smart-36f5faeb-619c-4f3f-a5e7-5977a27bcab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323377785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1323377785
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2740587529
Short name T650
Test name
Test status
Simulation time 4012330385 ps
CPU time 4.49 seconds
Started May 28 02:29:01 PM PDT 24
Finished May 28 02:29:07 PM PDT 24
Peak memory 201616 kb
Host smart-d95a74ae-fc68-41e4-823b-9eea56b0b7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740587529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2740587529
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3799066965
Short name T420
Test name
Test status
Simulation time 6006429941 ps
CPU time 6.96 seconds
Started May 28 02:28:49 PM PDT 24
Finished May 28 02:28:56 PM PDT 24
Peak memory 201528 kb
Host smart-5a183b69-8476-4b1b-913e-549707837cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799066965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3799066965
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2172548519
Short name T747
Test name
Test status
Simulation time 416648639864 ps
CPU time 774.96 seconds
Started May 28 02:29:00 PM PDT 24
Finished May 28 02:41:57 PM PDT 24
Peak memory 212436 kb
Host smart-de515a53-7a04-4c1c-9888-e85b39210092
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172548519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2172548519
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.600237711
Short name T18
Test name
Test status
Simulation time 231264391885 ps
CPU time 47.44 seconds
Started May 28 02:29:01 PM PDT 24
Finished May 28 02:29:50 PM PDT 24
Peak memory 210164 kb
Host smart-38b15ec8-3b52-4695-b6de-79cceb35690e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600237711 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.600237711
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1950222767
Short name T471
Test name
Test status
Simulation time 460056233 ps
CPU time 0.84 seconds
Started May 28 02:29:17 PM PDT 24
Finished May 28 02:29:20 PM PDT 24
Peak memory 201532 kb
Host smart-7e04628c-34bd-4c09-ae1c-3623099704df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950222767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1950222767
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1472787062
Short name T264
Test name
Test status
Simulation time 525675594394 ps
CPU time 898.97 seconds
Started May 28 02:29:16 PM PDT 24
Finished May 28 02:44:16 PM PDT 24
Peak memory 201932 kb
Host smart-10f42e08-fa7c-4217-9b47-6926216c6128
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472787062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1472787062
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.3533170441
Short name T186
Test name
Test status
Simulation time 593441756433 ps
CPU time 191.22 seconds
Started May 28 02:29:16 PM PDT 24
Finished May 28 02:32:28 PM PDT 24
Peak memory 201900 kb
Host smart-28e558f9-b3c0-4f4a-81b1-71ff860e758b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533170441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3533170441
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3679591315
Short name T711
Test name
Test status
Simulation time 495622378160 ps
CPU time 1117.58 seconds
Started May 28 02:29:16 PM PDT 24
Finished May 28 02:47:55 PM PDT 24
Peak memory 201720 kb
Host smart-065b6032-8763-4ab3-8cbc-3054442d17e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679591315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3679591315
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1247290610
Short name T379
Test name
Test status
Simulation time 325562300864 ps
CPU time 192.58 seconds
Started May 28 02:29:17 PM PDT 24
Finished May 28 02:32:32 PM PDT 24
Peak memory 201812 kb
Host smart-959e61a6-8df9-4d71-a20b-a7c35ef8a9f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247290610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1247290610
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3897471272
Short name T394
Test name
Test status
Simulation time 164811594946 ps
CPU time 100.69 seconds
Started May 28 02:29:01 PM PDT 24
Finished May 28 02:30:43 PM PDT 24
Peak memory 201792 kb
Host smart-21120a14-6af7-4cc6-bff3-86c04833a589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897471272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3897471272
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3905271373
Short name T628
Test name
Test status
Simulation time 323492820100 ps
CPU time 203.07 seconds
Started May 28 02:29:01 PM PDT 24
Finished May 28 02:32:25 PM PDT 24
Peak memory 201836 kb
Host smart-53d20f04-3816-4f38-83d5-f04e1b4ecdf2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905271373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3905271373
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.162825494
Short name T227
Test name
Test status
Simulation time 182943231222 ps
CPU time 413.92 seconds
Started May 28 02:29:16 PM PDT 24
Finished May 28 02:36:13 PM PDT 24
Peak memory 201936 kb
Host smart-b25709ed-f6d5-4c77-b0ef-d0eabe1584ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162825494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.162825494
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2414238852
Short name T604
Test name
Test status
Simulation time 598717832516 ps
CPU time 1454.02 seconds
Started May 28 02:29:17 PM PDT 24
Finished May 28 02:53:34 PM PDT 24
Peak memory 201836 kb
Host smart-12757b6a-9c42-43f5-b499-bc4a0b1c3f86
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414238852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2414238852
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1827864213
Short name T429
Test name
Test status
Simulation time 119088910429 ps
CPU time 417.86 seconds
Started May 28 02:29:16 PM PDT 24
Finished May 28 02:36:17 PM PDT 24
Peak memory 202228 kb
Host smart-7c89395e-747c-4715-82b9-bb14cd0811a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827864213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1827864213
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1488072917
Short name T498
Test name
Test status
Simulation time 29680283899 ps
CPU time 8.67 seconds
Started May 28 02:29:15 PM PDT 24
Finished May 28 02:29:25 PM PDT 24
Peak memory 201644 kb
Host smart-e5d8f147-35bc-4f56-bd31-a537eae79521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488072917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1488072917
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2991213019
Short name T103
Test name
Test status
Simulation time 4646781282 ps
CPU time 11.9 seconds
Started May 28 02:29:17 PM PDT 24
Finished May 28 02:29:31 PM PDT 24
Peak memory 201680 kb
Host smart-821a0125-d1bf-4b4b-98c5-c3b1670c6625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991213019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2991213019
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1995874091
Short name T94
Test name
Test status
Simulation time 5893009443 ps
CPU time 7.74 seconds
Started May 28 02:29:01 PM PDT 24
Finished May 28 02:29:10 PM PDT 24
Peak memory 201660 kb
Host smart-c2d13848-1522-4185-847e-8804d88d0fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995874091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1995874091
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.136622440
Short name T138
Test name
Test status
Simulation time 517912499114 ps
CPU time 1141.7 seconds
Started May 28 02:29:16 PM PDT 24
Finished May 28 02:48:21 PM PDT 24
Peak memory 201840 kb
Host smart-7cd55691-2874-4517-9684-81d40bf73669
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136622440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
136622440
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3962541432
Short name T299
Test name
Test status
Simulation time 69223853784 ps
CPU time 198.51 seconds
Started May 28 02:29:17 PM PDT 24
Finished May 28 02:32:38 PM PDT 24
Peak memory 210468 kb
Host smart-71ce9623-fbc9-49f7-b9f6-655343f17d4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962541432 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3962541432
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3303468169
Short name T611
Test name
Test status
Simulation time 390842887 ps
CPU time 0.82 seconds
Started May 28 02:29:27 PM PDT 24
Finished May 28 02:29:29 PM PDT 24
Peak memory 201552 kb
Host smart-ca69cb55-eeb9-4ab6-b2ee-7370fc19e8e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303468169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3303468169
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2751293321
Short name T254
Test name
Test status
Simulation time 340923804083 ps
CPU time 760.85 seconds
Started May 28 02:29:27 PM PDT 24
Finished May 28 02:42:09 PM PDT 24
Peak memory 201932 kb
Host smart-802b8b22-a9d8-440c-85ed-b50faf2206b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751293321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2751293321
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2339199511
Short name T580
Test name
Test status
Simulation time 322706949463 ps
CPU time 641.34 seconds
Started May 28 02:29:27 PM PDT 24
Finished May 28 02:40:09 PM PDT 24
Peak memory 201920 kb
Host smart-d6db5d0b-cc6a-49af-bab6-2102637c8283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339199511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2339199511
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3621186763
Short name T717
Test name
Test status
Simulation time 482086765792 ps
CPU time 233.22 seconds
Started May 28 02:29:30 PM PDT 24
Finished May 28 02:33:24 PM PDT 24
Peak memory 201836 kb
Host smart-16fc2911-ddd3-4fde-abc5-8f6a09ff57cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621186763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3621186763
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.4036563862
Short name T746
Test name
Test status
Simulation time 166108727241 ps
CPU time 243.02 seconds
Started May 28 02:29:17 PM PDT 24
Finished May 28 02:33:22 PM PDT 24
Peak memory 201856 kb
Host smart-fceb038f-adf2-41cf-8773-c1b41f27f287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036563862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.4036563862
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.4288570165
Short name T781
Test name
Test status
Simulation time 170049643410 ps
CPU time 201.1 seconds
Started May 28 02:29:26 PM PDT 24
Finished May 28 02:32:47 PM PDT 24
Peak memory 201888 kb
Host smart-b45d8c20-1e09-4be8-929f-e3b814f209c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288570165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.4288570165
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.648898863
Short name T553
Test name
Test status
Simulation time 568238329719 ps
CPU time 402.12 seconds
Started May 28 02:29:26 PM PDT 24
Finished May 28 02:36:10 PM PDT 24
Peak memory 201856 kb
Host smart-6234b1ad-ee73-4bd5-9fed-a814e5be6df5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648898863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.648898863
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2465958680
Short name T733
Test name
Test status
Simulation time 600560297629 ps
CPU time 1419.49 seconds
Started May 28 02:29:26 PM PDT 24
Finished May 28 02:53:07 PM PDT 24
Peak memory 202068 kb
Host smart-4052bf2c-e364-4393-81fe-ac167d4e7849
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465958680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2465958680
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1516504066
Short name T326
Test name
Test status
Simulation time 87322618859 ps
CPU time 302.93 seconds
Started May 28 02:29:27 PM PDT 24
Finished May 28 02:34:31 PM PDT 24
Peak memory 202200 kb
Host smart-e2c07b98-1474-4b14-8d8f-305b12e202f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516504066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1516504066
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.823808446
Short name T695
Test name
Test status
Simulation time 30592120663 ps
CPU time 9.78 seconds
Started May 28 02:29:26 PM PDT 24
Finished May 28 02:29:37 PM PDT 24
Peak memory 201660 kb
Host smart-b08cbd6c-8f83-4aeb-b1fd-8d8820d7c63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823808446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.823808446
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.158916610
Short name T597
Test name
Test status
Simulation time 5265994940 ps
CPU time 4.06 seconds
Started May 28 02:29:27 PM PDT 24
Finished May 28 02:29:32 PM PDT 24
Peak memory 201636 kb
Host smart-ae6acff0-78bc-462d-9780-70de3541ab67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158916610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.158916610
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2220660650
Short name T505
Test name
Test status
Simulation time 5708325852 ps
CPU time 4.7 seconds
Started May 28 02:29:17 PM PDT 24
Finished May 28 02:29:24 PM PDT 24
Peak memory 201684 kb
Host smart-07e7c06b-50ef-480e-bac8-e06db891b985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220660650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2220660650
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3862031845
Short name T772
Test name
Test status
Simulation time 149753106804 ps
CPU time 51.86 seconds
Started May 28 02:29:26 PM PDT 24
Finished May 28 02:30:19 PM PDT 24
Peak memory 210200 kb
Host smart-62694687-fabd-473b-88ce-a3d77c2caf22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862031845 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3862031845
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.845716829
Short name T481
Test name
Test status
Simulation time 479253196 ps
CPU time 1.83 seconds
Started May 28 02:20:36 PM PDT 24
Finished May 28 02:20:40 PM PDT 24
Peak memory 201540 kb
Host smart-9c9c7f2c-242c-41f3-a0c3-6da5ed2213d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845716829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.845716829
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.83583755
Short name T657
Test name
Test status
Simulation time 349717280751 ps
CPU time 784.49 seconds
Started May 28 02:20:35 PM PDT 24
Finished May 28 02:33:42 PM PDT 24
Peak memory 201812 kb
Host smart-7fe19c63-7b47-436c-b1f8-7488a6ba70ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83583755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gating
.83583755
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.45372286
Short name T750
Test name
Test status
Simulation time 163479282303 ps
CPU time 181.41 seconds
Started May 28 02:20:37 PM PDT 24
Finished May 28 02:23:41 PM PDT 24
Peak memory 201932 kb
Host smart-977adcf0-3fda-412f-8352-46ca7f8096d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45372286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.45372286
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1667156728
Short name T211
Test name
Test status
Simulation time 323261718842 ps
CPU time 182.32 seconds
Started May 28 02:20:36 PM PDT 24
Finished May 28 02:23:41 PM PDT 24
Peak memory 201844 kb
Host smart-927ef877-ae2c-464f-8b31-114dd0c82b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667156728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1667156728
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2640810575
Short name T146
Test name
Test status
Simulation time 326779963645 ps
CPU time 208.92 seconds
Started May 28 02:20:35 PM PDT 24
Finished May 28 02:24:06 PM PDT 24
Peak memory 201828 kb
Host smart-c25f5c2a-478d-4187-97c6-227db8f042d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640810575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2640810575
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2844952505
Short name T5
Test name
Test status
Simulation time 492646155925 ps
CPU time 608.32 seconds
Started May 28 02:20:31 PM PDT 24
Finished May 28 02:30:41 PM PDT 24
Peak memory 201832 kb
Host smart-78d8bb09-ebd6-427d-9e47-932c2f3002e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844952505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2844952505
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.414513711
Short name T792
Test name
Test status
Simulation time 490872630049 ps
CPU time 1250.81 seconds
Started May 28 02:20:35 PM PDT 24
Finished May 28 02:41:27 PM PDT 24
Peak memory 201920 kb
Host smart-190346d2-1eb0-4eb9-b7f9-5ce1c6ef2a91
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=414513711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.414513711
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1687612668
Short name T97
Test name
Test status
Simulation time 348976430935 ps
CPU time 422.82 seconds
Started May 28 02:20:35 PM PDT 24
Finished May 28 02:27:40 PM PDT 24
Peak memory 201872 kb
Host smart-fb158b53-52d2-4516-8358-14032ee8790b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687612668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1687612668
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2865151852
Short name T533
Test name
Test status
Simulation time 401813683144 ps
CPU time 444.59 seconds
Started May 28 02:20:35 PM PDT 24
Finished May 28 02:28:02 PM PDT 24
Peak memory 201664 kb
Host smart-7d8a81b6-fcd7-4d87-92ee-e2b2ba59f11f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865151852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2865151852
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.568637059
Short name T415
Test name
Test status
Simulation time 108957883630 ps
CPU time 606.54 seconds
Started May 28 02:20:38 PM PDT 24
Finished May 28 02:30:47 PM PDT 24
Peak memory 202148 kb
Host smart-63173f4a-ce92-4d62-99c3-6d8cb90977dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568637059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.568637059
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.4241231244
Short name T9
Test name
Test status
Simulation time 22312590636 ps
CPU time 55.5 seconds
Started May 28 02:20:38 PM PDT 24
Finished May 28 02:21:36 PM PDT 24
Peak memory 201656 kb
Host smart-683d0f03-0a73-495e-975e-a1406ed5b8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241231244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.4241231244
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1950102476
Short name T697
Test name
Test status
Simulation time 3490396230 ps
CPU time 2.39 seconds
Started May 28 02:20:37 PM PDT 24
Finished May 28 02:20:42 PM PDT 24
Peak memory 201592 kb
Host smart-232121ff-b3bc-45f3-89c4-ada4d26faee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950102476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1950102476
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.394020531
Short name T431
Test name
Test status
Simulation time 5897957154 ps
CPU time 4.25 seconds
Started May 28 02:20:31 PM PDT 24
Finished May 28 02:20:36 PM PDT 24
Peak memory 201664 kb
Host smart-8cdeb8ba-596a-4e86-8f36-291f9ce763ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394020531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.394020531
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2158870541
Short name T562
Test name
Test status
Simulation time 369908463686 ps
CPU time 441.64 seconds
Started May 28 02:20:34 PM PDT 24
Finished May 28 02:27:57 PM PDT 24
Peak memory 201896 kb
Host smart-a28b9e5a-b725-4552-8cac-9b5b9f082832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158870541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2158870541
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2144412958
Short name T763
Test name
Test status
Simulation time 114700792079 ps
CPU time 121.91 seconds
Started May 28 02:20:36 PM PDT 24
Finished May 28 02:22:40 PM PDT 24
Peak memory 201972 kb
Host smart-ff38b2e9-1ae1-4f1a-9ff4-89fc27bd2282
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144412958 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2144412958
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.218271538
Short name T643
Test name
Test status
Simulation time 470612610 ps
CPU time 1.66 seconds
Started May 28 02:20:50 PM PDT 24
Finished May 28 02:20:52 PM PDT 24
Peak memory 201524 kb
Host smart-7a043879-d9ca-40af-9209-64f2b72ad737
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218271538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.218271538
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2397657460
Short name T784
Test name
Test status
Simulation time 161243542273 ps
CPU time 168.07 seconds
Started May 28 02:20:37 PM PDT 24
Finished May 28 02:23:28 PM PDT 24
Peak memory 201848 kb
Host smart-b240518a-ed6a-4d01-85d5-e14c4e426c77
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397657460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2397657460
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1603377300
Short name T242
Test name
Test status
Simulation time 187834480406 ps
CPU time 72.42 seconds
Started May 28 02:20:34 PM PDT 24
Finished May 28 02:21:47 PM PDT 24
Peak memory 201860 kb
Host smart-ccd9cce2-3433-4015-9fc6-223c8ce3fe8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603377300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1603377300
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.840782377
Short name T252
Test name
Test status
Simulation time 487758588383 ps
CPU time 1147.37 seconds
Started May 28 02:20:37 PM PDT 24
Finished May 28 02:39:47 PM PDT 24
Peak memory 202176 kb
Host smart-483d069c-9f84-4eb7-962f-0b53b005547c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840782377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.840782377
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1125130686
Short name T692
Test name
Test status
Simulation time 162657578687 ps
CPU time 199.77 seconds
Started May 28 02:20:38 PM PDT 24
Finished May 28 02:24:00 PM PDT 24
Peak memory 201816 kb
Host smart-f304d306-3bc3-4cbe-83e8-23a5669aa5e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125130686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1125130686
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3609998545
Short name T145
Test name
Test status
Simulation time 495779519379 ps
CPU time 303.53 seconds
Started May 28 02:20:36 PM PDT 24
Finished May 28 02:25:43 PM PDT 24
Peak memory 201808 kb
Host smart-06fffc51-21f6-45f0-9c78-f80e42e6c93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609998545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3609998545
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.727211223
Short name T458
Test name
Test status
Simulation time 159771956464 ps
CPU time 187.16 seconds
Started May 28 02:20:38 PM PDT 24
Finished May 28 02:23:48 PM PDT 24
Peak memory 201820 kb
Host smart-bfa53edf-6a33-46ce-ac75-d927cb42f798
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=727211223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed
.727211223
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1687498243
Short name T794
Test name
Test status
Simulation time 357956379955 ps
CPU time 178.95 seconds
Started May 28 02:20:37 PM PDT 24
Finished May 28 02:23:39 PM PDT 24
Peak memory 201916 kb
Host smart-d407fd43-e2c8-4940-bf38-002cabcdd195
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687498243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1687498243
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.297102793
Short name T511
Test name
Test status
Simulation time 403454974812 ps
CPU time 79.8 seconds
Started May 28 02:20:37 PM PDT 24
Finished May 28 02:21:59 PM PDT 24
Peak memory 202148 kb
Host smart-16981970-2223-4c04-84f3-285d62873a67
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297102793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.297102793
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1377816342
Short name T579
Test name
Test status
Simulation time 89953932173 ps
CPU time 484.54 seconds
Started May 28 02:20:50 PM PDT 24
Finished May 28 02:28:56 PM PDT 24
Peak memory 202160 kb
Host smart-62904a6a-375e-4380-be80-cded79fd42a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377816342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1377816342
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1186577323
Short name T558
Test name
Test status
Simulation time 23210058750 ps
CPU time 52.86 seconds
Started May 28 02:20:50 PM PDT 24
Finished May 28 02:21:44 PM PDT 24
Peak memory 201640 kb
Host smart-5a0f33a1-cd1a-4744-87e7-a641a8224d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186577323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1186577323
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.3335995806
Short name T405
Test name
Test status
Simulation time 4300092931 ps
CPU time 9.65 seconds
Started May 28 02:20:49 PM PDT 24
Finished May 28 02:20:59 PM PDT 24
Peak memory 201648 kb
Host smart-1ba1ced5-bf9e-4f34-8bc5-577635aa5935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335995806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3335995806
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.429551721
Short name T400
Test name
Test status
Simulation time 5734514644 ps
CPU time 4.17 seconds
Started May 28 02:20:38 PM PDT 24
Finished May 28 02:20:44 PM PDT 24
Peak memory 201676 kb
Host smart-ed8faf88-3c08-4b61-8687-87e0c0b890f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429551721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.429551721
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1216965492
Short name T451
Test name
Test status
Simulation time 203572477275 ps
CPU time 1143.48 seconds
Started May 28 02:20:49 PM PDT 24
Finished May 28 02:39:54 PM PDT 24
Peak memory 210392 kb
Host smart-cdd930a5-401b-4335-b6f2-df848b5cbaea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216965492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1216965492
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1703528703
Short name T335
Test name
Test status
Simulation time 296817232 ps
CPU time 0.82 seconds
Started May 28 02:21:01 PM PDT 24
Finished May 28 02:21:03 PM PDT 24
Peak memory 201184 kb
Host smart-7203625b-a0ad-4738-9d04-1857cb0474dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703528703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1703528703
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3745100941
Short name T707
Test name
Test status
Simulation time 523031466941 ps
CPU time 822.04 seconds
Started May 28 02:20:50 PM PDT 24
Finished May 28 02:34:33 PM PDT 24
Peak memory 201856 kb
Host smart-01b56f8f-deb2-400d-a66d-bf8c73cbcfd4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745100941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3745100941
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3293843462
Short name T300
Test name
Test status
Simulation time 598726201549 ps
CPU time 1395.94 seconds
Started May 28 02:20:52 PM PDT 24
Finished May 28 02:44:09 PM PDT 24
Peak memory 201832 kb
Host smart-79ba0bbd-9dfc-4c9f-86b9-b4d8ab5da5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293843462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3293843462
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2102542119
Short name T218
Test name
Test status
Simulation time 324787818372 ps
CPU time 787.13 seconds
Started May 28 02:20:50 PM PDT 24
Finished May 28 02:33:58 PM PDT 24
Peak memory 201932 kb
Host smart-8bdf8f08-8fa2-4f05-8702-c6e205e7c65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102542119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2102542119
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2925649504
Short name T410
Test name
Test status
Simulation time 160848445898 ps
CPU time 384.15 seconds
Started May 28 02:20:53 PM PDT 24
Finished May 28 02:27:18 PM PDT 24
Peak memory 201820 kb
Host smart-380db16b-7453-4e10-badd-cef2a0f872f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925649504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2925649504
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1205051838
Short name T166
Test name
Test status
Simulation time 494858754929 ps
CPU time 292.05 seconds
Started May 28 02:20:51 PM PDT 24
Finished May 28 02:25:44 PM PDT 24
Peak memory 201924 kb
Host smart-6111435a-aa65-419c-a5d8-440148a711bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205051838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1205051838
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3184470355
Short name T519
Test name
Test status
Simulation time 320806749422 ps
CPU time 163.69 seconds
Started May 28 02:20:50 PM PDT 24
Finished May 28 02:23:35 PM PDT 24
Peak memory 201840 kb
Host smart-f8f86319-a7a3-4124-866b-462e2eedbe95
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184470355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3184470355
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.4076029964
Short name T172
Test name
Test status
Simulation time 205190438094 ps
CPU time 489.44 seconds
Started May 28 02:20:53 PM PDT 24
Finished May 28 02:29:03 PM PDT 24
Peak memory 201840 kb
Host smart-edfa640f-edd5-4324-b789-04ffc6e2f5ba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076029964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.4076029964
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3075766633
Short name T617
Test name
Test status
Simulation time 115208099370 ps
CPU time 613.39 seconds
Started May 28 02:20:59 PM PDT 24
Finished May 28 02:31:13 PM PDT 24
Peak memory 202236 kb
Host smart-6aa5ebbc-f28a-42ca-96f8-dc239a452691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075766633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3075766633
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1578237152
Short name T686
Test name
Test status
Simulation time 34836973021 ps
CPU time 12.79 seconds
Started May 28 02:20:58 PM PDT 24
Finished May 28 02:21:12 PM PDT 24
Peak memory 201668 kb
Host smart-bb0e22fc-11de-4388-a0b5-c840945eece7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578237152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1578237152
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1522935553
Short name T495
Test name
Test status
Simulation time 3343632169 ps
CPU time 2.78 seconds
Started May 28 02:21:00 PM PDT 24
Finished May 28 02:21:04 PM PDT 24
Peak memory 201592 kb
Host smart-fe694274-828c-456f-9a61-4806b5a34f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522935553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1522935553
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2963777659
Short name T422
Test name
Test status
Simulation time 6054948657 ps
CPU time 7.79 seconds
Started May 28 02:20:49 PM PDT 24
Finished May 28 02:20:57 PM PDT 24
Peak memory 201656 kb
Host smart-ebaae304-9f55-460f-b536-a13029d8b4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963777659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2963777659
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3072246463
Short name T274
Test name
Test status
Simulation time 501738725804 ps
CPU time 302.96 seconds
Started May 28 02:21:01 PM PDT 24
Finished May 28 02:26:05 PM PDT 24
Peak memory 201512 kb
Host smart-d817e9ed-914e-43c3-ae63-672f3a6a2ca5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072246463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3072246463
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1481124803
Short name T77
Test name
Test status
Simulation time 332767960 ps
CPU time 0.83 seconds
Started May 28 02:21:12 PM PDT 24
Finished May 28 02:21:14 PM PDT 24
Peak memory 201496 kb
Host smart-a5a10418-2397-4779-beb2-402756b6c1a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481124803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1481124803
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1886489846
Short name T744
Test name
Test status
Simulation time 157035538601 ps
CPU time 80.57 seconds
Started May 28 02:21:13 PM PDT 24
Finished May 28 02:22:34 PM PDT 24
Peak memory 201948 kb
Host smart-3fbbcd4e-5d2e-4320-84c1-6f449e04ee82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886489846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1886489846
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.77714725
Short name T213
Test name
Test status
Simulation time 325324038914 ps
CPU time 750.71 seconds
Started May 28 02:20:59 PM PDT 24
Finished May 28 02:33:31 PM PDT 24
Peak memory 201852 kb
Host smart-41bbe3db-9ea4-4955-a9cf-2fd86de3269a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77714725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.77714725
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2354834749
Short name T372
Test name
Test status
Simulation time 165324082136 ps
CPU time 376.69 seconds
Started May 28 02:21:02 PM PDT 24
Finished May 28 02:27:19 PM PDT 24
Peak memory 201828 kb
Host smart-0a4c273a-6570-435f-b0d9-dafc40435708
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354834749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2354834749
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.232613580
Short name T48
Test name
Test status
Simulation time 324274563393 ps
CPU time 775.02 seconds
Started May 28 02:20:58 PM PDT 24
Finished May 28 02:33:54 PM PDT 24
Peak memory 201924 kb
Host smart-f72535b6-d9a7-4e14-9d7c-e6b3d82b0965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232613580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.232613580
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.870171241
Short name T613
Test name
Test status
Simulation time 502710216865 ps
CPU time 545.09 seconds
Started May 28 02:20:59 PM PDT 24
Finished May 28 02:30:06 PM PDT 24
Peak memory 201804 kb
Host smart-dc47de80-8004-4bc6-9532-91bb70c343cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=870171241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.870171241
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.942541779
Short name T298
Test name
Test status
Simulation time 582862951079 ps
CPU time 1359.86 seconds
Started May 28 02:20:59 PM PDT 24
Finished May 28 02:43:40 PM PDT 24
Peak memory 201852 kb
Host smart-5338c8e1-4e09-411b-a124-17408251b93c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942541779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.942541779
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1568369982
Short name T536
Test name
Test status
Simulation time 401585645320 ps
CPU time 249.96 seconds
Started May 28 02:20:58 PM PDT 24
Finished May 28 02:25:09 PM PDT 24
Peak memory 201700 kb
Host smart-bd9caf9f-aafa-4033-a8eb-1c0b0b3122fc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568369982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1568369982
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1306513514
Short name T3
Test name
Test status
Simulation time 107610348191 ps
CPU time 370.1 seconds
Started May 28 02:21:11 PM PDT 24
Finished May 28 02:27:22 PM PDT 24
Peak memory 202204 kb
Host smart-96a18d8d-3500-41f5-b98d-c29c0502b7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306513514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1306513514
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.839644436
Short name T105
Test name
Test status
Simulation time 34830538076 ps
CPU time 43.39 seconds
Started May 28 02:21:12 PM PDT 24
Finished May 28 02:21:56 PM PDT 24
Peak memory 201668 kb
Host smart-b7321486-b391-48db-8f62-2a1e0277604f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839644436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.839644436
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1558177197
Short name T500
Test name
Test status
Simulation time 4160525211 ps
CPU time 10.08 seconds
Started May 28 02:21:10 PM PDT 24
Finished May 28 02:21:21 PM PDT 24
Peak memory 201612 kb
Host smart-09f49a88-6fc1-4087-86ca-adcb2137db00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558177197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1558177197
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.47055729
Short name T402
Test name
Test status
Simulation time 5770736167 ps
CPU time 4.31 seconds
Started May 28 02:21:02 PM PDT 24
Finished May 28 02:21:07 PM PDT 24
Peak memory 201660 kb
Host smart-8c87fe6b-88e5-419e-8712-a1fe84d24b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47055729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.47055729
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2784918327
Short name T269
Test name
Test status
Simulation time 269268721731 ps
CPU time 327.78 seconds
Started May 28 02:21:11 PM PDT 24
Finished May 28 02:26:40 PM PDT 24
Peak memory 210532 kb
Host smart-40296393-6e99-455c-9364-4f14804ecc51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784918327 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2784918327
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3542039135
Short name T778
Test name
Test status
Simulation time 531598354 ps
CPU time 1.11 seconds
Started May 28 02:21:23 PM PDT 24
Finished May 28 02:21:25 PM PDT 24
Peak memory 201500 kb
Host smart-2410b6fc-abbe-4f74-af00-060aed913998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542039135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3542039135
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2001431130
Short name T212
Test name
Test status
Simulation time 333189940867 ps
CPU time 579.95 seconds
Started May 28 02:21:22 PM PDT 24
Finished May 28 02:31:03 PM PDT 24
Peak memory 201920 kb
Host smart-788dbe31-3c2a-44ba-9469-faee8328a71f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001431130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2001431130
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1834538484
Short name T301
Test name
Test status
Simulation time 504927959680 ps
CPU time 305.56 seconds
Started May 28 02:21:25 PM PDT 24
Finished May 28 02:26:31 PM PDT 24
Peak memory 201852 kb
Host smart-8e79c6e9-8a5a-41fd-a82a-812fe3a1185b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834538484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1834538484
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3895766366
Short name T29
Test name
Test status
Simulation time 486057745311 ps
CPU time 117.16 seconds
Started May 28 02:21:23 PM PDT 24
Finished May 28 02:23:22 PM PDT 24
Peak memory 201828 kb
Host smart-dc305679-febb-4c47-a694-cc6bdaee477b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895766366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3895766366
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.572971614
Short name T638
Test name
Test status
Simulation time 160832286186 ps
CPU time 63.81 seconds
Started May 28 02:21:24 PM PDT 24
Finished May 28 02:22:29 PM PDT 24
Peak memory 201844 kb
Host smart-aa1642c4-e6ba-40b1-9968-3b6b38234d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572971614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.572971614
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.3277600063
Short name T631
Test name
Test status
Simulation time 500642513581 ps
CPU time 302.62 seconds
Started May 28 02:21:26 PM PDT 24
Finished May 28 02:26:29 PM PDT 24
Peak memory 201968 kb
Host smart-6424f0cf-39cd-4008-9a20-db11963e8b0d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277600063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.3277600063
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.343656533
Short name T522
Test name
Test status
Simulation time 245584273561 ps
CPU time 267.88 seconds
Started May 28 02:21:27 PM PDT 24
Finished May 28 02:25:56 PM PDT 24
Peak memory 202140 kb
Host smart-8e96bd4a-af44-4d14-950f-d7738d9b92a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343656533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.343656533
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2415298469
Short name T359
Test name
Test status
Simulation time 612505438645 ps
CPU time 1348.47 seconds
Started May 28 02:21:24 PM PDT 24
Finished May 28 02:43:53 PM PDT 24
Peak memory 201852 kb
Host smart-6262a781-3ff9-4bb9-a51d-58d5c4a0ddf2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415298469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2415298469
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.528160126
Short name T461
Test name
Test status
Simulation time 98369138555 ps
CPU time 517.03 seconds
Started May 28 02:21:22 PM PDT 24
Finished May 28 02:30:00 PM PDT 24
Peak memory 202164 kb
Host smart-99085012-2451-4936-bb26-7dfacca8176d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528160126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.528160126
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3525618421
Short name T633
Test name
Test status
Simulation time 30114282652 ps
CPU time 20.01 seconds
Started May 28 02:21:26 PM PDT 24
Finished May 28 02:21:47 PM PDT 24
Peak memory 201656 kb
Host smart-764ad02b-fb10-4411-947c-96652959f21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525618421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3525618421
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.10104301
Short name T564
Test name
Test status
Simulation time 5223076278 ps
CPU time 3.54 seconds
Started May 28 02:21:24 PM PDT 24
Finished May 28 02:21:28 PM PDT 24
Peak memory 201468 kb
Host smart-aaca091a-7174-4447-8894-3a3d0902a490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10104301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.10104301
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3117721505
Short name T412
Test name
Test status
Simulation time 5983988883 ps
CPU time 8.02 seconds
Started May 28 02:21:13 PM PDT 24
Finished May 28 02:21:22 PM PDT 24
Peak memory 201688 kb
Host smart-75c26c47-941a-4947-bb19-6577d2dddd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117721505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3117721505
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2102112821
Short name T735
Test name
Test status
Simulation time 101027011431 ps
CPU time 222.75 seconds
Started May 28 02:21:23 PM PDT 24
Finished May 28 02:25:07 PM PDT 24
Peak memory 218224 kb
Host smart-ff931fbf-254c-47e6-b959-93e85b8c71a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102112821 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2102112821
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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