Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7093	1			T2	20		T3	55		T4	20
testmodes[AdcCtrlTestmodeNormal]	5542	1			T1	2		T3	47		T5	26
testmodes[AdcCtrlTestmodeLowpower]	5858	1			T3	67		T5	28		T7	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3866	1			T2	19		T3	16		T4	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1742	1			T3	17		T5	12		T8	15
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1363	1			T3	22		T5	2		T8	22
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1744	1			T3	19		T5	12		T8	20
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2053	1			T1	1		T3	13		T5	12
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1416	1			T3	15		T5	1		T7	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1369	1			T3	20		T5	1		T8	18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1415	1			T3	16		T5	2		T8	16
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2825	1			T3	30		T5	25		T8	10