Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26972

1

T1

16

T2

20

T3

169

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23063

1

T1

15

T2

20

T3

169

auto[ADC_CTRL_FILTER_COND_OUT]

3909

1

T1

1

T5

6

T6

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20579

1

T1

15

T2

20

T3

169

auto[1]

6393

1

T1

1

T5

6

T6

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22708

1

T1

2

T2

20

T3

169

auto[1]

4264

1

T1

14

T5

7

T6

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T193	1		-	-		-	-
values[0]	45	1			T155	4		T194	19		T18	22
values[1]	773	1			T5	2		T15	9		T135	13
values[2]	563	1			T8	16		T28	3		T143	28
values[3]	753	1			T7	34		T93	4		T195	27
values[4]	905	1			T6	1		T93	14		T35	12
values[5]	701	1			T1	1		T13	9		T34	11
values[6]	764	1			T5	6		T6	12		T23	3
values[7]	791	1			T6	17		T27	13		T195	22
values[8]	2831	1			T1	14		T5	4		T8	44
values[9]	1317	1			T10	29		T34	6		T15	19
minimum	17528	1			T1	1		T2	20		T3	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	961	1			T5	2		T15	9		T135	13
values[1]	537	1			T7	23		T8	16		T143	28
values[2]	937	1			T6	1		T7	11		T93	4
values[3]	761	1			T93	14		T35	12		T140	20
values[4]	683	1			T1	1		T5	6		T13	9
values[5]	685	1			T6	12		T34	10		T27	13
values[6]	3076	1			T6	17		T8	44		T9	12
values[7]	682	1			T1	14		T5	4		T35	13
values[8]	837	1			T34	6		T15	19		T138	7
values[9]	229	1			T10	29		T196	1		T197	3
minimum	17584	1			T1	1		T2	20		T3	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

4215

1

T5

5

T6

4

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	2		T135	13		T198	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T15	4		T124	1		T199	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	10		T8	8		T124	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T143	14		T42	1		T150	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T6	1		T7	5		T195	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T93	1		T14	3		T28	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T93	2		T140	13		T38	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T35	3		T142	1		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T23	1		T121	1		T135	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T1	1		T5	4		T13	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T201	6		T202	11		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	1		T34	10		T27	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1584	1			T6	5		T9	1		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T8	22		T143	14		T203	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	1		T5	4		T35	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T16	19		T137	1		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T34	6		T138	7		T122	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T15	7		T136	1		T139	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T196	1		T197	1		T204	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T10	15		T205	11		T206	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17435	1			T2	20		T3	169		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T125	17		T207	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T141	14		T208	15		T209	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T15	5		T124	12		T210	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T7	13		T8	8		T124	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T143	14		T29	1		T186	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T7	6		T195	4		T123	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T93	3		T14	1		T28	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T93	12		T140	7		T38	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T35	9		T142	11		T211	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T23	2		T121	8		T46	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	2		T28	4		T136	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T201	2		T202	11		T212	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	11		T27	5		T195	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1080	1			T6	12		T9	11		T11	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T8	22		T143	18		T203	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	13		T35	9		T213	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T16	8		T151	12		T214	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T122	4		T37	3		T150	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T15	12		T136	6		T126	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T197	2		T204	11		T215	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T10	14		T205	12		T206	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T1	1		T5	5		T6	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T193	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T155	4		T194	10		T18	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	2		T135	13		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T15	4		T124	1		T125	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T8	8		T124	2		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T28	2		T143	14		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T7	15		T195	23		T46	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T93	1		T139	14		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	1		T93	2		T140	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T35	3		T14	3		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T135	6		T46	10		T200	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T1	1		T13	9		T34	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T23	1		T35	10		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	4		T6	1		T34	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	5		T150	7		T126	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T27	8		T195	12		T123	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1538	1			T1	1		T5	4		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T8	22		T139	14		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T34	6		T138	7		T122	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T10	15		T15	7		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17413	1			T2	20		T3	169		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T194	9		T18	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T141	14		T208	4		T209	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T15	5		T124	12		T210	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T8	8		T124	2		T197	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T28	1		T143	14		T182	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	19		T195	4		T38	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T93	3		T140	1		T141	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T93	12		T140	7		T123	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T35	9		T14	1		T142	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T46	10		T127	1		T151	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T28	4		T136	14		T30	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T23	2		T35	6		T121	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	2		T6	11		T136	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	12		T150	9		T126	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T27	5		T195	10		T123	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1064	1			T1	13		T9	11		T11	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T8	22		T214	10		T216	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T122	4		T37	3		T213	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T10	14		T15	12		T136	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T5	5		T6	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	2		T135	1		T198	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T15	9		T124	13		T199	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	14		T8	9		T124	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T143	15		T42	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T6	1		T7	7		T195	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T93	4		T14	3		T28	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T93	14		T140	8		T38	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T35	10		T142	12		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T23	3		T121	9		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	1		T5	3		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T201	3		T202	12		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T6	12		T34	1		T27	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1416	1			T6	13		T9	12		T11	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T8	23		T143	19		T203	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	14		T5	2		T35	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T16	13		T137	1		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T34	1		T138	1		T122	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T15	15		T136	7		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T196	1		T197	3		T204	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T10	15		T205	13		T206	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17546	1			T1	1		T2	20		T3	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T125	1		T207	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T135	12		T125	11		T208	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T78	8		T210	7		T182	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T7	9		T8	7		T124	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T143	13		T150	14		T29	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T7	4		T195	21		T46	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	1		T28	1		T139	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T140	12		T38	3		T126	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T35	2		T211	9		T77	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T135	5		T46	9		T151	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	3		T13	8		T34	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T201	5		T202	10		T217	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T34	9		T27	3		T195	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T6	4		T12	21		T35	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T8	21		T143	13		T203	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	2		T35	3		T46	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T16	14		T151	11		T217	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T34	5		T138	6		T122	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T15	4		T139	13		T154	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T167	12		T218	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T10	14		T205	10		T219	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T155	6		T220	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T125	16		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T193	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T155	1		T194	10		T18	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T5	2		T135	1		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T15	9		T124	13		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	9		T124	3		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T28	2		T143	15		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T7	21		T195	6		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T93	4		T139	1		T140	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T6	1		T93	14		T140	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T35	10		T14	3		T142	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T135	1		T46	11		T200	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	1		T13	1		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T23	3		T35	7		T121	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T5	3		T6	12		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	13		T150	10		T126	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T27	10		T195	11		T123	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1412	1			T1	14		T5	2		T9	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T8	23		T139	1		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T34	1		T138	1		T122	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	406	1			T10	15		T15	15		T136	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T1	1		T2	20		T3	169
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T155	3		T194	9		T18	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T135	12		T208	5		T155	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T125	16		T210	7		T221	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T8	7		T124	1		T125	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T28	1		T143	13		T78	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	13		T195	21		T46	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T139	13		T150	14		T29	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T140	12		T123	11		T38	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T35	2		T14	1		T211	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T135	5		T46	9		T126	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	8		T34	10		T30	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T35	9		T201	5		T202	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	3		T34	9		T135	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T6	4		T150	6		T126	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T27	3		T195	11		T123	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1190	1			T5	2		T12	21		T35	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T8	21		T139	13		T217	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T34	5		T138	6		T122	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T10	14		T15	4		T16	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

auto[0]

4215

1

T5

5

T6

4

T7

13

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26972

1

T1

16

T2

20

T3

169

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20956

1

T1

16

T2

20

T3

169

auto[ADC_CTRL_FILTER_COND_OUT]

6016

1

T5

4

T6

29

T8

44

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21164

1

T1

2

T2

20

T3

169

auto[1]

5808

1

T1

14

T5

10

T6

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22708

1

T1

2

T2

20

T3

169

auto[1]

4264

1

T1

14

T5

7

T6

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T222	1		-	-		-	-
values[0]	90	1			T37	8		T221	11		T223	1
values[1]	772	1			T138	7		T135	13		T136	12
values[2]	923	1			T5	6		T6	12		T34	10
values[3]	816	1			T93	3		T195	12		T46	20
values[4]	661	1			T13	9		T23	3		T35	16
values[5]	596	1			T7	11		T10	29		T135	5
values[6]	551	1			T34	6		T28	3		T16	1
values[7]	644	1			T1	1		T6	17		T7	23
values[8]	698	1			T8	60		T122	9		T123	23
values[9]	3692	1			T1	14		T5	6		T6	1
minimum	17528	1			T1	1		T2	20		T3	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1092	1			T34	10		T27	13		T138	7
values[1]	3136	1			T5	6		T6	12		T9	12
values[2]	710	1			T23	3		T195	12		T46	20
values[3]	701	1			T7	11		T13	9		T35	16
values[4]	645	1			T10	29		T34	6		T135	5
values[5]	578	1			T7	23		T28	3		T16	1
values[6]	677	1			T6	17		T8	44		T34	11
values[7]	675	1			T1	1		T5	4		T8	16
values[8]	1032	1			T1	14		T5	2		T35	12
values[9]	198	1			T6	1		T136	15		T78	8
minimum	17528	1			T1	1		T2	20		T3	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

4215

1

T5

5

T6

4

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T34	10		T27	8		T138	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T135	13		T123	12		T37	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	4		T195	12		T16	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1594	1			T6	1		T9	1		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T23	1		T195	10		T125	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T46	10		T203	4		T149	29
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	5		T13	9		T35	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T140	13		T37	1		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T34	6		T46	17		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T10	15		T135	5		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	10		T28	2		T139	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T16	1		T199	1		T176	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T34	11		T93	1		T14	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T6	5		T8	22		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T1	1		T8	8		T38	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	4		T15	4		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	1		T5	2		T121	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T35	3		T28	4		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T6	1		T78	8		T217	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T136	1		T224	1		T216	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17413	1			T2	20		T3	169		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T27	5		T136	11		T124	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T123	9		T37	3		T77	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	2		T195	10		T16	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1174	1			T6	11		T9	11		T11	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T23	2		T195	2		T150	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T46	10		T203	3		T225	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	6		T35	6		T210	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T140	7		T226	2		T127	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T136	6		T143	32		T150	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T10	14		T124	12		T197	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	13		T28	1		T140	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T214	10		T31	1		T227	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T93	10		T14	1		T201	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	12		T8	22		T93	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	8		T38	3		T151	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T15	5		T123	11		T38	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	13		T121	8		T195	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T35	9		T28	4		T141	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T228	1		T229	1		T230	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T136	14		T224	14		T216	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T5	5		T6	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T222	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T221	6		T231	1		T232	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T37	5		T223	1		T233	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T138	7		T136	1		T16	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T135	13		T77	10		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T5	4		T34	10		T27	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T6	1		T35	4		T15	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T195	10		T150	13		T126	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T93	1		T46	10		T142	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	9		T23	1		T35	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T226	1		T127	1		T234	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	5		T46	17		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T10	15		T135	5		T140	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T34	6		T28	2		T139	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T16	1		T199	1		T176	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	1		T7	10		T34	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T6	5		T93	1		T15	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	8		T199	1		T151	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T8	22		T122	5		T123	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T1	1		T5	2		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1793	1			T5	4		T9	1		T11	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17413	1			T2	20		T3	169		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T221	5		T231	7		T232	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T37	3		T233	2		T235	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T136	11		T16	8		T124	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T77	12		T182	4		T194	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	2		T27	5		T195	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T6	11		T35	9		T15	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T195	2		T150	11		T236	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T93	2		T46	10		T203	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T23	2		T35	6		T210	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T226	2		T127	1		T237	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	6		T136	6		T143	32
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	14		T140	7		T124	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T28	1		T162	15		T238	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T214	10		T33	2		T223	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T7	13		T93	10		T14	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T6	12		T93	3		T15	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T8	8		T151	12		T39	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	22		T122	4		T123	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T1	13		T121	8		T195	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1271	1			T9	11		T11	16		T148	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T5	5		T6	3