Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26972

1

T1

16

T2

20

T3

169

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23215

1

T1

15

T2

20

T3

169

auto[ADC_CTRL_FILTER_COND_OUT]

3757

1

T1

1

T5

4

T7

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20982

1

T1

16

T2

20

T3

169

auto[1]

5990

1

T5

8

T6

18

T8

44

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22708

1

T1

2

T2

20

T3

169

auto[1]

4264

1

T1

14

T5

7

T6

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	183	1			T10	29		T38	13		T126	10
values[0]	7	1			T176	1		T160	1		T250	1
values[1]	623	1			T1	1		T5	6		T13	9
values[2]	810	1			T8	44		T34	6		T14	4
values[3]	794	1			T7	23		T195	22		T201	8
values[4]	744	1			T6	29		T34	10		T135	13
values[5]	3052	1			T6	1		T9	12		T11	18
values[6]	631	1			T35	12		T121	9		T46	12
values[7]	723	1			T5	6		T138	7		T135	6
values[8]	731	1			T8	16		T23	3		T46	5
values[9]	1146	1			T1	14		T7	11		T93	3
minimum	17528	1			T1	1		T2	20		T3	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	586	1			T5	6		T13	9		T93	11
values[1]	795	1			T1	1		T8	44		T34	6
values[2]	842	1			T6	12		T7	23		T195	22
values[3]	3059	1			T6	18		T9	12		T11	18
values[4]	701	1			T93	4		T35	13		T139	14
values[5]	696	1			T5	2		T35	12		T121	9
values[6]	589	1			T5	4		T138	7		T135	6
values[7]	862	1			T8	16		T23	3		T46	5
values[8]	1003	1			T1	14		T7	11		T10	29
values[9]	118	1			T126	10		T196	1		T227	2
minimum	17721	1			T1	1		T2	20		T3	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

4215

1

T5

5

T6

4

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	4		T93	1		T139	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	9		T124	1		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T8	22		T34	6		T14	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	1		T136	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T6	1		T7	10		T201	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T195	12		T135	13		T16	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1590	1			T6	6		T9	1		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T34	10		T202	11		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T35	4		T139	14		T38	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T93	1		T143	14		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	2		T35	3		T46	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T121	1		T46	10		T16	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T138	7		T135	6		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	4		T137	1		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T8	8		T23	1		T123	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T46	5		T124	11		T200	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T1	1		T15	7		T135	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T7	5		T10	15		T93	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T126	10		T196	1		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T267	1		T164	1		T292	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17453	1			T2	20		T3	169		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T34	11		T27	8		T126	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T5	2		T93	10		T226	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T124	12		T226	2		T127	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T8	22		T14	1		T195	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T136	6		T141	3		T124	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	11		T7	13		T201	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T195	10		T16	8		T143	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1112	1			T6	12		T9	11		T11	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T202	11		T213	10		T88	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T35	9		T38	3		T77	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T93	3		T143	14		T144	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T35	9		T28	1		T224	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T121	8		T46	10		T123	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T140	1		T182	4		T212	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T123	17		T142	11		T226	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T8	8		T23	2		T123	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T124	11		T203	17		T24	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	13		T15	12		T37	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T7	6		T10	14		T93	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T227	1		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T267	8		T164	1		T82	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T1	1		T5	5		T6	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T27	5		T126	8		T265	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T126	10		T196	1		T227	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T10	15		T38	1		T196	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T176	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T160	1		T250	1		T265	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	4		T93	1		T35	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	1		T13	9		T34	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T8	22		T34	6		T14	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T136	1		T141	1		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	10		T201	6		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T195	12		T16	19		T124	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	6		T136	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T34	10		T135	13		T202	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1529	1			T6	1		T9	1		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T93	1		T199	1		T78	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T35	3		T46	12		T28	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T121	1		T16	1		T123	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	2		T138	7		T135	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T5	4		T46	10		T123	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T8	8		T23	1		T123	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T46	5		T137	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T1	1		T15	7		T135	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T7	5		T93	1		T15	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17413	1			T2	20		T3	169		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T227	1		T167	2		T293	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T10	14		T38	12		T267	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T265	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T5	2		T93	10		T35	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T27	5		T226	2		T126	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	22		T14	1		T195	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T136	6		T141	3		T124	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	13		T201	2		T136	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T195	10		T16	8		T124	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	23		T136	14		T156	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T202	11		T143	18		T213	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1086	1			T9	11		T11	16		T148	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T93	3		T144	13		T31	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T35	9		T28	1		T77	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T121	8		T123	9		T143	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T140	1		T224	14		T210	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T46	10		T123	17		T142	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T8	8		T23	2		T123	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T124	11		T203	17		T24	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T1	13		T15	12		T37	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T7	6		T93	2		T15	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T5	5		T6	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	3		T93	11		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	1		T124	13		T226	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T8	23		T34	1		T14	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	1		T136	7		T141	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	12		T7	14		T201	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T195	11		T135	1		T16	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1457	1			T6	14		T9	12		T11	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T34	1		T202	12		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T35	10		T139	1		T38	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T93	4		T143	15		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	2		T35	10		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T121	9		T46	11		T16	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T138	1		T135	1		T140	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	2		T137	1		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T8	9		T23	3		T123	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T46	1		T124	12		T200	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T1	14		T15	15		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T7	7		T10	15		T93	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T126	1		T196	1		T227	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T267	9		T164	2		T292	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17558	1			T1	1		T2	20		T3	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T34	1		T27	10		T126	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	3		T139	13		T150	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T13	8		T127	9		T39	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	21		T34	5		T14	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T124	1		T217	13		T197	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	9		T201	5		T142	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T195	11		T135	12		T16	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1245	1			T6	4		T12	21		T36	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T34	9		T202	10		T234	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T35	3		T139	13		T38	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T143	13		T78	8		T31	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T35	2		T46	11		T28	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T46	9		T123	11		T154	31
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T138	6		T135	5		T78	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	2		T123	13		T149	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T8	7		T123	11		T211	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T46	4		T124	10		T203	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T15	4		T135	4		T37	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T7	4		T10	14		T195	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T126	9		T263	11		T269	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T173	11		T270	10		T274	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T35	9		T289	11		T286	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T34	10		T27	3		T126	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T126	1		T196	1		T227	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T10	15		T38	13		T196	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T176	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T160	1		T250	1		T265	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	3		T93	11		T35	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T1	1		T13	1		T34	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T8	23		T34	1		T14	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T136	7		T141	4		T124	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	14		T201	3		T136	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T195	11		T16	13		T124	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	25		T136	15		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T34	1		T135	1		T202	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1425	1			T6	1		T9	12		T11	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T93	4		T199	1		T78	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T35	10		T46	1		T28	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T121	9		T16	1		T123	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	2		T138	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T5	2		T46	11		T123	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T8	9		T23	3		T123	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T46	1		T137	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T1	14		T15	15		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T7	7		T93	3		T15	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T1	1		T2	20		T3	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T126	9		T263	11		T293	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T10	14		T274	11		T228	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	3		T35	9		T139	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T13	8		T34	10		T27	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T8	21		T34	5		T14	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T127	9		T39	6		T25	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	9		T201	5		T142	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T195	11		T16	14		T124	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	4		T253	18		T232	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T34	9		T135	12		T202	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1190	1			T12	21		T35	3		T36	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T78	8		T31	2		T252	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	2		T46	11		T28	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T123	11		T143	13		T154	31
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T138	6		T135	5		T78	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	2		T46	9		T123	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T8	7		T123	11		T203	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T46	4		T124	10		T203	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T15	4		T135	4		T37	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T7	4		T195	9		T122	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

auto[0]

4215

1

T5

5

T6

4

T7

13