Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26972

1

T1

16

T2

20

T3

169

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23114

1

T1

2

T2

20

T3

169

auto[ADC_CTRL_FILTER_COND_OUT]

3858

1

T1

14

T5

2

T6

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20945

1

T1

1

T2

20

T3

169

auto[1]

6027

1

T1

15

T6

29

T8

44

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22708

1

T1

2

T2

20

T3

169

auto[1]

4264

1

T1

14

T5

7

T6

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	246	1			T123	23		T200	1		T38	13
values[0]	30	1			T138	7		T126	15		T20	8
values[1]	893	1			T10	29		T195	22		T135	13
values[2]	719	1			T1	1		T5	6		T6	1
values[3]	809	1			T6	12		T8	44		T15	19
values[4]	601	1			T13	9		T34	6		T46	12
values[5]	730	1			T5	2		T7	23		T8	16
values[6]	659	1			T1	14		T93	11		T27	13
values[7]	652	1			T5	4		T6	17		T135	11
values[8]	699	1			T7	11		T93	3		T35	41
values[9]	3406	1			T9	12		T11	18		T12	23
minimum	17528	1			T1	1		T2	20		T3	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	931	1			T6	1		T10	29		T135	13
values[1]	648	1			T1	1		T5	6		T6	12
values[2]	853	1			T15	19		T28	3		T137	1
values[3]	577	1			T5	2		T7	23		T8	16
values[4]	767	1			T34	11		T14	4		T46	5
values[5]	624	1			T1	14		T93	11		T27	13
values[6]	2949	1			T5	4		T6	17		T9	12
values[7]	725	1			T7	11		T35	41		T136	7
values[8]	1054	1			T23	3		T15	9		T195	27
values[9]	126	1			T123	23		T38	13		T233	14
minimum	17718	1			T1	1		T2	20		T3	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

4215

1

T5

5

T6

4

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T135	13		T202	11		T150	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T6	1		T10	15		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	1		T5	4		T8	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T6	1		T93	1		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T15	7		T137	1		T123	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T28	2		T200	1		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	9		T34	6		T46	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	2		T7	10		T8	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	3		T139	14		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T34	11		T46	5		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T125	17		T160	1		T172	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	1		T93	1		T27	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1531	1			T5	4		T6	5		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T135	5		T46	10		T199	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T136	1		T143	28		T124	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T7	5		T35	17		T188	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T15	4		T195	10		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T23	1		T195	13		T201	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T297	1		T220	15		T298	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T123	12		T38	1		T233	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17476	1			T2	20		T3	169		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T195	12		T141	1		T126	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T202	11		T150	11		T24	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T10	14		T140	7		T124	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	2		T8	22		T136	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	11		T93	3		T121	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T15	12		T123	17		T77	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T28	1		T30	1		T209	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T197	2		T210	12		T164	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	13		T8	8		T142	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T14	1		T141	14		T226	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T140	1		T124	2		T37	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T162	15		T89	8		T276	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	13		T93	10		T27	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1044	1			T6	12		T9	11		T11	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T46	10		T26	11		T250	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T136	6		T143	32		T124	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	6		T35	24		T224	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T15	5		T195	2		T136	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T23	2		T195	2		T201	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T297	6		T220	16		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T123	11		T38	12		T233	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	1		T5	5		T6	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T195	10		T141	3		T126	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T42	1		T149	12		T176	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T123	12		T200	1		T38	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T138	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T126	7		T20	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T135	13		T202	11		T150	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T10	15		T195	12		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	1		T5	4		T34	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T6	1		T93	1		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T8	22		T15	7		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T6	1		T28	2		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	9		T34	6		T46	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T142	1		T126	12		T299	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T14	3		T139	14		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T5	2		T7	10		T8	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T125	17		T160	1		T276	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	1		T93	1		T27	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T5	4		T6	5		T135	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T135	5		T46	10		T28	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T93	1		T136	1		T143	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	5		T35	17		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1678	1			T9	1		T11	2		T12	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T23	1		T195	13		T201	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17413	1			T2	20		T3	169		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T297	18		T220	16		T300	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T123	11		T38	12		T260	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T126	8		T20	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T202	11		T150	11		T24	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T10	14		T195	10		T140	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	2		T16	8		T29	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T93	3		T121	8		T123	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T8	22		T15	12		T136	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T6	11		T28	1		T30	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T197	2		T210	12		T164	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T142	11		T126	11		T162	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T14	1		T141	14		T226	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	13		T8	8		T140	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T276	2		T301	4		T265	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	13		T93	10		T27	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T6	12		T186	9		T162	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T46	10		T28	4		T214	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T93	2		T136	6		T143	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	6		T35	24		T224	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1161	1			T9	11		T11	16		T148	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T23	2		T195	2		T201	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T5	5		T6	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T135	1		T202	12		T150	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T6	1		T10	15		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	1		T5	3		T8	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	12		T93	4		T121	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T15	15		T137	1		T123	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T28	2		T200	1		T30	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T13	1		T34	1		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	2		T7	14		T8	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T14	3		T139	1		T141	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T34	1		T46	1		T140	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T125	1		T160	1		T172	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T1	14		T93	11		T27	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T5	2		T6	13		T9	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T135	1		T46	11		T199	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T136	7		T143	34		T124	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T7	7		T35	27		T188	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T15	9		T195	3		T136	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T23	3		T195	3		T201	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T297	7		T220	17		T298	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T123	12		T38	13		T233	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17589	1			T1	1		T2	20		T3	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T195	11		T141	4		T126	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T135	12		T202	10		T150	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T10	14		T140	12		T154	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T5	3		T8	21		T34	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T123	11		T39	6		T278	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T15	4		T123	13		T125	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T28	1		T30	2		T245	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	8		T34	5		T46	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T7	9		T8	7		T149	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	1		T139	13		T154	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T34	10		T46	4		T124	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T125	16		T265	9		T289	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T27	3		T203	14		T149	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1197	1			T5	2		T6	4		T12	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T135	4		T46	9		T26	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T143	26		T124	10		T38	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T7	4		T35	14		T208	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T195	9		T122	4		T203	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T195	12		T201	5		T139	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T220	14		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T123	11		T275	11		T241	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T138	6		T151	11		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T195	11		T126	6		T236	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T42	1		T149	1		T176	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T123	12		T200	1		T38	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T138	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T126	9		T20	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T135	1		T202	12		T150	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T10	15		T195	11		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	1		T5	3		T34	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T6	1		T93	4		T121	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T8	23		T15	15		T136	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	12		T28	2		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	1		T34	1		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T142	12		T126	12		T299	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T14	3		T139	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T5	2		T7	14		T8	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T125	1		T160	1		T276	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T1	14		T93	11		T27	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	2		T6	13		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T135	1		T46	11		T28	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T93	3		T136	7		T143	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	7		T35	27		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1519	1			T9	12		T11	18		T12	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T23	3		T195	3		T201	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T1	1		T2	20		T3	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T149	11		T155	6		T242	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T123	11		T184	3		T302	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T138	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T126	6		T20	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T135	12		T202	10		T150	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T10	14		T195	11		T140	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T5	3		T34	9		T16	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T123	11		T154	10		T75	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T8	21		T15	4		T123	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T28	1		T30	2		T39	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	8		T34	5		T46	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T126	11		T290	10		T194	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T14	1		T139	13		T154	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	9		T8	7		T34	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T125	16		T265	9		T289	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T27	3		T154	16		T203	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T5	2		T6	4		T135	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T135	4		T46	9		T26	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T143	13		T38	3		T217	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T7	4		T35	14		T240	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1320	1			T12	21		T36	12		T134	27
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T195	12		T201	5		T139	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

auto[0]

4215

1

T5

5

T6

4

T7

13