Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26972

1

T1

16

T2

20

T3

169

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23317

1

T1

16

T2

20

T3

169

auto[ADC_CTRL_FILTER_COND_OUT]

3655

1

T5

4

T6

18

T7

34

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21077

1

T1

2

T2

20

T3

169

auto[1]

5895

1

T1

14

T5

2

T6

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22708

1

T1

2

T2

20

T3

169

auto[1]

4264

1

T1

14

T5

7

T6

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	288	1			T5	2		T34	11		T35	12
values[0]	49	1			T1	14		T151	22		T276	13
values[1]	748	1			T8	16		T34	6		T93	11
values[2]	573	1			T1	1		T93	7		T136	15
values[3]	706	1			T5	6		T6	13		T35	13
values[4]	603	1			T6	17		T13	9		T202	22
values[5]	3089	1			T8	44		T9	12		T11	18
values[6]	745	1			T35	16		T14	4		T198	1
values[7]	1061	1			T5	4		T7	11		T10	29
values[8]	571	1			T7	23		T23	3		T34	10
values[9]	1011	1			T15	9		T135	24		T46	12
minimum	17528	1			T1	1		T2	20		T3	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	705	1			T1	1		T8	16		T93	3
values[1]	625	1			T93	4		T28	3		T136	15
values[2]	682	1			T5	6		T6	13		T35	13
values[3]	2918	1			T6	17		T8	44		T9	12
values[4]	824	1			T28	8		T142	8		T124	22
values[5]	849	1			T35	16		T14	4		T195	15
values[6]	894	1			T5	4		T7	11		T10	29
values[7]	765	1			T7	23		T23	3		T34	10
values[8]	944	1			T34	11		T35	12		T15	19
values[9]	63	1			T5	2		T39	10		T160	1
minimum	17703	1			T1	15		T2	20		T3	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

4215

1

T5

5

T6

4

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T1	1		T8	8		T93	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T137	1		T226	1		T150	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T93	1		T137	1		T123	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T28	2		T136	1		T122	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	4		T6	1		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	1		T35	4		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1563	1			T8	22		T9	1		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T6	5		T13	9		T126	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T28	4		T37	5		T127	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T142	8		T124	11		T24	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T35	10		T14	3		T198	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T195	13		T123	12		T203	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T195	10		T136	1		T211	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	4		T7	5		T10	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T23	1		T135	13		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T7	10		T34	10		T15	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T135	5		T16	1		T139	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T34	11		T35	3		T15	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T5	2		T39	7		T291	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T160	1		T294	20		T279	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17435	1			T1	1		T2	20		T3	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T34	6		T93	1		T141	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T8	8		T93	2		T27	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T226	17		T75	9		T151	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T93	3		T123	17		T38	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T28	1		T136	14		T122	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T5	2		T6	11		T121	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T35	9		T141	14		T38	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1134	1			T8	22		T9	11		T11	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T6	12		T126	8		T227	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T28	4		T37	3		T127	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T124	11		T24	2		T30	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T35	6		T14	1		T201	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T195	2		T123	11		T203	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T195	2		T136	11		T211	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T7	6		T10	14		T29	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T23	2		T140	1		T143	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	13		T15	5		T46	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T127	1		T208	11		T182	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T35	9		T15	12		T16	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T39	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T294	17		T279	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	14		T5	5		T6	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T93	10		T141	3		T276	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T5	2		T16	1		T139	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T34	11		T35	3		T15	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T1	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T151	12		T276	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T8	8		T27	8		T214	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T34	6		T93	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T1	1		T93	2		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T136	1		T137	1		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	4		T6	1		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	1		T35	4		T28	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T202	11		T139	14		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T6	5		T13	9		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1596	1			T8	22		T9	1		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T142	8		T124	11		T24	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T35	10		T14	3		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T123	12		T203	15		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T195	10		T211	10		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T5	4		T7	5		T10	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T23	1		T136	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	10		T34	10		T46	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T135	18		T143	14		T154	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T15	4		T135	6		T46	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17413	1			T2	20		T3	169		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T127	1		T39	3		T182	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T35	9		T15	12		T16	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T1	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T151	10		T276	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	8		T27	5		T214	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T93	10		T141	3		T226	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T93	5		T123	17		T38	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T136	14		T75	9		T210	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	2		T6	11		T121	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T35	9		T28	1		T122	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T202	11		T142	11		T124	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T6	12		T38	12		T126	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1101	1			T8	22		T9	11		T11	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T124	11		T24	2		T30	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T35	6		T14	1		T201	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T123	11		T203	17		T156	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T195	2		T211	10		T150	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	6		T10	14		T195	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T23	2		T136	11		T140	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	13		T46	10		T29	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T143	18		T25	9		T197	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T15	5		T126	11		T214	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T5	5		T6	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T1	1		T8	9		T93	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T137	1		T226	18		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T93	4		T137	1		T123	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T28	2		T136	15		T122	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	3		T6	12		T121	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T6	1		T35	10		T141	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1471	1			T8	23		T9	12		T11	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T6	13		T13	1		T126	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T28	8		T37	4		T127	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T142	1		T124	12		T24	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T35	7		T14	3		T198	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T195	3		T123	12		T203	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T195	3		T136	12		T211	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	2		T7	7		T10	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T23	3		T135	1		T140	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T7	14		T34	1		T15	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T135	1		T16	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T34	1		T35	10		T15	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T5	2		T39	4		T291	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T160	1		T294	18		T279	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17572	1			T1	15		T2	20		T3	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T34	1		T93	11		T141	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T8	7		T27	3		T77	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T150	14		T75	8		T151	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T123	13		T38	3		T149	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T28	1		T122	4		T78	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	3		T138	6		T195	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T35	3		T208	5		T26	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T8	21		T12	21		T36	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T6	4		T13	8		T126	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T37	4		T127	9		T236	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T142	7		T124	10		T24	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T35	9		T14	1		T201	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T195	12		T123	11		T203	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T195	9		T211	9		T150	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T5	2		T7	4		T10	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T135	12		T143	13		T154	26
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	9		T34	9		T46	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T135	4		T139	13		T208	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T34	10		T35	2		T15	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T39	6		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T294	19		T279	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T164	18		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T34	5		T125	16		T217	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T5	2		T16	1		T139	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T34	1		T35	10		T15	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T1	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T151	11		T276	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T8	9		T27	10		T214	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T34	1		T93	11		T141	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	1		T93	7		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T136	15		T137	1		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	3		T6	12		T121	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T6	1		T35	10		T28	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T202	12		T139	1		T142	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	13		T13	1		T38	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1443	1			T8	23		T9	12		T11	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T142	1		T124	12		T24	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T35	7		T14	3		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T123	12		T203	18		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T195	3		T211	11		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T5	2		T7	7		T10	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T23	3		T136	12		T140	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	14		T34	1		T46	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T135	2		T143	19		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T15	9		T135	1		T46	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T1	1		T2	20		T3	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T139	13		T39	6		T182	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T34	10		T35	2		T15	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T151	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T8	7		T27	3		T33	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T34	5		T125	16		T150	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T123	13		T38	3		T77	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T75	8		T78	8		T210	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	3		T138	6		T195	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T35	3		T28	1		T122	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T202	10		T139	13		T124	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T6	4		T13	8		T126	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T8	21		T12	21		T36	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T142	7		T124	10		T24	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T35	9		T14	1		T201	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T123	11		T203	14		T88	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T195	9		T211	9		T150	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T5	2		T7	4		T10	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T154	16		T125	11		T126	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	9		T34	9		T46	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T135	16		T143	13		T154	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T135	5		T46	11		T149	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

auto[0]

4215

1

T5

5

T6

4

T7

13