Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26972

1

T1

16

T2

20

T3

169

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23286

1

T1

2

T2

20

T3

169

auto[ADC_CTRL_FILTER_COND_OUT]

3686

1

T1

14

T6

13

T7

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20848

1

T1

1

T2

20

T3

169

auto[1]

6124

1

T1

15

T6

29

T7

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22708

1

T1

2

T2

20

T3

169

auto[1]

4264

1

T1

14

T5

7

T6

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	44	1			T123	23		T200	1		T275	9
values[0]	62	1			T138	7		T126	15		T163	1
values[1]	886	1			T10	29		T195	22		T135	13
values[2]	739	1			T1	1		T5	6		T6	13
values[3]	750	1			T8	44		T15	19		T28	3
values[4]	687	1			T13	9		T34	6		T46	12
values[5]	647	1			T5	2		T7	23		T8	16
values[6]	696	1			T1	14		T34	11		T93	11
values[7]	618	1			T5	4		T6	17		T135	5
values[8]	692	1			T93	3		T35	41		T135	6
values[9]	3623	1			T7	11		T9	12		T11	18
minimum	17528	1			T1	1		T2	20		T3	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1063	1			T6	1		T10	29		T138	7
values[1]	600	1			T1	1		T5	6		T6	12
values[2]	846	1			T93	4		T15	19		T28	3
values[3]	669	1			T5	2		T7	23		T8	16
values[4]	760	1			T34	11		T46	5		T139	14
values[5]	627	1			T1	14		T93	11		T27	13
values[6]	2897	1			T5	4		T6	17		T9	12
values[7]	732	1			T7	11		T35	41		T136	7
values[8]	1035	1			T23	3		T15	9		T195	27
values[9]	152	1			T123	23		T217	1		T242	13
minimum	17591	1			T1	1		T2	20		T3	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

4215

1

T5

5

T6

4

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T138	7		T135	13		T202	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T6	1		T10	15		T195	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T1	1		T5	4		T8	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T6	1		T34	10		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T15	7		T137	1		T123	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T93	1		T28	2		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T5	2		T7	10		T13	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T8	8		T34	6		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T139	14		T226	1		T196	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T34	11		T46	5		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T28	4		T149	17		T125	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T1	1		T93	1		T27	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1526	1			T5	4		T6	5		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T135	5		T46	10		T199	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T136	1		T143	28		T38	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T7	5		T35	17		T188	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T15	4		T195	10		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T23	1		T195	13		T201	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T217	1		T297	19		T303	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T123	12		T242	13		T271	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17425	1			T2	20		T3	169		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T304	10		T305	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T202	11		T150	11		T24	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T10	14		T195	10		T140	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	2		T8	22		T136	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T6	11		T121	8		T123	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T15	12		T123	17		T77	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T93	3		T28	1		T142	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	13		T14	1		T141	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T8	8		T150	9		T126	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T226	17		T221	5		T184	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T140	1		T124	2		T37	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T28	4		T162	15		T89	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	13		T93	10		T27	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T6	12		T9	11		T11	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T46	10		T26	11		T250	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T136	6		T143	32		T38	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	6		T35	24		T224	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T15	5		T195	2		T136	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T23	2		T195	2		T201	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T297	18		T303	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T123	11		T271	11		T233	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T1	1		T5	5		T6	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T304	14		T305	10		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T275	9		T300	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T123	12		T200	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T138	7		T163	1		T298	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T126	7		T81	3		T20	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T135	13		T202	11		T150	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T10	15		T195	12		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T1	1		T5	4		T16	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	2		T34	10		T93	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T8	22		T15	7		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T28	2		T200	1		T30	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	9		T46	12		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T34	6		T142	1		T126	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	2		T7	10		T14	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T8	8		T46	5		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T149	17		T125	17		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	1		T34	11		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T5	4		T6	5		T28	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T135	5		T46	10		T214	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T93	1		T135	6		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T35	17		T199	1		T188	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1728	1			T9	1		T11	2		T12	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T7	5		T23	1		T195	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17413	1			T2	20		T3	169		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T300	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T123	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T126	8		T81	2		T20	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T202	11		T24	2		T151	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	14		T195	10		T140	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	2		T16	8		T150	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	11		T93	3		T121	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T8	22		T15	12		T136	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T28	1		T30	1		T39	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T210	12		T88	9		T164	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T142	11		T126	11		T197	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	13		T14	1		T141	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T8	8		T140	1		T124	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T276	14		T301	4		T265	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	13		T93	10		T27	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T6	12		T28	4		T186	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T46	10		T214	10		T227	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T93	2		T136	6		T143	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T35	24		T224	14		T32	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1164	1			T9	11		T11	16		T148	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T7	6		T23	2		T195	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T5	5		T6	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T138	1		T135	1		T202	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T6	1		T10	15		T195	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T1	1		T5	3		T8	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	12		T34	1		T121	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T15	15		T137	1		T123	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T93	4		T28	2		T142	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	2		T7	14		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T8	9		T34	1		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T139	1		T226	18		T196	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T34	1		T46	1		T140	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T28	8		T149	1		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	14		T93	11		T27	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1373	1			T5	2		T6	13		T9	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T135	1		T46	11		T199	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T136	7		T143	34		T38	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T7	7		T35	27		T188	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T15	9		T195	3		T136	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T23	3		T195	3		T201	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T217	1		T297	20		T303	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T123	12		T242	1		T271	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17539	1			T1	1		T2	20		T3	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T304	15		T305	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T138	6		T135	12		T202	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T10	14		T195	11		T140	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T5	3		T8	21		T16	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T34	9		T123	11		T278	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T15	4		T123	13		T77	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T28	1		T30	2		T39	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	9		T13	8		T14	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T8	7		T34	5		T149	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T139	13		T221	5		T219	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T34	10		T46	4		T124	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T149	16		T125	16		T265	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T27	3		T203	14		T151	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1194	1			T5	2		T6	4		T12	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T135	4		T46	9		T26	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T143	26		T38	3		T217	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T7	4		T35	14		T208	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T195	9		T122	4		T124	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T195	12		T201	5		T139	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T297	17		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T123	11		T242	12		T275	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T258	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T304	9		T305	6		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T275	1		T300	11		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T123	12		T200	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T138	1		T163	1		T298	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T126	9		T81	4		T20	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T135	1		T202	12		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T10	15		T195	11		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	1		T5	3		T16	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	13		T34	1		T93	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T8	23		T15	15		T136	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T28	2		T200	1		T30	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	1		T46	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T34	1		T142	12		T126	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	2		T7	14		T14	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T8	9		T46	1		T140	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T149	1		T125	1		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T1	14		T34	1		T93	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	2		T6	13		T28	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T135	1		T46	11		T214	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T93	3		T135	1		T136	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T35	27		T199	1		T188	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1531	1			T9	12		T11	18		T12	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	439	1			T7	7		T23	3		T195	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T1	1		T2	20		T3	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T275	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T123	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T138	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T126	6		T81	1		T20	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T135	12		T202	10		T150	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T10	14		T195	11		T140	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	3		T16	14		T150	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T34	9		T123	11		T154	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T8	21		T15	4		T123	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T28	1		T30	2		T39	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	8		T46	11		T210	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T34	5		T126	11		T182	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	9		T14	1		T139	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T8	7		T46	4		T124	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T149	16		T125	16		T265	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T34	10		T27	3		T154	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T5	2		T6	4		T253	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T135	4		T46	9		T26	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T135	5		T143	13		T38	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T35	14		T183	7		T253	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1361	1			T12	21		T36	12		T134	27
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T7	4		T195	12		T201	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

auto[0]

4215

1

T5

5

T6

4

T7

13