Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26972

1

T1

16

T2

20

T3

169

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23201

1

T1

1

T2

20

T3

169

auto[ADC_CTRL_FILTER_COND_OUT]

3771

1

T1

15

T5

4

T6

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20609

1

T1

1

T2

20

T3

169

auto[1]

6363

1

T1

15

T5

2

T6

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22708

1

T1

2

T2

20

T3

169

auto[1]

4264

1

T1

14

T5

7

T6

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	273	1			T8	16		T138	7		T136	12
values[0]	42	1			T245	12		T204	4		T283	9
values[1]	683	1			T1	14		T5	2		T6	1
values[2]	645	1			T6	17		T195	37		T202	22
values[3]	818	1			T7	23		T34	11		T35	16
values[4]	3021	1			T9	12		T11	18		T12	23
values[5]	708	1			T5	6		T35	13		T121	9
values[6]	732	1			T5	4		T7	11		T10	29
values[7]	742	1			T1	1		T93	15		T135	11
values[8]	689	1			T6	12		T23	3		T34	6
values[9]	1091	1			T8	44		T13	9		T15	9
minimum	17528	1			T1	1		T2	20		T3	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	736	1			T1	14		T5	2		T6	1
values[1]	672	1			T6	17		T195	22		T135	13
values[2]	691	1			T7	23		T34	11		T35	16
values[3]	3070	1			T9	12		T11	18		T12	23
values[4]	770	1			T5	6		T7	11		T35	13
values[5]	723	1			T5	4		T10	29		T35	12
values[6]	728	1			T1	1		T93	15		T135	6
values[7]	610	1			T6	12		T23	3		T34	6
values[8]	1149	1			T8	60		T13	9		T15	9
values[9]	116	1			T138	7		T136	12		T211	20
minimum	17707	1			T1	1		T2	20		T3	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

4215

1

T5

5

T6

4

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	2		T6	1		T195	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T1	1		T199	1		T125	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T195	12		T200	1		T31	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T6	5		T135	13		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	10		T35	10		T15	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T34	11		T198	1		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1597	1			T9	1		T11	2		T12	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T46	12		T28	4		T124	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	4		T35	4		T27	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	5		T14	3		T139	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T35	3		T135	5		T149	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T5	4		T10	15		T201	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T93	1		T136	1		T200	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	1		T93	1		T135	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T34	6		T93	1		T280	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T6	1		T23	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T15	4		T46	10		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	428	1			T8	30		T13	9		T200	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T138	7		T149	2		T19	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T136	1		T211	10		T152	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17465	1			T2	20		T3	169		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T143	14		T281	1		T88	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T195	2		T202	11		T142	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	13		T144	13		T162	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T195	10		T31	1		T32	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	12		T141	3		T144	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	13		T35	6		T15	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T123	9		T226	4		T25	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1113	1			T9	11		T11	16		T148	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T28	4		T124	12		T203	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	2		T35	9		T27	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	6		T14	1		T208	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T35	9		T150	11		T214	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T10	14		T201	2		T122	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T93	3		T136	6		T126	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T93	10		T28	1		T123	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T93	2		T216	2		T212	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T6	11		T23	2		T124	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T15	5		T46	10		T197	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T8	30		T213	10		T150	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T273	15		T21	2		T306	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T136	11		T211	10		T307	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	1		T5	5		T6	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T143	18		T88	9		T231	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T138	7		T149	2		T161	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T8	8		T136	1		T211	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T245	12		T283	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T204	1		T308	1		T309	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	2		T6	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T1	1		T143	14		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T195	25		T202	11		T200	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T6	5		T141	1		T199	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	10		T35	10		T15	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T34	11		T135	13		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1581	1			T9	1		T11	2		T12	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T46	12		T28	4		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T5	4		T35	4		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T14	3		T139	14		T203	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T35	3		T149	12		T250	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T5	4		T7	5		T10	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T93	1		T135	5		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	1		T93	1		T135	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T34	6		T93	1		T200	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	1		T23	1		T28	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T15	4		T46	10		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	399	1			T8	22		T13	9		T200	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17413	1			T2	20		T3	169		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T264	8		T256	6		T257	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T8	8		T136	11		T211	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T283	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T204	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T141	14		T142	11		T39	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	13		T143	18		T144	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T195	12		T202	11		T127	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T6	12		T141	3		T144	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	13		T35	6		T15	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T123	9		T226	4		T224	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1103	1			T9	11		T11	16		T148	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T28	4		T124	12		T126	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	2		T35	9		T121	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T14	1		T203	17		T24	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T35	9		T204	2		T310	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T7	6		T10	14		T201	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T93	3		T136	6		T150	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T93	10		T122	4		T123	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T93	2		T126	11		T216	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	11		T23	2		T28	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T15	5		T46	10		T197	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T8	22		T213	10		T150	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T5	5		T6	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T5	2		T6	1		T195	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	14		T199	1		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T195	11		T200	1		T31	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T6	13		T135	1		T141	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	14		T35	7		T15	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T34	1		T198	1		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1456	1			T9	12		T11	18		T12	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T46	1		T28	8		T124	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T5	3		T35	10		T27	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	7		T14	3		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T35	10		T135	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T5	2		T10	15		T201	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T93	4		T136	7		T200	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	1		T93	11		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T34	1		T93	3		T280	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	12		T23	3		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T15	9		T46	11		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T8	32		T13	1		T200	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T138	1		T149	1		T19	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T136	12		T211	11		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17569	1			T1	1		T2	20		T3	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T143	19		T281	1		T88	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T195	12		T202	10		T78	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T125	16		T85	16		T311	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T195	11		T31	2		T182	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T6	4		T135	12		T151	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	9		T35	9		T15	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T34	10		T123	11		T25	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T12	21		T34	9		T36	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T46	11		T203	14		T126	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	3		T35	3		T27	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T7	4		T14	1		T139	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T35	2		T135	4		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	2		T10	14		T201	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T150	14		T126	11		T127	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T135	5		T46	4		T28	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T34	5		T242	12		T237	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T124	10		T77	9		T151	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T46	9		T154	10		T125	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T8	28		T13	8		T154	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T138	6		T149	1		T19	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T211	9		T152	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T78	8		T245	11		T173	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T143	13		T88	4		T219	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T138	1		T149	1		T161	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T8	9		T136	12		T211	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T245	1		T283	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T204	4		T308	1		T309	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	2		T6	1		T141	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T1	14		T143	19		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T195	14		T202	12		T200	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	13		T141	4		T199	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	14		T35	7		T15	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T34	1		T135	1		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1442	1			T9	12		T11	18		T12	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T46	1		T28	8		T124	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T5	3		T35	10		T121	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	3		T139	1		T203	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T35	10		T149	1		T250	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T5	2		T7	7		T10	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T93	4		T135	1		T136	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	1		T93	11		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T34	1		T93	3		T200	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	12		T23	3		T28	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T15	9		T46	11		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T8	23		T13	1		T200	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T1	1		T2	20		T3	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T138	6		T149	1		T286	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T8	7		T211	9		T183	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T245	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T309	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T78	15		T39	6		T240	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T143	13		T125	16		T88	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T195	23		T202	10		T31	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T6	4		T151	11		T210	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	9		T35	9		T15	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T34	10		T135	12		T123	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T12	21		T34	9		T36	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T46	11		T126	15		T291	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	3		T35	3		T27	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T14	1		T139	13		T203	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T35	2		T149	11		T286	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T5	2		T7	4		T10	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T135	4		T150	26		T127	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T135	5		T46	4		T122	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T34	5		T126	11		T249	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T28	1		T124	10		T151	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T46	9		T154	10		T125	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T8	21		T13	8		T154	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

auto[0]

4215

1

T5

5

T6

4

T7

13