Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26972

1

T1

16

T2

20

T3

169

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20950

1

T1

16

T2

20

T3

169

auto[ADC_CTRL_FILTER_COND_OUT]

6022

1

T5

4

T6

29

T8

44

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21184

1

T1

2

T2

20

T3

169

auto[1]

5788

1

T1

14

T5

10

T6

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22708

1

T1

2

T2

20

T3

169

auto[1]

4264

1

T1

14

T5

7

T6

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	252	1			T42	1		T29	3		T144	10
values[0]	49	1			T233	3		T232	19		T312	14
values[1]	771	1			T138	7		T135	13		T136	12
values[2]	876	1			T5	6		T6	12		T34	10
values[3]	880	1			T23	3		T195	12		T46	20
values[4]	683	1			T13	9		T35	16		T137	1
values[5]	569	1			T7	11		T10	29		T135	5
values[6]	535	1			T34	6		T28	3		T16	1
values[7]	695	1			T1	1		T6	17		T7	23
values[8]	687	1			T8	60		T123	23		T38	13
values[9]	3447	1			T1	14		T5	6		T6	1
minimum	17528	1			T1	1		T2	20		T3	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	879	1			T27	13		T138	7		T135	13
values[1]	3179	1			T5	6		T6	12		T9	12
values[2]	729	1			T23	3		T195	12		T46	20
values[3]	670	1			T7	11		T13	9		T35	16
values[4]	618	1			T10	29		T34	6		T135	5
values[5]	588	1			T7	23		T28	3		T16	1
values[6]	668	1			T1	1		T6	17		T34	11
values[7]	688	1			T8	60		T122	1		T38	20
values[8]	1085	1			T1	14		T5	6		T6	1
values[9]	148	1			T136	15		T224	15		T217	10
minimum	17720	1			T1	1		T2	20		T3	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

4215

1

T5

5

T6

4

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T27	8		T138	7		T136	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T135	13		T123	12		T25	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	4		T34	10		T195	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1596	1			T6	1		T9	1		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T23	1		T195	10		T125	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T46	10		T203	4		T149	29
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	5		T13	9		T35	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T140	13		T37	1		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T34	6		T46	17		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T10	15		T135	5		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	10		T28	2		T139	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T16	1		T199	2		T176	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	1		T34	11		T93	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T6	5		T93	1		T15	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T8	8		T38	4		T154	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T8	22		T122	1		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T1	1		T5	2		T6	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T5	4		T35	3		T28	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T217	10		T228	13		T229	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T136	1		T224	1		T227	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17457	1			T2	20		T3	169		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T37	5		T77	10		T172	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T27	5		T136	11		T124	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T123	9		T25	9		T182	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	2		T195	10		T16	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1202	1			T6	11		T9	11		T11	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T23	2		T195	2		T150	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T46	10		T203	3		T225	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T7	6		T35	6		T210	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T140	7		T226	2		T127	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T136	6		T143	18		T150	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	14		T124	12		T197	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	13		T28	1		T140	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T214	10		T31	1		T227	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T93	10		T14	1		T201	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	12		T93	3		T15	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	8		T38	3		T151	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T8	22		T38	12		T75	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T1	13		T121	8		T195	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T35	9		T28	4		T141	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T228	1		T229	1		T313	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T136	14		T224	14		T227	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T1	1		T5	5		T6	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T37	3		T77	12		T253	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T42	1		T89	1		T209	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T29	2		T144	1		T224	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T232	9		T312	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T233	1		T314	1		T244	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T138	7		T136	1		T124	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T135	13		T37	5		T77	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	4		T34	10		T27	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	1		T93	1		T35	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T23	1		T195	10		T150	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T46	10		T142	8		T203	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	9		T35	10		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T37	1		T200	1		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	5		T46	17		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T10	15		T135	5		T140	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T34	6		T28	2		T139	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T16	1		T199	2		T176	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	1		T7	10		T34	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T6	5		T93	1		T15	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	8		T199	1		T151	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T8	22		T123	12		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T1	1		T5	2		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1730	1			T5	4		T9	1		T11	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17413	1			T2	20		T3	169		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T89	8		T209	7		T276	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T29	1		T144	9		T224	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T232	10		T312	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T233	2		T314	9		T244	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T136	11		T124	11		T127	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T37	3		T77	12		T182	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	2		T27	5		T195	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T6	11		T93	2		T35	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T23	2		T195	2		T150	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T46	10		T203	20		T126	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T35	6		T210	7		T208	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T226	2		T127	1		T237	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T7	6		T136	6		T143	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T10	14		T140	7		T124	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T28	1		T143	14		T238	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T214	10		T223	10		T26	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T7	13		T93	10		T14	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T6	12		T93	3		T15	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	8		T151	12		T39	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	22		T123	11		T38	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	13		T121	8		T195	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1210	1			T9	11		T11	16		T148	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T5	5		T6	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T27	10		T138	1		T136	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T135	1		T123	10		T25	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T5	3		T34	1		T195	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1548	1			T6	12		T9	12		T11	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T23	3		T195	3		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T46	11		T203	4		T149	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	7		T13	1		T35	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T140	8		T37	1		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T34	1		T46	2		T136	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	15		T135	1		T124	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	14		T28	2		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T16	1		T199	2		T176	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	1		T34	1		T93	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	13		T93	4		T15	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T8	9		T38	4		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	23		T122	1		T38	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T1	14		T5	2		T6	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T5	2		T35	10		T28	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T217	1		T228	2		T229	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T136	15		T224	15		T227	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17548	1			T1	1		T2	20		T3	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T37	4		T77	13		T172	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T27	3		T138	6		T124	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T135	12		T123	11		T25	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	3		T34	9		T195	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1250	1			T12	21		T35	3		T36	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T195	9		T125	11		T150	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T46	9		T203	3		T149	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	4		T13	8		T35	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T140	12		T234	15		T239	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T34	5		T46	15		T143	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T10	14		T135	4		T197	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	9		T28	1		T139	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T31	2		T240	2		T223	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T34	10		T14	1		T201	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	4		T202	10		T122	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T8	7		T38	3		T154	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T8	21		T75	8		T152	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T195	12		T124	1		T125	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T5	2		T35	2		T29	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T217	9		T228	12		T313	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T290	10		T165	17		T243	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T221	5		T315	18		T285	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T37	4		T77	9		T253	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T42	1		T89	9		T209	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T29	2		T144	10		T224	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T232	11		T312	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T233	3		T314	10		T244	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T138	1		T136	12		T124	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T135	1		T37	4		T77	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T5	3		T34	1		T27	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T6	12		T93	3		T35	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T23	3		T195	3		T150	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T46	11		T142	1		T203	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	1		T35	7		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T37	1		T200	1		T226	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	7		T46	2		T136	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T10	15		T135	1		T140	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T34	1		T28	2		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T16	1		T199	2		T176	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T1	1		T7	14		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T6	13		T93	4		T15	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T8	9		T199	1		T151	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	23		T123	12		T38	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T1	14		T5	2		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1584	1			T5	2		T9	12		T11	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T1	1		T2	20		T3	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T258	11		T316	13		T317	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T29	1		T252	10		T302	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T232	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T244	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T138	6		T124	10		T127	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T135	12		T37	4		T77	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	3		T34	9		T27	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T35	3		T15	4		T135	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T195	9		T150	12		T236	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T46	9		T142	7		T203	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	8		T35	9		T125	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T234	15		T239	19		T157	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	4		T46	15		T143	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T10	14		T135	4		T140	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T34	5		T28	1		T139	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T223	4		T26	11		T318	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	9		T34	10		T14	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T6	4		T202	10		T122	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T8	7		T151	11		T39	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T8	21		T123	11		T75	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T195	12		T124	1		T38	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1356	1			T5	2		T12	21		T35	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

auto[0]

4215

1

T5

5

T6

4

T7

13