Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T34	1		T27	10		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T135	1		T123	10		T37	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	3		T195	11		T16	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1517	1			T6	12		T9	12		T11	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T23	3		T195	3		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T46	11		T203	4		T149	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	7		T13	1		T35	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T140	8		T37	1		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T34	1		T46	2		T136	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	15		T135	1		T124	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	14		T28	2		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T16	1		T199	1		T176	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T34	1		T93	11		T14	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	13		T8	23		T93	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	1		T8	9		T38	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	2		T15	9		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T1	14		T5	2		T121	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T35	10		T28	8		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T6	1		T78	1		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T136	15		T224	15		T216	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T1	1		T2	20		T3	169
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T34	9		T27	3		T138	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T135	12		T123	11		T37	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	3		T195	11		T16	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1251	1			T12	21		T35	3		T36	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T195	9		T125	11		T150	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T46	9		T203	3		T149	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	4		T13	8		T35	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T140	12		T239	19		T157	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T34	5		T46	15		T143	26
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T10	14		T135	4		T197	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	9		T28	1		T139	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T31	2		T240	2		T223	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T34	10		T14	1		T201	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	4		T8	21		T202	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	7		T38	3		T154	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	2		T123	11		T75	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T195	12		T124	1		T125	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T35	2		T29	1		T151	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T78	7		T217	9		T241	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T242	7		T165	17		T243	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T222	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T221	6		T231	8		T232	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T37	4		T223	1		T233	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T138	1		T136	12		T16	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T135	1		T77	13		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T5	3		T34	1		T27	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T6	12		T35	10		T15	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T195	3		T150	12		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T93	3		T46	11		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	1		T23	3		T35	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T226	3		T127	2		T234	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	7		T46	2		T136	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T10	15		T135	1		T140	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T34	1		T28	2		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T16	1		T199	1		T176	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T1	1		T7	14		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T6	13		T93	4		T15	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	9		T199	1		T151	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T8	23		T122	5		T123	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	354	1			T1	14		T5	2		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1660	1			T5	2		T9	12		T11	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T1	1		T2	20		T3	169
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T221	5		T232	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T37	4		T244	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T138	6		T16	14		T124	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T135	12		T77	9		T182	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	3		T34	9		T27	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T35	3		T15	4		T135	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T195	9		T150	12		T126	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T46	9		T142	7		T203	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	8		T35	9		T125	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T234	15		T239	19		T157	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	4		T46	15		T143	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T10	14		T135	4		T140	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T34	5		T28	1		T139	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T33	1		T223	4		T26	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	9		T34	10		T14	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T6	4		T202	10		T245	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T8	7		T151	11		T39	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	21		T122	4		T123	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T195	12		T124	1		T38	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1404	1			T5	2		T12	21		T35	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

auto[0]

4215

1

T5

5

T6

4

T7

13