Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26972

1

T1

16

T2

20

T3

169

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23261

1

T1

2

T2

20

T3

169

auto[ADC_CTRL_FILTER_COND_OUT]

3711

1

T1

14

T5

6

T7

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20852

1

T1

1

T2

20

T3

169

auto[1]

6120

1

T1

15

T5

6

T6

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22708

1

T1

2

T2

20

T3

169

auto[1]

4264

1

T1

14

T5

7

T6

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	302	1			T23	3		T135	5		T28	8
values[1]	581	1			T121	9		T135	6		T46	12
values[2]	2958	1			T7	23		T9	12		T11	18
values[3]	857	1			T8	44		T10	29		T93	4
values[4]	735	1			T8	16		T35	13		T198	1
values[5]	672	1			T34	6		T15	9		T136	12
values[6]	705	1			T1	1		T6	17		T138	7
values[7]	767	1			T5	6		T6	12		T7	11
values[8]	815	1			T1	14		T5	4		T6	1
values[9]	1052	1			T5	2		T13	9		T14	4
minimum	17528	1			T1	1		T2	20		T3	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	589	1			T7	23		T93	3		T121	9
values[1]	3075	1			T9	12		T11	18		T12	23
values[2]	761	1			T8	60		T10	29		T137	1
values[3]	775	1			T34	6		T35	13		T15	9
values[4]	699	1			T195	34		T136	12		T125	12
values[5]	567	1			T1	1		T5	6		T6	17
values[6]	851	1			T1	14		T6	12		T93	11
values[7]	757	1			T5	6		T6	1		T35	12
values[8]	1039	1			T23	3		T195	15		T135	5
values[9]	183	1			T13	9		T15	19		T135	13
minimum	17676	1			T1	1		T2	20		T3	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

4215

1

T5

5

T6

4

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T46	22		T127	10		T78	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	10		T93	1		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1557	1			T9	1		T11	2		T12	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T34	10		T93	1		T139	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T8	30		T143	14		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T10	15		T137	1		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T15	4		T198	1		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T34	6		T35	4		T16	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T195	10		T160	1		T208	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T195	12		T136	1		T125	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T1	1		T6	5		T7	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	4		T27	8		T138	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	1		T142	8		T149	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T1	1		T93	1		T136	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	6		T6	1		T35	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T46	5		T42	1		T149	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T23	1		T195	13		T135	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T28	2		T202	11		T139	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T13	9		T15	7		T135	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T155	1		T246	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17463	1			T2	20		T3	169		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T140	1		T151	12		T184	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T46	10		T127	4		T214	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T7	13		T93	2		T121	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1103	1			T9	11		T11	16		T148	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T93	3		T124	2		T150	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T8	30		T143	14		T197	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T10	14		T142	11		T143	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T15	5		T226	2		T227	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T35	9		T16	8		T123	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T195	2		T208	2		T81	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T195	10		T136	11		T224	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T6	12		T7	6		T140	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	2		T27	5		T141	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	11		T126	8		T24	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T1	13		T93	10		T136	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T35	9		T14	1		T124	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T77	12		T151	12		T227	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T23	2		T195	2		T28	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T28	1		T202	11		T123	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T15	12		T75	9		T210	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T246	19		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	1		T5	5		T6	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T140	1		T151	10		T247	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T23	1		T135	5		T28	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T123	14		T203	4		T248	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T135	6		T46	12		T127	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T121	1		T140	1		T150	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1544	1			T9	1		T11	2		T12	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	10		T34	10		T93	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T8	22		T137	1		T122	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T10	15		T93	1		T139	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T8	8		T198	1		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T35	4		T137	1		T154	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	4		T208	3		T81	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T34	6		T136	1		T16	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	1		T6	5		T195	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T138	7		T195	12		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T6	1		T7	5		T142	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	4		T93	1		T27	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	4		T6	1		T35	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T1	1		T46	5		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T5	2		T13	9		T14	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T28	2		T202	11		T139	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17413	1			T2	20		T3	169		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T23	2		T28	4		T124	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T123	17		T203	3		T248	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T127	4		T151	10		T214	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T121	8		T140	1		T150	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1079	1			T9	11		T11	16		T148	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T7	13		T93	2		T201	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	22		T122	4		T143	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T10	14		T93	3		T142	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T8	8		T226	2		T227	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T35	9		T213	10		T240	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T15	5		T208	2		T81	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T136	11		T16	8		T123	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T6	12		T195	2		T140	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T195	10		T141	3		T236	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T6	11		T7	6		T211	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	2		T93	10		T27	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T35	9		T38	3		T126	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T1	13		T141	14		T37	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T14	1		T15	12		T195	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T28	1		T202	11		T226	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T5	5		T6	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T46	12		T127	5		T78	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	14		T93	3		T121	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1445	1			T9	12		T11	18		T12	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T34	1		T93	4		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T8	32		T143	15		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T10	15		T137	1		T142	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T15	9		T198	1		T226	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T34	1		T35	10		T16	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T195	3		T160	1		T208	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T195	11		T136	12		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	1		T6	13		T7	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	3		T27	10		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	12		T142	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T1	14		T93	11		T136	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T5	4		T6	1		T35	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T46	1		T42	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T23	3		T195	3		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T28	2		T202	12		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T13	1		T15	15		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T155	1		T246	20		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17581	1			T1	1		T2	20		T3	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T140	2		T151	11		T184	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T46	20		T127	9		T78	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T7	9		T201	5		T150	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T12	21		T34	10		T35	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T34	9		T139	13		T124	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T8	28		T143	13		T249	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	14		T143	13		T125	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T150	14		T152	9		T26	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T34	5		T35	3		T16	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T195	9		T208	2		T81	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T195	11		T125	11		T197	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T6	4		T7	4		T140	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T5	3		T27	3		T138	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T142	7		T149	1		T126	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T37	4		T155	3		T85	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	2		T35	2		T14	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T46	4		T149	11		T77	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T195	12		T135	4		T29	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T28	1		T202	10		T139	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T13	8		T15	4		T135	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T151	7		T242	7		T250	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T151	11		T247	5		T251	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T23	3		T135	1		T28	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T123	18		T203	4		T248	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T135	1		T46	1		T127	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T121	9		T140	2		T150	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1416	1			T9	12		T11	18		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	14		T34	1		T93	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T8	23		T137	1		T122	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T10	15		T93	4		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T8	9		T198	1		T226	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T35	10		T137	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T15	9		T208	3		T81	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T34	1		T136	12		T16	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T1	1		T6	13		T195	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T138	1		T195	11		T141	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	12		T7	7		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T5	3		T93	11		T27	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T5	2		T6	1		T35	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	14		T46	1		T141	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T5	2		T13	1		T14	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T28	2		T202	12		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T1	1		T2	20		T3	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T135	4		T210	12		T252	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T123	13		T203	3		T248	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T135	5		T46	11		T127	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T150	12		T151	11		T253	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1207	1			T12	21		T34	10		T35	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	9		T34	9		T201	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	21		T122	4		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T10	14		T139	13		T143	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	7		T150	14		T152	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T35	3		T154	10		T240	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T208	2		T81	1		T238	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T34	5		T16	14		T123	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	4		T195	9		T140	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T138	6		T195	11		T154	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	4		T142	7		T211	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	3		T27	3		T85	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T5	2		T35	2		T38	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T46	4		T37	4		T77	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T13	8		T14	1		T15	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T28	1		T202	10		T139	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

auto[0]

4215

1

T5

5

T6

4

T7

13