Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26972

1

T1

16

T2

20

T3

169

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23236

1

T1

15

T2

20

T3

169

auto[ADC_CTRL_FILTER_COND_OUT]

3736

1

T1

1

T5

6

T6

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20552

1

T1

15

T2

20

T3

169

auto[1]

6420

1

T1

1

T5

6

T6

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22708

1

T1

2

T2

20

T3

169

auto[1]

4264

1

T1

14

T5

7

T6

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	172	1			T34	6		T138	7		T136	7
values[1]	778	1			T5	2		T15	9		T135	13
values[2]	624	1			T8	16		T28	3		T143	28
values[3]	702	1			T7	23		T93	4		T195	27
values[4]	962	1			T6	1		T7	11		T93	14
values[5]	699	1			T1	1		T13	9		T23	3
values[6]	700	1			T5	6		T6	12		T34	10
values[7]	790	1			T6	17		T35	16		T195	22
values[8]	2888	1			T1	14		T5	4		T8	44
values[9]	1129	1			T10	29		T15	19		T46	5
minimum	17528	1			T1	1		T2	20		T3	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	759	1			T5	2		T15	9		T135	13
values[1]	545	1			T7	23		T8	16		T28	3
values[2]	878	1			T7	11		T93	4		T14	4
values[3]	760	1			T6	1		T93	14		T35	12
values[4]	727	1			T1	1		T5	6		T13	9
values[5]	701	1			T6	12		T34	10		T35	16
values[6]	3079	1			T6	17		T8	44		T9	12
values[7]	663	1			T1	14		T5	4		T35	13
values[8]	910	1			T10	29		T34	6		T15	19
values[9]	160	1			T196	1		T197	3		T206	12
minimum	17790	1			T1	1		T2	20		T3	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

4215

1

T5

5

T6

4

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	2		T135	13		T198	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T15	4		T199	1		T78	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T7	10		T8	8		T200	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T28	2		T143	14		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T7	5		T195	23		T46	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T93	1		T14	3		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	1		T93	2		T140	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T35	3		T142	1		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T23	1		T121	1		T135	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T1	1		T5	4		T13	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T35	10		T201	6		T202	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	1		T34	10		T27	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1606	1			T6	5		T9	1		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T8	22		T123	12		T143	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	1		T5	4		T35	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T16	19		T139	14		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T34	6		T138	7		T122	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	15		T15	7		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T196	1		T197	1		T215	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T206	1		T254	12		T255	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17458	1			T2	20		T3	169		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T124	1		T125	17		T209	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T124	2		T208	15		T221	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T15	5		T210	7		T182	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T7	13		T8	8		T210	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T28	1		T143	14		T29	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T7	6		T195	4		T123	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T93	3		T14	1		T140	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T93	12		T140	7		T38	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T35	9		T142	11		T211	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T23	2		T121	8		T46	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	2		T28	4		T136	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T35	6		T201	2		T202	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	11		T27	5		T195	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1105	1			T6	12		T9	11		T11	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T8	22		T123	11		T143	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	13		T35	9		T213	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T16	8		T151	12		T214	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T122	4		T37	3		T150	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	14		T15	12		T136	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T197	2		T215	11		T167	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T206	11		T256	13		T257	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	1		T5	5		T6	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T124	12		T209	7		T258	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T34	6		T138	7		T227	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T136	1		T154	17		T259	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	2		T135	13		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T15	4		T124	1		T125	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T8	8		T124	2		T125	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T28	2		T143	14		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T7	10		T195	23		T46	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T93	1		T140	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T6	1		T7	5		T93	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T35	3		T14	3		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T23	1		T121	1		T135	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	1		T13	9		T34	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T201	6		T202	11		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	4		T6	1		T34	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T6	5		T35	10		T150	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T195	12		T123	12		T142	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1546	1			T1	1		T5	4		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T8	22		T139	14		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T46	5		T122	5		T37	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T10	15		T15	7		T16	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17413	1			T2	20		T3	169		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T227	1		T260	3		T17	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T136	6		T204	2		T244	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T141	14		T208	4		T221	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T15	5		T124	12		T210	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T8	8		T124	2		T210	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T28	1		T143	14		T182	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	13		T195	4		T38	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T93	3		T140	1		T141	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T7	6		T93	12		T140	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T35	9		T14	1		T142	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T23	2		T121	8		T46	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T28	4		T136	14		T30	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T201	2		T202	11		T252	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	2		T6	11		T27	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	12		T35	6		T150	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T195	10		T123	11		T143	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1088	1			T1	13		T9	11		T11	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T8	22		T151	12		T214	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T122	4		T37	3		T213	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T10	14		T15	12		T16	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T5	5		T6	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T5	2		T135	1		T198	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T15	9		T199	1		T78	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	14		T8	9		T200	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T28	2		T143	15		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T7	7		T195	6		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T93	4		T14	3		T140	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	1		T93	14		T140	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T35	10		T142	12		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T23	3		T121	9		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	1		T5	3		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T35	7		T201	3		T202	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T6	12		T34	1		T27	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1447	1			T6	13		T9	12		T11	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	23		T123	12		T143	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	14		T5	2		T35	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T16	13		T139	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T34	1		T138	1		T122	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T10	15		T15	15		T136	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T196	1		T197	3		T215	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T206	12		T254	1		T255	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17590	1			T1	1		T2	20		T3	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T124	13		T125	1		T209	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T135	12		T124	1		T125	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T78	8		T210	7		T182	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T7	9		T8	7		T210	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T28	1		T143	13		T150	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T7	4		T195	21		T46	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T14	1		T205	10		T232	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T140	12		T38	3		T126	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T35	2		T211	9		T77	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T135	5		T46	9		T151	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	3		T13	8		T34	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T35	9		T201	5		T202	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T34	9		T27	3		T195	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T6	4		T12	21		T36	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T8	21		T123	11		T143	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T5	2		T35	3		T46	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T16	14		T139	13		T154	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T34	5		T138	6		T122	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	14		T15	4		T154	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T167	12		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T254	11		T256	12		T257	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T261	9		T220	14		T262	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T125	16		T263	10		T264	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T34	1		T138	1		T227	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T136	7		T154	1		T259	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	2		T135	1		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T15	9		T124	13		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T8	9		T124	3		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T28	2		T143	15		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T7	14		T195	6		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T93	4		T140	2		T141	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T6	1		T7	7		T93	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T35	10		T14	3		T142	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T23	3		T121	9		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	1		T13	1		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T201	3		T202	12		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	3		T6	12		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T6	13		T35	7		T150	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T195	11		T123	12		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1436	1			T1	14		T5	2		T9	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T8	23		T139	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T46	1		T122	5		T37	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T10	15		T15	15		T16	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T1	1		T2	20		T3	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T34	5		T138	6		T234	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T154	16		T244	1		T243	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T135	12		T208	5		T221	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T125	16		T210	7		T155	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T8	7		T124	1		T125	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T28	1		T143	13		T150	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	9		T195	21		T46	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T29	1		T242	12		T232	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	4		T140	12		T123	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T35	2		T14	1		T211	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T135	5		T46	9		T151	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	8		T34	10		T30	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T201	5		T202	10		T252	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T5	3		T34	9		T27	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T6	4		T35	9		T150	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T195	11		T123	11		T142	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1198	1			T5	2		T12	21		T35	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T8	21		T139	13		T151	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T46	4		T122	4		T37	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T10	14		T15	4		T16	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

auto[0]

4215

1

T5

5

T6

4

T7

13