Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26972

1

T1

16

T2

20

T3

169

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23189

1

T1

15

T2

20

T3

169

auto[ADC_CTRL_FILTER_COND_OUT]

3783

1

T1

1

T5

10

T13

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21040

1

T1

16

T2

20

T3

169

auto[1]

5932

1

T5

2

T6

18

T8

44

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22708

1

T1

2

T2

20

T3

169

auto[1]

4264

1

T1

14

T5

7

T6

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	21	1			T37	8		T38	13		-	-
values[0]	34	1			T250	1		T265	4		T266	1
values[1]	568	1			T1	1		T13	9		T34	11
values[2]	834	1			T5	6		T8	44		T34	6
values[3]	814	1			T7	23		T195	22		T201	8
values[4]	701	1			T6	12		T34	10		T135	13
values[5]	3076	1			T6	18		T9	12		T11	18
values[6]	646	1			T5	2		T35	12		T121	9
values[7]	730	1			T5	4		T138	7		T135	6
values[8]	652	1			T8	16		T23	3		T46	5
values[9]	1368	1			T1	14		T7	11		T10	29
minimum	17528	1			T1	1		T2	20		T3	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	754	1			T5	6		T13	9		T34	11
values[1]	774	1			T1	1		T8	44		T34	6
values[2]	896	1			T7	23		T195	22		T135	13
values[3]	3054	1			T6	30		T9	12		T11	18
values[4]	688	1			T93	4		T35	13		T28	3
values[5]	662	1			T5	6		T35	12		T121	9
values[6]	629	1			T138	7		T135	6		T137	1
values[7]	874	1			T8	16		T23	3		T46	5
values[8]	962	1			T7	11		T10	29		T93	3
values[9]	150	1			T1	14		T15	9		T122	9
minimum	17529	1			T1	1		T2	20		T3	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

4215

1

T5

5

T6

4

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T34	11		T35	10		T226	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	4		T13	9		T93	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	22		T34	6		T195	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T1	1		T14	3		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	10		T201	6		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T195	12		T135	13		T16	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1593	1			T6	7		T9	1		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T34	10		T202	11		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T139	14		T137	1		T38	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T93	1		T35	4		T28	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	2		T35	3		T46	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T5	4		T121	1		T46	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T138	7		T135	6		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T137	1		T122	1		T123	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T8	8		T23	1		T123	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T46	5		T124	11		T200	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T7	5		T10	15		T15	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T93	1		T195	10		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T1	1		T126	10		T196	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T15	4		T122	5		T267	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17413	1			T2	20		T3	169		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T193	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T35	6		T226	4		T39	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	2		T93	10		T27	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T8	22		T195	2		T28	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T14	1		T141	3		T124	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	13		T201	2		T136	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T195	10		T16	8		T77	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1111	1			T6	23		T9	11		T11	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T202	11		T213	10		T88	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T38	3		T77	12		T144	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T93	3		T35	9		T28	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T35	9		T151	10		T224	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T121	8		T46	10		T123	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T140	1		T142	11		T226	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T123	17		T126	11		T32	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T8	8		T23	2		T123	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T124	11		T203	3		T24	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T7	6		T10	14		T15	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T93	2		T195	2		T141	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T1	13		T227	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T15	5		T122	4		T267	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T5	5		T6	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T37	5		T38	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T266	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T250	1		T265	1		T193	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T34	11		T35	10		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	1		T13	9		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T8	22		T34	6		T195	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T5	4		T14	3		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T7	10		T201	6		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T195	12		T16	19		T124	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	1		T136	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T34	10		T135	13		T202	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1579	1			T6	6		T9	1		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T93	1		T35	4		T28	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T35	3		T46	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T121	1		T16	1		T123	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T138	7		T135	6		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T5	4		T46	10		T123	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T8	8		T23	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T46	5		T137	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	379	1			T1	1		T7	5		T10	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T93	1		T15	4		T195	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17413	1			T2	20		T3	169		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T37	3		T38	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T265	3		T268	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T35	6		T226	4		T227	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T93	10		T27	5		T141	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	22		T195	2		T28	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	2		T14	1		T124	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	13		T201	2		T136	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T195	10		T16	8		T124	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	11		T136	14		T143	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T202	11		T213	10		T221	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1099	1			T6	12		T9	11		T11	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T93	3		T35	9		T28	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T35	9		T77	12		T81	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T121	8		T123	9		T143	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T142	11		T226	17		T151	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T46	10		T123	17		T150	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	8		T23	2		T140	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T203	3		T24	2		T32	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T1	13		T7	6		T10	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T93	2		T15	5		T195	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T5	5		T6	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T34	1		T35	7		T226	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	3		T13	1		T93	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	23		T34	1		T195	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T1	1		T14	3		T141	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T7	14		T201	3		T136	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T195	11		T135	1		T16	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1460	1			T6	26		T9	12		T11	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T34	1		T202	12		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T139	1		T137	1		T38	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T93	4		T35	10		T28	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	2		T35	10		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	2		T121	9		T46	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T138	1		T135	1		T140	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T137	1		T122	1		T123	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T8	9		T23	3		T123	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T46	1		T124	12		T200	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T7	7		T10	15		T15	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T93	3		T195	3		T141	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T1	14		T126	1		T196	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T15	9		T122	5		T267	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T1	1		T2	20		T3	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T193	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T34	10		T35	9		T150	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	3		T13	8		T27	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	21		T34	5		T195	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	1		T124	1		T127	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	9		T201	5		T142	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T195	11		T135	12		T16	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T6	4		T12	21		T36	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T34	9		T202	10		T234	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T139	13		T38	3		T125	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T35	3		T28	1		T143	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T35	2		T46	11		T149	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	2		T46	9		T123	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T138	6		T135	5		T182	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T123	13		T126	11		T78	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T8	7		T123	11		T211	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T46	4		T124	10		T203	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	4		T10	14		T15	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T195	9		T37	4		T30	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T126	9		T263	11		T269	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T122	4		T173	11		T270	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T37	4		T38	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T266	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T250	1		T265	4		T193	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T34	1		T35	7		T226	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	1		T13	1		T93	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T8	23		T34	1		T195	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	3		T14	3		T124	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	14		T201	3		T136	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T195	11		T16	13		T124	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T6	12		T136	15		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T34	1		T135	1		T202	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1446	1			T6	14		T9	12		T11	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T93	4		T35	10		T28	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	2		T35	10		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T121	9		T16	1		T123	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T138	1		T135	1		T142	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	2		T46	11		T123	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T8	9		T23	3		T140	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T46	1		T137	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	382	1			T1	14		T7	7		T10	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	403	1			T93	3		T15	9		T195	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T1	1		T2	20		T3	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T37	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T268	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T34	10		T35	9		T150	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T13	8		T27	3		T139	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T8	21		T34	5		T195	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T5	3		T14	1		T127	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T7	9		T201	5		T142	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T195	11		T16	14		T124	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T143	13		T245	11		T253	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T34	9		T135	12		T202	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T6	4		T12	21		T36	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T35	3		T28	1		T78	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T35	2		T46	11		T149	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T123	11		T143	13		T154	31
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T138	6		T135	5		T151	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	2		T46	9		T123	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T8	7		T123	11		T125	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T46	4		T203	3		T24	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T7	4		T10	14		T15	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T195	9		T122	4		T124	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

auto[0]

4215

1

T5

5

T6

4

T7

13