Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26972

1

T1

16

T2

20

T3

169

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23285

1

T1

2

T2

20

T3

169

auto[ADC_CTRL_FILTER_COND_OUT]

3687

1

T1

14

T5

6

T7

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20868

1

T1

1

T2

20

T3

169

auto[1]

6104

1

T1

15

T5

6

T6

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22708

1

T1

2

T2

20

T3

169

auto[1]

4264

1

T1

14

T5

7

T6

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	88	1			T149	17		T126	23		T271	12
values[0]	22	1			T127	14		T268	8		-	-
values[1]	574	1			T34	11		T121	9		T135	6
values[2]	3000	1			T7	23		T9	12		T11	18
values[3]	768	1			T8	44		T10	29		T93	4
values[4]	758	1			T8	16		T35	13		T198	1
values[5]	659	1			T34	6		T15	9		T136	12
values[6]	719	1			T1	1		T6	17		T138	7
values[7]	732	1			T5	6		T6	12		T7	11
values[8]	790	1			T1	14		T5	4		T6	1
values[9]	1334	1			T5	2		T13	9		T23	3
minimum	17528	1			T1	1		T2	20		T3	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	743	1			T7	23		T93	3		T121	9
values[1]	3108	1			T9	12		T11	18		T12	23
values[2]	761	1			T8	60		T10	29		T137	1
values[3]	697	1			T34	6		T35	13		T15	9
values[4]	696	1			T195	34		T136	12		T16	27
values[5]	590	1			T1	1		T5	6		T6	17
values[6]	834	1			T1	14		T6	12		T93	11
values[7]	829	1			T5	6		T6	1		T14	4
values[8]	944	1			T23	3		T195	15		T135	18
values[9]	241	1			T13	9		T15	19		T188	1
minimum	17529	1			T1	1		T2	20		T3	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

4215

1

T5

5

T6

4

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T46	22		T127	10		T78	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	10		T93	1		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1568	1			T9	1		T11	2		T12	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T34	10		T93	1		T201	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	30		T143	14		T226	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T10	15		T137	1		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T15	4		T198	1		T150	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T34	6		T35	4		T154	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T195	10		T160	1		T208	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T195	12		T136	1		T16	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T1	1		T6	5		T7	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	4		T27	8		T138	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T6	1		T35	3		T46	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	1		T93	1		T136	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T5	6		T6	1		T14	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T202	11		T42	1		T149	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T23	1		T195	13		T135	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T28	2		T139	14		T123	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T13	9		T15	7		T188	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T272	1		T155	1		T273	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17414	1			T2	20		T3	169		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T46	10		T127	4		T151	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	13		T93	2		T121	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1095	1			T9	11		T11	16		T148	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T93	3		T201	2		T124	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T8	30		T143	14		T226	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	14		T142	11		T143	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T15	5		T26	6		T209	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T35	9		T203	17		T213	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T195	2		T208	2		T81	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T195	10		T136	11		T16	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T6	12		T7	6		T140	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	2		T27	5		T141	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T6	11		T35	9		T38	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	13		T93	10		T136	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T14	1		T124	11		T38	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T202	11		T77	12		T151	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T23	2		T195	2		T28	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T28	1		T123	17		T226	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T15	12		T75	9		T210	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T273	15		T246	19		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T5	5		T6	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T271	1		T274	12		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T149	17		T126	12		T275	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T127	10		T268	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T34	11		T135	6		T46	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T121	1		T140	1		T150	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1554	1			T9	1		T11	2		T12	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	10		T34	10		T93	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T8	22		T137	1		T122	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T10	15		T93	1		T139	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T8	8		T198	1		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T35	4		T137	1		T203	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T15	4		T208	3		T81	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T34	6		T136	1		T16	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	1		T6	5		T195	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T138	7		T195	12		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	1		T7	5		T200	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T5	4		T93	1		T27	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	4		T6	1		T35	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T1	1		T141	1		T37	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	392	1			T5	2		T13	9		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T28	2		T202	11		T139	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17413	1			T2	20		T3	169		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T271	11		T274	12		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T126	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T127	4		T268	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T151	10		T214	10		T208	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T121	8		T140	1		T150	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1069	1			T9	11		T11	16		T148	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	13		T93	2		T201	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T8	22		T122	4		T143	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T10	14		T93	3		T142	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T8	8		T226	2		T227	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T35	9		T203	17		T213	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T15	5		T208	2		T81	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T136	11		T16	8		T123	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T6	12		T195	2		T140	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T195	10		T141	3		T236	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	11		T7	6		T211	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	2		T93	10		T27	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T35	9		T38	3		T126	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	13		T141	14		T37	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T23	2		T14	1		T15	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T28	1		T202	11		T123	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T5	5		T6	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T46	12		T127	5		T78	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T7	14		T93	3		T121	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T9	12		T11	18		T12	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T34	1		T93	4		T201	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T8	32		T143	15		T226	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T10	15		T137	1		T142	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T15	9		T198	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T34	1		T35	10		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T195	3		T160	1		T208	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T195	11		T136	12		T16	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T1	1		T6	13		T7	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	3		T27	10		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T6	12		T35	10		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T1	14		T93	11		T136	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T5	4		T6	1		T14	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T202	12		T42	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T23	3		T195	3		T135	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T28	2		T139	1		T123	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T13	1		T15	15		T188	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T272	1		T155	1		T273	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17529	1			T1	1		T2	20		T3	169
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T46	20		T127	9		T78	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	9		T150	12		T151	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T12	21		T34	10		T35	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T34	9		T201	5		T139	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T8	28		T143	13		T249	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T10	14		T143	13		T125	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T150	14		T152	9		T26	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T34	5		T35	3		T154	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T195	9		T208	2		T81	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T195	11		T16	14		T123	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T6	4		T7	4		T140	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	3		T27	3		T138	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T35	2		T46	4		T142	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T37	4		T155	3		T85	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	2		T14	1		T124	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T202	10		T149	11		T77	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T195	12		T135	16		T29	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T28	1		T139	13		T123	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	8		T15	4		T75	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T273	15		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T271	12		T274	13		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T149	1		T126	12		T275	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T127	5		T268	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T34	1		T135	1		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T121	9		T140	2		T150	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1409	1			T9	12		T11	18		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T7	14		T34	1		T93	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T8	23		T137	1		T122	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T10	15		T93	4		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T8	9		T198	1		T226	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T35	10		T137	1		T203	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T15	9		T208	3		T81	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T34	1		T136	12		T16	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T1	1		T6	13		T195	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T138	1		T195	11		T141	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	12		T7	7		T200	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T5	3		T93	11		T27	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T5	2		T6	1		T35	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	14		T141	15		T37	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	387	1			T5	2		T13	1		T23	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T28	2		T202	12		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T1	1		T2	20		T3	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T274	11		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T149	16		T126	11		T275	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T127	9		T268	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T34	10		T135	5		T46	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T150	12		T151	11		T253	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T12	21		T35	9		T36	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	9		T34	9		T201	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	21		T122	4		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	14		T139	13		T143	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T8	7		T150	14		T152	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T35	3		T203	14		T240	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T208	2		T81	1		T238	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T34	5		T16	14		T123	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T6	4		T195	9		T140	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T138	6		T195	11		T154	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	4		T211	9		T149	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	3		T27	3		T221	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	2		T35	2		T46	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T37	4		T77	9		T151	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T13	8		T14	1		T15	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T28	1		T202	10		T139	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

auto[0]

4215

1

T5

5

T6

4

T7

13