Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26972

1

T1

16

T2

20

T3

169

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23259

1

T1

2

T2

20

T3

169

auto[ADC_CTRL_FILTER_COND_OUT]

3713

1

T1

14

T5

6

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20854

1

T1

15

T2

20

T3

167

auto[1]

6118

1

T1

1

T3

2

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22708

1

T1

2

T2

20

T3

169

auto[1]

4264

1

T1

14

T5

7

T6

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	405	1			T3	2		T8	1		T27	16
values[0]	64	1			T197	15		T221	11		T263	12
values[1]	562	1			T1	14		T6	13		T15	19
values[2]	3180	1			T9	12		T11	18		T12	23
values[3]	777	1			T14	4		T46	12		T124	4
values[4]	718	1			T1	1		T5	4		T8	44
values[5]	774	1			T13	9		T93	3		T15	9
values[6]	511	1			T5	2		T8	16		T35	13
values[7]	677	1			T7	11		T34	10		T93	4
values[8]	712	1			T5	6		T6	17		T93	11
values[9]	1465	1			T7	23		T34	6		T195	12
minimum	17127	1			T1	1		T2	20		T3	167

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	846	1			T1	14		T6	13		T35	16
values[1]	3109	1			T9	12		T11	18		T12	23
values[2]	717	1			T5	4		T14	4		T46	12
values[3]	703	1			T1	1		T10	29		T93	3
values[4]	871	1			T8	44		T13	9		T15	9
values[5]	594	1			T5	2		T7	11		T8	16
values[6]	670	1			T34	10		T93	4		T35	13
values[7]	769	1			T5	6		T6	17		T7	23
values[8]	950	1			T34	6		T198	1		T201	8
values[9]	213	1			T195	12		T203	32		T80	1
minimum	17530	1			T1	1		T2	20		T3	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

4215

1

T5

5

T6

4

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T6	1		T15	7		T135	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	1		T6	1		T35	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1623	1			T9	1		T11	2		T12	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T23	1		T34	11		T35	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	4		T14	3		T200	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T46	12		T16	1		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	1		T93	1		T46	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T10	15		T138	7		T139	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T15	4		T124	11		T236	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T8	22		T13	9		T135	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	2		T7	5		T27	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T8	8		T135	5		T28	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T35	4		T121	1		T142	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T34	10		T93	1		T46	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T6	5		T93	1		T139	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T5	4		T7	10		T211	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T122	5		T141	1		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T34	6		T198	1		T201	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T203	15		T209	1		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T195	10		T80	1		T144	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17414	1			T2	20		T3	169		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T196	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T6	11		T15	12		T140	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	13		T35	6		T28	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1056	1			T9	11		T11	16		T148	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T23	2		T35	9		T195	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T14	1		T226	17		T182	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T203	3		T75	9		T214	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T93	2		T123	11		T143	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T10	14		T140	7		T38	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	5		T124	11		T236	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T8	22		T143	18		T151	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T7	6		T27	5		T195	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T8	8		T28	1		T123	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T35	9		T121	8		T208	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T93	3		T46	10		T141	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T6	12		T93	10		T39	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	2		T7	13		T211	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T122	4		T141	3		T124	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T201	2		T202	11		T126	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T203	17		T209	7		T231	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T195	2		T144	9		T276	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T5	5		T6	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	403	1			T3	2		T8	1		T27	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T30	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T197	3		T185	4		T167	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T221	6		T263	12		T173	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T6	1		T15	7		T135	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T1	1		T6	1		T28	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1586	1			T9	1		T11	2		T12	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T23	1		T34	11		T35	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T14	3		T200	1		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T46	12		T124	2		T30	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	1		T5	4		T46	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T8	22		T10	15		T138	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T93	1		T15	4		T124	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T13	9		T135	13		T140	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T5	2		T35	4		T195	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T8	8		T135	5		T28	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	5		T27	8		T142	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T34	10		T93	1		T123	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T6	5		T93	1		T121	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	4		T46	10		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	414	1			T139	14		T137	1		T122	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	423	1			T7	10		T34	6		T195	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17012	1			T2	20		T3	167		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T218	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T197	12		T185	1		T167	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T221	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T6	11		T15	12		T140	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T1	13		T28	4		T136	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1068	1			T9	11		T11	16		T148	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T23	2		T35	15		T195	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	1		T226	17		T216	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T124	2		T30	1		T197	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T123	11		T143	14		T226	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T8	22		T10	14		T38	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T93	2		T15	5		T124	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T140	7		T143	18		T151	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T35	9		T195	10		T33	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T8	8		T28	1		T77	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	6		T27	5		T208	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T93	3		T123	9		T142	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T6	12		T93	10		T121	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	2		T46	10		T141	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T122	4		T141	3		T124	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T7	13		T195	2		T201	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T5	5		T6	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T6	12		T15	15		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	14		T6	1		T35	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1401	1			T9	12		T11	18		T12	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T23	3		T34	1		T35	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	2		T14	3		T200	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T46	1		T16	1		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	1		T93	3		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T10	15		T138	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T15	9		T124	12		T236	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T8	23		T13	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	2		T7	7		T27	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	9		T135	1		T28	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T35	10		T121	9		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T34	1		T93	4		T46	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T6	13		T93	11		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	3		T7	14		T211	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T122	5		T141	4		T124	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T34	1		T198	1		T201	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T203	18		T209	8		T231	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T195	3		T80	1		T144	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17529	1			T1	1		T2	20		T3	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T196	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T15	4		T135	5		T125	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T35	9		T16	14		T123	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T12	21		T36	12		T134	27
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T34	10		T35	2		T195	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	2		T14	1		T182	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T46	11		T203	3		T75	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T46	4		T123	11		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	14		T138	6		T139	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T124	10		T236	2		T217	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T8	21		T13	8		T135	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T7	4		T27	3		T195	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T8	7		T135	4		T28	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T35	3		T142	7		T150	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T34	9		T46	9		T149	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	4		T139	13		T78	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T5	3		T7	9		T211	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T122	4		T154	15		T126	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T34	5		T201	5		T202	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T203	14		T184	3		T157	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T195	9		T269	8		T277	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	403	1			T3	2		T8	1		T27	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T30	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T197	13		T185	4		T167	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T221	6		T263	1		T173	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	12		T15	15		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T1	14		T6	1		T28	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1409	1			T9	12		T11	18		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T23	3		T34	1		T35	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T14	3		T200	1		T226	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T46	1		T124	3		T30	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	1		T5	2		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	23		T10	15		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T93	3		T15	9		T124	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T13	1		T135	1		T140	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	2		T35	10		T195	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T8	9		T135	1		T28	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T7	7		T27	10		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T34	1		T93	4		T123	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T6	13		T93	11		T121	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	3		T46	11		T141	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T139	1		T137	1		T122	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	442	1			T7	14		T34	1		T195	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17127	1			T1	1		T2	20		T3	167
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T218	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T197	2		T185	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T221	5		T263	11		T173	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T15	4		T135	5		T125	27
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T123	13		T150	12		T29	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1245	1			T12	21		T36	12		T134	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T34	10		T35	11		T195	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	1		T154	16		T217	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T46	11		T124	1		T30	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	2		T46	4		T123	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	21		T10	14		T138	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T124	10		T37	4		T236	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T13	8		T135	12		T140	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T35	3		T195	11		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T8	7		T135	4		T28	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	4		T27	3		T142	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T34	9		T123	11		T38	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	4		T278	11		T205	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T5	3		T46	9		T211	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T139	13		T122	4		T154	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T7	9		T34	5		T195	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

auto[0]

4215

1

T5

5

T6

4

T7

13