Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26972

1

T1

16

T2

20

T3

169

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23208

1

T1

1

T2

20

T3

169

auto[ADC_CTRL_FILTER_COND_OUT]

3764

1

T1

15

T5

4

T6

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20609

1

T1

1

T2

20

T3

169

auto[1]

6363

1

T1

15

T5

2

T6

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22708

1

T1

2

T2

20

T3

169

auto[1]

4264

1

T1

14

T5

7

T6

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	11	1			T279	11		-	-		-	-
values[0]	71	1			T245	12		T204	4		T269	9
values[1]	674	1			T1	14		T5	2		T6	1
values[2]	605	1			T6	17		T195	37		T202	22
values[3]	813	1			T34	11		T35	16		T15	19
values[4]	3072	1			T7	23		T9	12		T11	18
values[5]	663	1			T5	6		T34	10		T35	13
values[6]	748	1			T5	4		T7	11		T10	29
values[7]	747	1			T1	1		T93	15		T35	12
values[8]	713	1			T6	12		T13	9		T23	3
values[9]	1327	1			T8	60		T138	7		T46	20
minimum	17528	1			T1	1		T2	20		T3	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	904	1			T1	14		T5	2		T6	1
values[1]	674	1			T6	17		T135	13		T16	27
values[2]	664	1			T7	23		T34	11		T35	16
values[3]	3120	1			T9	12		T11	18		T12	23
values[4]	720	1			T5	6		T7	11		T35	13
values[5]	718	1			T5	4		T10	29		T93	4
values[6]	792	1			T1	1		T93	11		T135	6
values[7]	591	1			T6	12		T23	3		T34	6
values[8]	902	1			T8	16		T13	9		T15	9
values[9]	326	1			T8	44		T138	7		T136	12
minimum	17561	1			T1	1		T2	20		T3	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

4215

1

T5

5

T6

4

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T5	2		T6	1		T195	25
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	1		T143	14		T199	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T16	19		T200	1		T39	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T6	5		T135	13		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	10		T35	10		T15	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T34	11		T198	1		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1631	1			T9	1		T11	2		T12	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T28	4		T124	1		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	4		T35	4		T27	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	5		T14	3		T46	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T93	1		T35	3		T135	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T5	4		T10	15		T201	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T136	1		T200	1		T150	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	1		T93	1		T135	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T34	6		T30	1		T280	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T6	1		T23	1		T93	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T15	4		T46	10		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T8	8		T13	9		T154	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T138	7		T154	11		T149	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T8	22		T136	1		T211	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17414	1			T2	20		T3	169		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T281	1		T231	1		T269	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T195	12		T202	11		T142	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	13		T143	18		T144	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T16	8		T39	3		T31	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	12		T141	3		T144	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T7	13		T35	6		T15	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T123	9		T226	4		T25	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1139	1			T9	11		T11	16		T148	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T28	4		T124	12		T203	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	2		T35	9		T27	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	6		T14	1		T208	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T93	3		T35	9		T150	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T10	14		T201	2		T122	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T136	6		T126	11		T127	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T93	10		T123	17		T38	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T216	2		T212	10		T237	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T6	11		T23	2		T93	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	5		T46	10		T197	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	8		T213	10		T150	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T273	15		T282	2		T21	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T8	22		T136	11		T211	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T1	1		T5	5		T6	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T231	7		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T279	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T245	12		T283	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T204	1		T269	9		T277	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	2		T6	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T1	1		T143	14		T125	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T195	25		T202	11		T200	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T6	5		T141	1		T199	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T35	10		T15	7		T16	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T34	11		T135	13		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1600	1			T7	10		T9	1		T11	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T46	12		T28	4		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	4		T34	10		T35	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T14	3		T139	14		T203	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T214	1		T186	1		T250	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T5	4		T7	5		T10	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T93	1		T35	3		T135	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	1		T93	1		T46	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T34	6		T15	4		T200	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T6	1		T13	9		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T138	7		T46	10		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	463	1			T8	30		T136	1		T200	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17413	1			T2	20		T3	169		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T279	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T283	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T204	3		T277	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T141	14		T142	11		T39	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	13		T143	18		T144	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T195	12		T202	11		T127	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T6	12		T141	3		T144	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T35	6		T15	12		T16	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T123	9		T226	4		T151	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1115	1			T7	13		T9	11		T11	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T28	4		T124	12		T126	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	2		T35	9		T121	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T14	1		T203	17		T24	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T214	10		T186	9		T204	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T7	6		T10	14		T38	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T93	3		T35	9		T136	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T93	10		T201	2		T122	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T15	5		T126	11		T216	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	11		T23	2		T93	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T46	10		T197	2		T227	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T8	30		T136	11		T211	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T5	5		T6	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T5	2		T6	1		T195	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T1	14		T143	19		T199	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T16	13		T200	1		T39	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	13		T135	1		T141	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	14		T35	7		T15	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T34	1		T198	1		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1483	1			T9	12		T11	18		T12	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T28	8		T124	13		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	3		T35	10		T27	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	7		T14	3		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T93	4		T35	10		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	2		T10	15		T201	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T136	7		T200	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	1		T93	11		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T34	1		T30	1		T280	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T6	12		T23	3		T93	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T15	9		T46	11		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T8	9		T13	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T138	1		T154	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T8	23		T136	12		T211	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17543	1			T1	1		T2	20		T3	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T281	1		T231	8		T269	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T195	23		T202	10		T78	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T143	13		T125	16		T85	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T16	14		T39	6		T31	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T6	4		T135	12		T151	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T7	9		T35	9		T15	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T34	10		T123	11		T25	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T12	21		T34	9		T36	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T203	14		T126	15		T24	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	3		T35	3		T27	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	4		T14	1		T46	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T35	2		T135	4		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T5	2		T10	14		T201	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T150	14		T126	11		T127	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T135	5		T46	4		T123	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	5		T242	12		T237	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T28	1		T124	10		T77	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T46	9		T125	11		T284	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T8	7		T13	8		T154	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T138	6		T154	10		T149	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T8	21		T211	9		T208	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T269	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T279	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T245	1		T283	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T204	4		T269	1		T277	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	2		T6	1		T141	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	14		T143	19		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T195	14		T202	12		T200	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	13		T141	4		T199	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T35	7		T15	15		T16	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T34	1		T135	1		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1456	1			T7	14		T9	12		T11	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T46	1		T28	8		T124	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T5	3		T34	1		T35	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T14	3		T139	1		T203	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T214	11		T186	10		T250	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T5	2		T7	7		T10	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T93	4		T35	10		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	1		T93	11		T46	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T34	1		T15	9		T200	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T6	12		T13	1		T23	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T138	1		T46	11		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T8	32		T136	12		T200	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T1	1		T2	20		T3	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T279	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T245	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T269	8		T277	7		T285	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T78	15		T39	6		T240	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T143	13		T125	16		T85	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T195	23		T202	10		T31	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T6	4		T210	7		T252	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T35	9		T15	4		T16	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T34	10		T135	12		T123	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T7	9		T12	21		T36	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T46	11		T126	15		T217	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	3		T34	9		T35	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T14	1		T139	13		T203	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T286	13		T273	23		T287	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T5	2		T7	4		T10	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T35	2		T135	4		T150	26
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T46	4		T201	5		T122	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T34	5		T126	11		T249	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	8		T135	5		T28	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T138	6		T46	9		T154	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	396	1			T8	28		T211	9		T154	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

auto[0]

4215

1

T5

5

T6

4

T7

13