Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26972

1

T1

16

T2

20

T3

169

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23164

1

T1

2

T2

20

T3

169

auto[ADC_CTRL_FILTER_COND_OUT]

3808

1

T1

14

T5

10

T7

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20811

1

T1

1

T2

20

T3

167

auto[1]

6161

1

T1

15

T3

2

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22708

1

T1

2

T2

20

T3

169

auto[1]

4264

1

T1

14

T5

7

T6

26

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	742	1			T3	2		T8	1		T27	16
values[0]	38	1			T197	15		T221	11		T288	12
values[1]	573	1			T1	14		T6	13		T35	16
values[2]	3222	1			T9	12		T11	18		T12	23
values[3]	734	1			T14	4		T46	12		T124	4
values[4]	690	1			T1	1		T5	4		T10	29
values[5]	833	1			T8	44		T13	9		T93	3
values[6]	482	1			T5	2		T8	16		T27	13
values[7]	663	1			T7	11		T34	10		T93	4
values[8]	722	1			T5	6		T93	11		T121	9
values[9]	1146	1			T6	17		T7	23		T34	6
minimum	17127	1			T1	1		T2	20		T3	167

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	650	1			T6	1		T35	16		T15	19
values[1]	3098	1			T9	12		T11	18		T12	23
values[2]	731	1			T5	4		T14	4		T46	12
values[3]	709	1			T1	1		T10	29		T93	3
values[4]	843	1			T8	44		T13	9		T15	9
values[5]	640	1			T5	2		T7	11		T8	16
values[6]	626	1			T34	10		T35	13		T121	9
values[7]	819	1			T5	6		T6	17		T7	23
values[8]	1015	1			T34	6		T198	1		T201	8
values[9]	141	1			T195	12		T203	32		T144	10
minimum	17700	1			T1	15		T2	20		T3	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

4215

1

T5

5

T6

4

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	1		T15	7		T135	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T35	10		T28	4		T200	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1563	1			T9	1		T11	2		T12	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T23	1		T34	11		T35	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T14	3		T46	12		T226	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	4		T16	1		T200	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	1		T93	1		T46	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T10	15		T138	7		T139	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T15	4		T236	3		T196	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T8	22		T13	9		T135	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	2		T7	5		T27	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	8		T195	12		T135	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T35	4		T25	1		T152	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T34	10		T121	1		T46	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T6	5		T93	1		T139	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	4		T7	10		T93	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T122	5		T124	1		T154	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T34	6		T198	1		T201	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T203	15		T172	1		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T195	10		T144	1		T209	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17460	1			T2	20		T3	169		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T1	1		T136	1		T196	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	12		T16	8		T140	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T35	6		T28	4		T150	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1063	1			T9	11		T11	16		T148	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T23	2		T35	9		T195	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T14	1		T226	17		T75	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T197	2		T210	12		T31	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T93	2		T123	11		T37	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	14		T140	7		T143	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T15	5		T236	2		T194	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T8	22		T143	18		T124	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	6		T27	5		T123	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T8	8		T195	10		T28	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T35	9		T223	10		T88	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T121	8		T46	10		T141	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T6	12		T93	10		T211	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	2		T7	13		T93	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T122	4		T124	12		T126	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T201	2		T202	11		T141	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T203	17		T231	7		T184	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T195	2		T144	9		T209	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	1		T5	5		T6	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T1	13		T136	6		T197	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	487	1			T3	2		T8	1		T27	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T195	10		T201	6		T30	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T197	3		T221	6		T288	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	2		T15	7		T135	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	1		T35	10		T28	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1559	1			T9	1		T11	2		T12	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T23	1		T34	11		T35	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T14	3		T46	12		T124	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T200	1		T197	1		T210	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T1	1		T46	5		T123	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	4		T10	15		T138	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T93	1		T15	4		T37	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T8	22		T13	9		T135	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T5	2		T27	8		T77	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T8	8		T195	12		T28	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T7	5		T35	4		T123	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T34	10		T93	1		T135	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T93	1		T211	10		T78	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	4		T121	1		T46	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T6	5		T139	14		T122	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T7	10		T34	6		T198	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17012	1			T2	20		T3	167		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T77	12		T184	3		T252	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T195	2		T201	2		T227	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T197	12		T221	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T6	11		T15	12		T140	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	13		T35	6		T28	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1091	1			T9	11		T11	16		T148	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T23	2		T35	9		T195	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	1		T124	2		T226	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T197	2		T210	12		T216	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T123	11		T214	10		T194	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	14		T143	14		T38	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T93	2		T15	5		T37	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T8	22		T140	7		T143	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T27	5		T77	5		T25	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T8	8		T195	10		T28	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	6		T35	9		T123	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T93	3		T142	11		T208	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T93	10		T211	10		T227	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	2		T121	8		T46	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T6	12		T122	4		T124	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T7	13		T202	11		T141	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T5	5		T6	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	1		T15	15		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T35	7		T28	8		T200	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T9	12		T11	18		T12	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T23	3		T34	1		T35	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T14	3		T46	1		T226	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	2		T16	1		T200	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	1		T93	3		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T10	15		T138	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T15	9		T236	3		T196	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T8	23		T13	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	2		T7	7		T27	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T8	9		T195	11		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T35	10		T25	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T34	1		T121	9		T46	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T6	13		T93	11		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T5	3		T7	14		T93	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T122	5		T124	13		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T34	1		T198	1		T201	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T203	18		T172	1		T231	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T195	3		T144	10		T209	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17554	1			T1	1		T2	20		T3	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T1	14		T136	7		T196	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	4		T135	5		T16	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T35	9		T150	12		T29	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T12	21		T36	12		T134	27
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T34	10		T35	2		T195	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	1		T46	11		T154	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	2		T210	12		T31	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T46	4		T123	11		T37	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	14		T138	6		T139	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T236	2		T217	13		T152	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T8	21		T13	8		T135	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	4		T27	3		T123	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T8	7		T195	11		T135	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T35	3		T152	3		T155	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T34	9		T46	9		T149	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	4		T139	13		T211	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T5	3		T7	9		T149	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T122	4		T154	15		T126	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T34	5		T201	5		T202	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T203	14		T184	3		T269	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T195	9		T20	5		T277	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T289	11		T269	14		T185	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T197	2		T208	5		T81	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	490	1			T3	2		T8	1		T27	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T195	3		T201	3		T30	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T197	13		T221	6		T288	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T6	13		T15	15		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	14		T35	7		T28	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1429	1			T9	12		T11	18		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T23	3		T34	1		T35	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T14	3		T46	1		T124	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T200	1		T197	3		T210	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	1		T46	1		T123	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	2		T10	15		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T93	3		T15	9		T37	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T8	23		T13	1		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	2		T27	10		T77	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T8	9		T195	11		T28	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	7		T35	10		T123	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T34	1		T93	4		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T93	11		T211	11		T78	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T5	3		T121	9		T46	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T6	13		T139	1		T122	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T7	14		T34	1		T198	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17127	1			T1	1		T2	20		T3	167
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T77	9		T184	3		T252	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T195	9		T201	5		T269	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T197	2		T221	5		T288	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	4		T135	5		T123	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T35	9		T125	11		T150	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1221	1			T12	21		T36	12		T134	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T34	10		T35	2		T195	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T14	1		T46	11		T124	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T210	12		T31	2		T290	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T46	4		T123	11		T291	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	2		T10	14		T138	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T37	4		T236	2		T217	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T8	21		T13	8		T135	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T27	3		T77	3		T25	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T8	7		T195	11		T28	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	4		T35	3		T123	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T34	9		T135	4		T142	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T211	9		T78	7		T205	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T5	3		T46	9		T149	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T6	4		T139	13		T122	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T7	9		T34	5		T202	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22757

1

T1

16

T2

20

T3

169

auto[1]

auto[0]

4215

1

T5

5

T6

4

T7

13