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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.69 99.07 96.67 100.00 100.00 98.83 98.33 90.92


Total test records in report: 920
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T799 /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3549508806 May 30 03:23:57 PM PDT 24 May 30 03:25:12 PM PDT 24 68752792804 ps
T800 /workspace/coverage/default/28.adc_ctrl_filters_interrupt.4189043900 May 30 03:20:32 PM PDT 24 May 30 03:24:00 PM PDT 24 164431579736 ps
T313 /workspace/coverage/default/14.adc_ctrl_filters_both.1332005756 May 30 03:16:27 PM PDT 24 May 30 03:20:21 PM PDT 24 570046656084 ps
T801 /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3642789674 May 30 03:15:40 PM PDT 24 May 30 03:21:25 PM PDT 24 158842518542 ps
T802 /workspace/coverage/default/27.adc_ctrl_smoke.1220392989 May 30 03:20:07 PM PDT 24 May 30 03:20:24 PM PDT 24 5590576706 ps
T47 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2014280476 May 30 03:12:20 PM PDT 24 May 30 03:12:28 PM PDT 24 8160993803 ps
T43 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2433311298 May 30 03:12:14 PM PDT 24 May 30 03:12:22 PM PDT 24 4924475822 ps
T803 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3438294895 May 30 03:13:08 PM PDT 24 May 30 03:13:13 PM PDT 24 406486444 ps
T94 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.267937981 May 30 03:12:27 PM PDT 24 May 30 03:12:30 PM PDT 24 482666578 ps
T114 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.392471174 May 30 03:12:27 PM PDT 24 May 30 03:12:30 PM PDT 24 427463017 ps
T804 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4201277461 May 30 03:13:09 PM PDT 24 May 30 03:13:12 PM PDT 24 345370307 ps
T44 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3242512147 May 30 03:11:27 PM PDT 24 May 30 03:11:30 PM PDT 24 2140637784 ps
T50 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1714543356 May 30 03:11:08 PM PDT 24 May 30 03:11:11 PM PDT 24 404326390 ps
T805 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2699728401 May 30 03:12:25 PM PDT 24 May 30 03:12:27 PM PDT 24 495568278 ps
T115 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1548952296 May 30 03:11:37 PM PDT 24 May 30 03:11:41 PM PDT 24 819964903 ps
T51 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2484569397 May 30 03:12:56 PM PDT 24 May 30 03:12:59 PM PDT 24 400566539 ps
T108 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3822655819 May 30 03:12:00 PM PDT 24 May 30 03:12:03 PM PDT 24 423985412 ps
T806 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.724518029 May 30 03:13:12 PM PDT 24 May 30 03:13:16 PM PDT 24 392516504 ps
T807 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3442110008 May 30 03:12:55 PM PDT 24 May 30 03:12:57 PM PDT 24 367822572 ps
T45 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3661007458 May 30 03:11:37 PM PDT 24 May 30 03:11:44 PM PDT 24 4290206375 ps
T48 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3960307949 May 30 03:11:10 PM PDT 24 May 30 03:11:23 PM PDT 24 4306941065 ps
T808 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3075384334 May 30 03:12:02 PM PDT 24 May 30 03:12:05 PM PDT 24 331817962 ps
T109 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.363704636 May 30 03:12:02 PM PDT 24 May 30 03:12:14 PM PDT 24 2044577406 ps
T55 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3025257919 May 30 03:12:40 PM PDT 24 May 30 03:12:45 PM PDT 24 795367897 ps
T49 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3715748930 May 30 03:12:20 PM PDT 24 May 30 03:12:26 PM PDT 24 4168617427 ps
T95 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1875826867 May 30 03:11:21 PM PDT 24 May 30 03:11:27 PM PDT 24 1020491579 ps
T809 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.4275478028 May 30 03:13:10 PM PDT 24 May 30 03:13:14 PM PDT 24 282205927 ps
T810 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.934489552 May 30 03:13:09 PM PDT 24 May 30 03:13:13 PM PDT 24 397876862 ps
T66 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.4258186345 May 30 03:12:41 PM PDT 24 May 30 03:12:54 PM PDT 24 9019365513 ps
T811 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1617549208 May 30 03:13:08 PM PDT 24 May 30 03:13:12 PM PDT 24 419664447 ps
T59 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3717101965 May 30 03:12:16 PM PDT 24 May 30 03:12:19 PM PDT 24 468796409 ps
T70 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1996353838 May 30 03:12:38 PM PDT 24 May 30 03:12:41 PM PDT 24 399274236 ps
T812 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3264493380 May 30 03:12:13 PM PDT 24 May 30 03:12:16 PM PDT 24 404236202 ps
T96 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2615494176 May 30 03:11:48 PM PDT 24 May 30 03:11:52 PM PDT 24 860163361 ps
T63 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1709671885 May 30 03:12:16 PM PDT 24 May 30 03:12:19 PM PDT 24 601773522 ps
T97 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2010240601 May 30 03:12:13 PM PDT 24 May 30 03:12:16 PM PDT 24 535589510 ps
T813 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2350929353 May 30 03:13:10 PM PDT 24 May 30 03:13:14 PM PDT 24 417061360 ps
T814 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2557138182 May 30 03:12:00 PM PDT 24 May 30 03:12:02 PM PDT 24 484644017 ps
T815 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.450463404 May 30 03:13:09 PM PDT 24 May 30 03:13:13 PM PDT 24 382800186 ps
T56 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4103539911 May 30 03:12:14 PM PDT 24 May 30 03:12:18 PM PDT 24 704030869 ps
T64 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.568335940 May 30 03:11:23 PM PDT 24 May 30 03:11:27 PM PDT 24 378061430 ps
T816 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1100895670 May 30 03:13:07 PM PDT 24 May 30 03:13:09 PM PDT 24 348754672 ps
T57 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1863275419 May 30 03:12:55 PM PDT 24 May 30 03:13:04 PM PDT 24 8315013461 ps
T110 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2601433697 May 30 03:12:03 PM PDT 24 May 30 03:12:07 PM PDT 24 3011193973 ps
T817 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1053675555 May 30 03:11:48 PM PDT 24 May 30 03:11:52 PM PDT 24 846885016 ps
T111 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.190471647 May 30 03:11:08 PM PDT 24 May 30 03:11:11 PM PDT 24 351994947 ps
T71 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.4237095605 May 30 03:11:50 PM PDT 24 May 30 03:11:56 PM PDT 24 4329728683 ps
T818 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2034775457 May 30 03:13:10 PM PDT 24 May 30 03:13:14 PM PDT 24 397761983 ps
T67 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.4061649175 May 30 03:12:27 PM PDT 24 May 30 03:12:30 PM PDT 24 437936111 ps
T819 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3267121053 May 30 03:13:09 PM PDT 24 May 30 03:13:13 PM PDT 24 449419375 ps
T820 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1958369353 May 30 03:13:11 PM PDT 24 May 30 03:13:14 PM PDT 24 359091476 ps
T821 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.720200342 May 30 03:12:13 PM PDT 24 May 30 03:12:15 PM PDT 24 338088319 ps
T112 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2237231976 May 30 03:12:25 PM PDT 24 May 30 03:12:31 PM PDT 24 3727008754 ps
T65 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1840652905 May 30 03:12:03 PM PDT 24 May 30 03:12:26 PM PDT 24 8157554857 ps
T68 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1242697186 May 30 03:12:02 PM PDT 24 May 30 03:12:08 PM PDT 24 8545487664 ps
T113 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1040755681 May 30 03:12:13 PM PDT 24 May 30 03:12:20 PM PDT 24 2270955937 ps
T98 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3974763465 May 30 03:11:22 PM PDT 24 May 30 03:12:38 PM PDT 24 47120606391 ps
T99 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3606847630 May 30 03:12:13 PM PDT 24 May 30 03:12:16 PM PDT 24 496328935 ps
T58 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2731745086 May 30 03:12:01 PM PDT 24 May 30 03:12:06 PM PDT 24 474004330 ps
T72 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2391278548 May 30 03:12:54 PM PDT 24 May 30 03:13:08 PM PDT 24 4272332855 ps
T822 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3282166483 May 30 03:11:22 PM PDT 24 May 30 03:11:25 PM PDT 24 481881388 ps
T823 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3605810288 May 30 03:12:01 PM PDT 24 May 30 03:12:19 PM PDT 24 4999959736 ps
T824 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2557783038 May 30 03:11:12 PM PDT 24 May 30 03:13:22 PM PDT 24 52420365041 ps
T825 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2527218599 May 30 03:11:10 PM PDT 24 May 30 03:11:12 PM PDT 24 1411273412 ps
T826 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2215269535 May 30 03:13:11 PM PDT 24 May 30 03:13:15 PM PDT 24 490890591 ps
T827 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3968642800 May 30 03:12:54 PM PDT 24 May 30 03:12:57 PM PDT 24 480851804 ps
T828 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3882130522 May 30 03:11:37 PM PDT 24 May 30 03:11:40 PM PDT 24 457803087 ps
T829 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2400319465 May 30 03:12:02 PM PDT 24 May 30 03:12:06 PM PDT 24 2097201611 ps
T830 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1494418601 May 30 03:12:02 PM PDT 24 May 30 03:12:06 PM PDT 24 446452175 ps
T69 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2159412143 May 30 03:12:40 PM PDT 24 May 30 03:12:45 PM PDT 24 967472448 ps
T831 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.4133976159 May 30 03:12:15 PM PDT 24 May 30 03:12:18 PM PDT 24 464064991 ps
T832 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3179215108 May 30 03:13:13 PM PDT 24 May 30 03:13:16 PM PDT 24 429736300 ps
T833 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.672461107 May 30 03:12:24 PM PDT 24 May 30 03:12:26 PM PDT 24 462694530 ps
T834 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2452082462 May 30 03:11:07 PM PDT 24 May 30 03:11:09 PM PDT 24 310682842 ps
T835 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.132738344 May 30 03:11:10 PM PDT 24 May 30 03:11:23 PM PDT 24 8350517040 ps
T836 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.916828656 May 30 03:11:12 PM PDT 24 May 30 03:11:18 PM PDT 24 2103175598 ps
T319 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3528270655 May 30 03:11:49 PM PDT 24 May 30 03:11:59 PM PDT 24 8849519250 ps
T837 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4262228049 May 30 03:12:27 PM PDT 24 May 30 03:12:31 PM PDT 24 573354017 ps
T838 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.233875277 May 30 03:12:40 PM PDT 24 May 30 03:12:53 PM PDT 24 8375607406 ps
T100 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3259138062 May 30 03:12:56 PM PDT 24 May 30 03:12:59 PM PDT 24 517173862 ps
T839 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2154073286 May 30 03:13:08 PM PDT 24 May 30 03:13:10 PM PDT 24 339158578 ps
T101 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1119188245 May 30 03:11:37 PM PDT 24 May 30 03:11:44 PM PDT 24 1291529717 ps
T840 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4035656657 May 30 03:11:37 PM PDT 24 May 30 03:11:39 PM PDT 24 557629594 ps
T841 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.17636705 May 30 03:11:37 PM PDT 24 May 30 03:11:45 PM PDT 24 2169419072 ps
T842 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3202694958 May 30 03:13:11 PM PDT 24 May 30 03:13:15 PM PDT 24 442329908 ps
T843 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3542795966 May 30 03:11:36 PM PDT 24 May 30 03:11:40 PM PDT 24 821586118 ps
T844 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3418463034 May 30 03:13:11 PM PDT 24 May 30 03:13:16 PM PDT 24 503580641 ps
T845 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3672408067 May 30 03:12:39 PM PDT 24 May 30 03:12:41 PM PDT 24 501786215 ps
T846 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1546103073 May 30 03:12:55 PM PDT 24 May 30 03:12:58 PM PDT 24 535895881 ps
T847 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3965001833 May 30 03:11:37 PM PDT 24 May 30 03:11:45 PM PDT 24 2226410620 ps
T102 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1426101022 May 30 03:12:16 PM PDT 24 May 30 03:12:18 PM PDT 24 498608643 ps
T848 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2161903615 May 30 03:12:39 PM PDT 24 May 30 03:12:42 PM PDT 24 527757440 ps
T849 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1937468298 May 30 03:12:20 PM PDT 24 May 30 03:12:22 PM PDT 24 559730091 ps
T850 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.559140305 May 30 03:12:39 PM PDT 24 May 30 03:12:43 PM PDT 24 432463266 ps
T851 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2053807213 May 30 03:12:16 PM PDT 24 May 30 03:12:41 PM PDT 24 5628984948 ps
T852 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3543863619 May 30 03:13:11 PM PDT 24 May 30 03:13:15 PM PDT 24 413586433 ps
T853 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.168353406 May 30 03:12:01 PM PDT 24 May 30 03:12:06 PM PDT 24 534744084 ps
T854 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3700610044 May 30 03:11:12 PM PDT 24 May 30 03:11:16 PM PDT 24 587047839 ps
T855 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1140534814 May 30 03:12:37 PM PDT 24 May 30 03:12:40 PM PDT 24 388086624 ps
T856 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.153308738 May 30 03:13:08 PM PDT 24 May 30 03:13:13 PM PDT 24 518331866 ps
T857 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3182596934 May 30 03:12:01 PM PDT 24 May 30 03:12:04 PM PDT 24 638722844 ps
T858 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2906955146 May 30 03:12:13 PM PDT 24 May 30 03:12:22 PM PDT 24 8584830999 ps
T859 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3161106879 May 30 03:12:56 PM PDT 24 May 30 03:13:02 PM PDT 24 4583393847 ps
T860 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2361612158 May 30 03:12:29 PM PDT 24 May 30 03:12:31 PM PDT 24 500560246 ps
T861 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.238390809 May 30 03:12:55 PM PDT 24 May 30 03:13:00 PM PDT 24 402575678 ps
T862 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.142664617 May 30 03:11:38 PM PDT 24 May 30 03:11:51 PM PDT 24 4449092906 ps
T863 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2174630919 May 30 03:11:37 PM PDT 24 May 30 03:12:41 PM PDT 24 53007140830 ps
T103 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.4237052858 May 30 03:11:22 PM PDT 24 May 30 03:11:26 PM PDT 24 865593364 ps
T107 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3086614305 May 30 03:11:22 PM PDT 24 May 30 03:11:25 PM PDT 24 585133230 ps
T104 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3004753552 May 30 03:11:38 PM PDT 24 May 30 03:11:43 PM PDT 24 807780336 ps
T105 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2131257834 May 30 03:11:50 PM PDT 24 May 30 03:13:27 PM PDT 24 46816405739 ps
T864 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1045133086 May 30 03:12:03 PM PDT 24 May 30 03:12:08 PM PDT 24 605829684 ps
T106 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.825924981 May 30 03:12:26 PM PDT 24 May 30 03:12:29 PM PDT 24 431461720 ps
T865 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1735828608 May 30 03:13:08 PM PDT 24 May 30 03:13:10 PM PDT 24 531850778 ps
T866 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2816321956 May 30 03:11:48 PM PDT 24 May 30 03:11:52 PM PDT 24 585333259 ps
T867 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3620896119 May 30 03:12:27 PM PDT 24 May 30 03:12:32 PM PDT 24 3961458254 ps
T868 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3866230531 May 30 03:12:39 PM PDT 24 May 30 03:12:41 PM PDT 24 495802012 ps
T869 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.343844397 May 30 03:12:25 PM PDT 24 May 30 03:12:36 PM PDT 24 8279090553 ps
T870 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.73694721 May 30 03:12:00 PM PDT 24 May 30 03:12:15 PM PDT 24 4535388993 ps
T871 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1465393772 May 30 03:11:50 PM PDT 24 May 30 03:11:54 PM PDT 24 362698117 ps
T872 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1949139890 May 30 03:13:10 PM PDT 24 May 30 03:13:14 PM PDT 24 332381245 ps
T873 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1802673656 May 30 03:11:50 PM PDT 24 May 30 03:11:52 PM PDT 24 421596382 ps
T874 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3082563264 May 30 03:12:40 PM PDT 24 May 30 03:12:43 PM PDT 24 554552018 ps
T875 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2247310513 May 30 03:12:26 PM PDT 24 May 30 03:12:50 PM PDT 24 8148961346 ps
T876 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2615870667 May 30 03:11:48 PM PDT 24 May 30 03:11:51 PM PDT 24 379609422 ps
T877 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3349481786 May 30 03:12:25 PM PDT 24 May 30 03:12:30 PM PDT 24 388741709 ps
T878 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.260293497 May 30 03:12:02 PM PDT 24 May 30 03:12:05 PM PDT 24 421275294 ps
T879 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2946847638 May 30 03:12:03 PM PDT 24 May 30 03:12:07 PM PDT 24 471432939 ps
T880 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2071602396 May 30 03:12:55 PM PDT 24 May 30 03:12:59 PM PDT 24 714557802 ps
T881 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.615525873 May 30 03:12:26 PM PDT 24 May 30 03:12:29 PM PDT 24 401873316 ps
T882 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1112797356 May 30 03:13:09 PM PDT 24 May 30 03:13:13 PM PDT 24 530274716 ps
T883 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3376864447 May 30 03:12:54 PM PDT 24 May 30 03:12:56 PM PDT 24 426755715 ps
T884 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.753660413 May 30 03:12:02 PM PDT 24 May 30 03:12:06 PM PDT 24 482360880 ps
T885 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1485971760 May 30 03:12:56 PM PDT 24 May 30 03:12:58 PM PDT 24 426620577 ps
T886 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2096843781 May 30 03:11:22 PM PDT 24 May 30 03:11:25 PM PDT 24 378499552 ps
T887 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3639686697 May 30 03:13:07 PM PDT 24 May 30 03:13:09 PM PDT 24 390548952 ps
T888 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.910781054 May 30 03:12:55 PM PDT 24 May 30 03:12:57 PM PDT 24 506070358 ps
T889 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.78861092 May 30 03:11:51 PM PDT 24 May 30 03:11:54 PM PDT 24 441445289 ps
T890 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3684509714 May 30 03:11:37 PM PDT 24 May 30 03:11:41 PM PDT 24 534068765 ps
T891 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1481329915 May 30 03:12:38 PM PDT 24 May 30 03:12:42 PM PDT 24 2597532627 ps
T892 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2710666342 May 30 03:11:23 PM PDT 24 May 30 03:11:26 PM PDT 24 503082132 ps
T893 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1147303371 May 30 03:11:38 PM PDT 24 May 30 03:11:41 PM PDT 24 440385860 ps
T894 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.385806398 May 30 03:12:55 PM PDT 24 May 30 03:13:00 PM PDT 24 3595342501 ps
T895 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3911455994 May 30 03:12:56 PM PDT 24 May 30 03:12:59 PM PDT 24 529525598 ps
T896 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.926262714 May 30 03:12:54 PM PDT 24 May 30 03:12:57 PM PDT 24 544558963 ps
T897 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.96544748 May 30 03:12:38 PM PDT 24 May 30 03:12:47 PM PDT 24 8618682319 ps
T898 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1979858638 May 30 03:12:20 PM PDT 24 May 30 03:12:24 PM PDT 24 549870091 ps
T899 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1826336096 May 30 03:11:08 PM PDT 24 May 30 03:11:10 PM PDT 24 411156633 ps
T320 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1649398927 May 30 03:11:21 PM PDT 24 May 30 03:11:31 PM PDT 24 8801287539 ps
T900 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.388212265 May 30 03:12:40 PM PDT 24 May 30 03:12:43 PM PDT 24 440462730 ps
T901 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3246601908 May 30 03:11:09 PM PDT 24 May 30 03:11:11 PM PDT 24 484486843 ps
T902 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3359193337 May 30 03:13:09 PM PDT 24 May 30 03:13:13 PM PDT 24 417319348 ps
T903 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.726963312 May 30 03:12:28 PM PDT 24 May 30 03:12:32 PM PDT 24 2135686284 ps
T904 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.818950888 May 30 03:11:10 PM PDT 24 May 30 03:11:14 PM PDT 24 702139159 ps
T905 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.542419600 May 30 03:13:08 PM PDT 24 May 30 03:13:12 PM PDT 24 481499796 ps
T906 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1964206275 May 30 03:11:50 PM PDT 24 May 30 03:11:59 PM PDT 24 5261434281 ps
T907 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.4087009040 May 30 03:12:12 PM PDT 24 May 30 03:12:15 PM PDT 24 448376184 ps
T908 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3812420679 May 30 03:12:25 PM PDT 24 May 30 03:12:35 PM PDT 24 4598528784 ps
T909 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.582569921 May 30 03:11:49 PM PDT 24 May 30 03:11:51 PM PDT 24 500926851 ps
T910 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.103465216 May 30 03:12:40 PM PDT 24 May 30 03:12:44 PM PDT 24 473378655 ps
T911 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.4208017876 May 30 03:12:57 PM PDT 24 May 30 03:12:59 PM PDT 24 832436795 ps
T912 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1068349527 May 30 03:12:28 PM PDT 24 May 30 03:12:32 PM PDT 24 512124354 ps
T913 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.563172913 May 30 03:12:00 PM PDT 24 May 30 03:12:03 PM PDT 24 562622373 ps
T914 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1739998078 May 30 03:12:01 PM PDT 24 May 30 03:12:06 PM PDT 24 572253380 ps
T915 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.184254855 May 30 03:13:11 PM PDT 24 May 30 03:13:16 PM PDT 24 466575313 ps
T916 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2987569301 May 30 03:12:56 PM PDT 24 May 30 03:12:59 PM PDT 24 460377447 ps
T917 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1602869271 May 30 03:12:56 PM PDT 24 May 30 03:13:01 PM PDT 24 4104733007 ps
T918 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.4030982071 May 30 03:12:15 PM PDT 24 May 30 03:12:18 PM PDT 24 413363901 ps
T919 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2263770819 May 30 03:12:41 PM PDT 24 May 30 03:12:49 PM PDT 24 4906832484 ps
T920 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3591796800 May 30 03:11:09 PM PDT 24 May 30 03:11:11 PM PDT 24 1193797783 ps

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1279144760
Short name T5
Test name
Test status
Simulation time 194669328311 ps
CPU time 205.66 seconds
Started May 30 03:22:21 PM PDT 24
Finished May 30 03:25:48 PM PDT 24
Peak memory 210120 kb
Host smart-c71e990c-c97e-4145-9c1c-2b12b52769bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279144760 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1279144760
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.4135704723
Short name T8
Test name
Test status
Simulation time 460809426942 ps
CPU time 497.88 seconds
Started May 30 03:19:25 PM PDT 24
Finished May 30 03:27:44 PM PDT 24
Peak memory 202192 kb
Host smart-61a780eb-e4ff-4f18-ab18-8f08b9227115
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135704723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.4135704723
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.994506609
Short name T35
Test name
Test status
Simulation time 508038761370 ps
CPU time 521.1 seconds
Started May 30 03:15:03 PM PDT 24
Finished May 30 03:23:45 PM PDT 24
Peak memory 201816 kb
Host smart-ce1f4a1b-a1c7-49c2-ac66-d84f3fa93001
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994506609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.994506609
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3432647437
Short name T40
Test name
Test status
Simulation time 73582124820 ps
CPU time 400.68 seconds
Started May 30 03:17:02 PM PDT 24
Finished May 30 03:23:44 PM PDT 24
Peak memory 202084 kb
Host smart-edbbc8a0-0de7-4a61-ae75-051fa1270f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432647437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3432647437
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2688515978
Short name T195
Test name
Test status
Simulation time 501258092708 ps
CPU time 606.01 seconds
Started May 30 03:24:54 PM PDT 24
Finished May 30 03:35:01 PM PDT 24
Peak memory 201740 kb
Host smart-d61f71a9-2867-4577-b20c-b452b7daa9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688515978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2688515978
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.305930894
Short name T126
Test name
Test status
Simulation time 526801813153 ps
CPU time 1289.49 seconds
Started May 30 03:15:02 PM PDT 24
Finished May 30 03:36:33 PM PDT 24
Peak memory 201780 kb
Host smart-0a10504c-b5ac-4a52-9ff5-68abf698942e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305930894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.305930894
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2958387678
Short name T93
Test name
Test status
Simulation time 493995616769 ps
CPU time 1157.96 seconds
Started May 30 03:24:13 PM PDT 24
Finished May 30 03:43:31 PM PDT 24
Peak memory 201812 kb
Host smart-c970f87e-621a-4fc7-88a0-882bf6d5f74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958387678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2958387678
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2317333950
Short name T46
Test name
Test status
Simulation time 518672048325 ps
CPU time 762.61 seconds
Started May 30 03:18:12 PM PDT 24
Finished May 30 03:30:56 PM PDT 24
Peak memory 201848 kb
Host smart-b075f8be-fa72-4a53-a623-04bb8d66fd65
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317333950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2317333950
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2052812164
Short name T194
Test name
Test status
Simulation time 528806183244 ps
CPU time 1241.29 seconds
Started May 30 03:22:22 PM PDT 24
Finished May 30 03:43:05 PM PDT 24
Peak memory 201888 kb
Host smart-4144ff2d-cb76-41c7-ad68-08d685a29795
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052812164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2052812164
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.26597116
Short name T34
Test name
Test status
Simulation time 543546577235 ps
CPU time 320.15 seconds
Started May 30 03:16:48 PM PDT 24
Finished May 30 03:22:11 PM PDT 24
Peak memory 201888 kb
Host smart-7ecba9a5-1f4f-4255-b81e-30c56ece55d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26597116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_w
akeup.26597116
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.351244141
Short name T151
Test name
Test status
Simulation time 516977206580 ps
CPU time 314.88 seconds
Started May 30 03:19:48 PM PDT 24
Finished May 30 03:25:03 PM PDT 24
Peak memory 201872 kb
Host smart-85eaead8-7a25-4515-957b-c5adbb907d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351244141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.351244141
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3025257919
Short name T55
Test name
Test status
Simulation time 795367897 ps
CPU time 2.62 seconds
Started May 30 03:12:40 PM PDT 24
Finished May 30 03:12:45 PM PDT 24
Peak memory 202028 kb
Host smart-2164f7ad-b8e3-4638-9512-906379d32613
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025257919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3025257919
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.153228503
Short name T143
Test name
Test status
Simulation time 337049533392 ps
CPU time 205.21 seconds
Started May 30 03:19:47 PM PDT 24
Finished May 30 03:23:14 PM PDT 24
Peak memory 201828 kb
Host smart-28362a0d-9e9d-4f2c-8f4a-97df3e1fc16b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153228503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.153228503
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3900288115
Short name T197
Test name
Test status
Simulation time 494740986060 ps
CPU time 636.57 seconds
Started May 30 03:21:30 PM PDT 24
Finished May 30 03:32:08 PM PDT 24
Peak memory 210388 kb
Host smart-ce28e13f-f9b3-407d-8886-2f601405416b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900288115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3900288115
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2978782836
Short name T7
Test name
Test status
Simulation time 349332896652 ps
CPU time 176.98 seconds
Started May 30 03:17:52 PM PDT 24
Finished May 30 03:20:50 PM PDT 24
Peak memory 201900 kb
Host smart-0e950eed-6474-4907-9ce1-3d2142786537
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978782836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2978782836
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3618994434
Short name T348
Test name
Test status
Simulation time 564179276 ps
CPU time 0.92 seconds
Started May 30 03:16:28 PM PDT 24
Finished May 30 03:16:30 PM PDT 24
Peak memory 201484 kb
Host smart-bcdebaff-b0ef-4a34-8223-bc3458a8f95d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618994434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3618994434
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3661007458
Short name T45
Test name
Test status
Simulation time 4290206375 ps
CPU time 5.04 seconds
Started May 30 03:11:37 PM PDT 24
Finished May 30 03:11:44 PM PDT 24
Peak memory 202004 kb
Host smart-7f773552-5620-4cb8-a9c9-f1cec817e826
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661007458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3661007458
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1141273010
Short name T37
Test name
Test status
Simulation time 433634246799 ps
CPU time 510.88 seconds
Started May 30 03:21:49 PM PDT 24
Finished May 30 03:30:22 PM PDT 24
Peak memory 213036 kb
Host smart-a4894cc8-4314-4005-a5b8-76ba1a0047ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141273010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1141273010
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2630220503
Short name T252
Test name
Test status
Simulation time 578937914145 ps
CPU time 1100.56 seconds
Started May 30 03:15:39 PM PDT 24
Finished May 30 03:34:01 PM PDT 24
Peak memory 201824 kb
Host smart-465a668b-2b7b-4af3-9d03-d7d1d8ba81d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630220503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2630220503
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3272269666
Short name T74
Test name
Test status
Simulation time 7964849645 ps
CPU time 20.3 seconds
Started May 30 03:14:26 PM PDT 24
Finished May 30 03:14:47 PM PDT 24
Peak memory 218024 kb
Host smart-e19ffe3d-4259-4709-9b50-7bee0dd8cda9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272269666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3272269666
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3479300387
Short name T184
Test name
Test status
Simulation time 810422404317 ps
CPU time 882.36 seconds
Started May 30 03:21:57 PM PDT 24
Finished May 30 03:36:40 PM PDT 24
Peak memory 217936 kb
Host smart-8f7fec17-566a-431e-b44d-2c65c76352b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479300387 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3479300387
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.323914990
Short name T136
Test name
Test status
Simulation time 498605647530 ps
CPU time 1048.04 seconds
Started May 30 03:18:55 PM PDT 24
Finished May 30 03:36:24 PM PDT 24
Peak memory 201800 kb
Host smart-4c8301e2-7103-47f8-8eef-90d687fe13bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323914990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.323914990
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1234234973
Short name T273
Test name
Test status
Simulation time 507758469416 ps
CPU time 305.98 seconds
Started May 30 03:19:56 PM PDT 24
Finished May 30 03:25:04 PM PDT 24
Peak memory 201864 kb
Host smart-b87caecb-e143-4ea6-9d45-7a50014d5f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234234973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1234234973
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1873122576
Short name T160
Test name
Test status
Simulation time 495194553219 ps
CPU time 230.84 seconds
Started May 30 03:20:07 PM PDT 24
Finished May 30 03:23:59 PM PDT 24
Peak memory 201800 kb
Host smart-1beaf324-53f5-4295-bcb4-3428eafa7c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873122576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1873122576
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1574697420
Short name T123
Test name
Test status
Simulation time 509251819677 ps
CPU time 846.94 seconds
Started May 30 03:15:04 PM PDT 24
Finished May 30 03:29:12 PM PDT 24
Peak memory 201876 kb
Host smart-d3eae577-f606-4b0e-b6fd-eb947835b4e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574697420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1574697420
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.171945978
Short name T36
Test name
Test status
Simulation time 191213968446 ps
CPU time 433.89 seconds
Started May 30 03:16:29 PM PDT 24
Finished May 30 03:23:44 PM PDT 24
Peak memory 201808 kb
Host smart-03b630c9-7463-4a65-b308-9ef8139f3344
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171945978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
adc_ctrl_filters_wakeup_fixed.171945978
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.385757572
Short name T39
Test name
Test status
Simulation time 426068028427 ps
CPU time 1176 seconds
Started May 30 03:20:07 PM PDT 24
Finished May 30 03:39:45 PM PDT 24
Peak memory 210384 kb
Host smart-68b7302b-40fb-4887-be85-8c2b6eeb6446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385757572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
385757572
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1098082374
Short name T173
Test name
Test status
Simulation time 522106504693 ps
CPU time 270.84 seconds
Started May 30 03:15:25 PM PDT 24
Finished May 30 03:19:57 PM PDT 24
Peak memory 201816 kb
Host smart-1edf18c3-c048-4b76-89fd-95fbde9234e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098082374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1098082374
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3781723796
Short name T256
Test name
Test status
Simulation time 696321523379 ps
CPU time 1432.16 seconds
Started May 30 03:17:39 PM PDT 24
Finished May 30 03:41:33 PM PDT 24
Peak memory 201864 kb
Host smart-be3d0f96-8b49-4c07-9075-6e3c2e72c3a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781723796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3781723796
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.516665045
Short name T209
Test name
Test status
Simulation time 500799975956 ps
CPU time 616.8 seconds
Started May 30 03:17:52 PM PDT 24
Finished May 30 03:28:10 PM PDT 24
Peak memory 201780 kb
Host smart-6801231e-dd6f-4b39-a473-7c4b96a507bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516665045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.516665045
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1863275419
Short name T57
Test name
Test status
Simulation time 8315013461 ps
CPU time 7.45 seconds
Started May 30 03:12:55 PM PDT 24
Finished May 30 03:13:04 PM PDT 24
Peak memory 201952 kb
Host smart-f2492f03-ba87-4825-8617-57700ae589ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863275419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1863275419
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.420674221
Short name T228
Test name
Test status
Simulation time 538624042263 ps
CPU time 1164.21 seconds
Started May 30 03:21:28 PM PDT 24
Finished May 30 03:40:54 PM PDT 24
Peak memory 201776 kb
Host smart-2a271431-3f94-42f3-b8c2-be59142c0d2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420674221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
420674221
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3186203459
Short name T182
Test name
Test status
Simulation time 324922008618 ps
CPU time 921.87 seconds
Started May 30 03:15:55 PM PDT 24
Finished May 30 03:31:18 PM PDT 24
Peak memory 210360 kb
Host smart-46de5be7-6ce1-4acd-942e-d877e00b3655
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186203459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3186203459
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.282900680
Short name T220
Test name
Test status
Simulation time 165409860289 ps
CPU time 183.35 seconds
Started May 30 03:16:38 PM PDT 24
Finished May 30 03:19:43 PM PDT 24
Peak memory 201760 kb
Host smart-292f69e2-db3d-4d33-9f9c-5347a4bbf950
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282900680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gati
ng.282900680
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3581938271
Short name T232
Test name
Test status
Simulation time 358164258960 ps
CPU time 204.27 seconds
Started May 30 03:18:47 PM PDT 24
Finished May 30 03:22:13 PM PDT 24
Peak memory 201772 kb
Host smart-b9ada36f-1134-4dbb-b493-80058b1b779e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581938271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3581938271
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.402997879
Short name T204
Test name
Test status
Simulation time 489001424771 ps
CPU time 220.49 seconds
Started May 30 03:20:06 PM PDT 24
Finished May 30 03:23:49 PM PDT 24
Peak memory 201804 kb
Host smart-714ab0e7-8401-4753-a9db-5fc316f7549e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402997879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.402997879
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1493899882
Short name T268
Test name
Test status
Simulation time 360437068293 ps
CPU time 146.82 seconds
Started May 30 03:21:18 PM PDT 24
Finished May 30 03:23:47 PM PDT 24
Peak memory 201784 kb
Host smart-0370ae94-30ce-49bb-902a-a923eae38072
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493899882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1493899882
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1437919289
Short name T125
Test name
Test status
Simulation time 542710355078 ps
CPU time 1252.71 seconds
Started May 30 03:18:47 PM PDT 24
Finished May 30 03:39:41 PM PDT 24
Peak memory 201760 kb
Host smart-b1fa5244-fcac-41d6-99ed-2a5ff9b13e11
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437919289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1437919289
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3680098288
Short name T164
Test name
Test status
Simulation time 604571300397 ps
CPU time 180.67 seconds
Started May 30 03:23:07 PM PDT 24
Finished May 30 03:26:09 PM PDT 24
Peak memory 201860 kb
Host smart-177b7dcd-6d16-49ce-a013-bf3e30421dd1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680098288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3680098288
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3465774136
Short name T26
Test name
Test status
Simulation time 362207491104 ps
CPU time 841.9 seconds
Started May 30 03:20:20 PM PDT 24
Finished May 30 03:34:23 PM PDT 24
Peak memory 201772 kb
Host smart-a0cb274c-41d9-4cb4-bd89-892a9cdd6f9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465774136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3465774136
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.372849797
Short name T279
Test name
Test status
Simulation time 509335084646 ps
CPU time 1223.97 seconds
Started May 30 03:23:35 PM PDT 24
Finished May 30 03:44:00 PM PDT 24
Peak memory 201816 kb
Host smart-a5dd7acf-32a5-47a6-84c7-ddf39a623bc2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372849797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gati
ng.372849797
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.190471647
Short name T111
Test name
Test status
Simulation time 351994947 ps
CPU time 1.72 seconds
Started May 30 03:11:08 PM PDT 24
Finished May 30 03:11:11 PM PDT 24
Peak memory 201720 kb
Host smart-a6e68c09-c503-4142-b9f2-5e7fb0fd0595
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190471647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.190471647
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3025656123
Short name T245
Test name
Test status
Simulation time 177223238764 ps
CPU time 68.46 seconds
Started May 30 03:20:32 PM PDT 24
Finished May 30 03:21:42 PM PDT 24
Peak memory 201908 kb
Host smart-c4273ddb-0f09-4b2e-b535-992a6220580c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025656123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3025656123
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2746999628
Short name T244
Test name
Test status
Simulation time 72447325490 ps
CPU time 233.61 seconds
Started May 30 03:21:02 PM PDT 24
Finished May 30 03:24:56 PM PDT 24
Peak memory 210380 kb
Host smart-6fa5d1a3-0fee-475b-bbd8-21abee275639
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746999628 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2746999628
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.4030729712
Short name T138
Test name
Test status
Simulation time 241693101383 ps
CPU time 553.28 seconds
Started May 30 03:23:46 PM PDT 24
Finished May 30 03:33:01 PM PDT 24
Peak memory 201804 kb
Host smart-ecb6b4f5-5409-4ff2-861f-ca2c0e5619cc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030729712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.4030729712
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2057682435
Short name T193
Test name
Test status
Simulation time 166161233776 ps
CPU time 392.41 seconds
Started May 30 03:17:24 PM PDT 24
Finished May 30 03:23:57 PM PDT 24
Peak memory 201784 kb
Host smart-288268b2-234b-42cf-8654-ffb337643c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057682435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2057682435
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3104338630
Short name T269
Test name
Test status
Simulation time 552383767764 ps
CPU time 1272.72 seconds
Started May 30 03:17:51 PM PDT 24
Finished May 30 03:39:05 PM PDT 24
Peak memory 201904 kb
Host smart-044b2196-a52c-4a13-a120-c35bc74d40f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104338630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3104338630
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2474603263
Short name T167
Test name
Test status
Simulation time 522233217589 ps
CPU time 95.5 seconds
Started May 30 03:21:19 PM PDT 24
Finished May 30 03:22:56 PM PDT 24
Peak memory 201792 kb
Host smart-2bcfad11-ade0-4c33-bf75-ffd91d1a26c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474603263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2474603263
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.3323401787
Short name T186
Test name
Test status
Simulation time 328387943231 ps
CPU time 538.33 seconds
Started May 30 03:23:35 PM PDT 24
Finished May 30 03:32:35 PM PDT 24
Peak memory 210300 kb
Host smart-0a7e2be1-7db5-4083-a07a-20f97a002b4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323401787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.3323401787
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.4189367576
Short name T1
Test name
Test status
Simulation time 337287737626 ps
CPU time 776.24 seconds
Started May 30 03:14:47 PM PDT 24
Finished May 30 03:27:45 PM PDT 24
Peak memory 201884 kb
Host smart-748f86ad-177d-42cb-84c3-316611f8e83f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189367576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
4189367576
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1280982283
Short name T275
Test name
Test status
Simulation time 563468792863 ps
CPU time 684.54 seconds
Started May 30 03:14:26 PM PDT 24
Finished May 30 03:25:52 PM PDT 24
Peak memory 201864 kb
Host smart-9ade3452-5055-4f71-b791-c1175823cb65
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280982283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1280982283
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.423138723
Short name T246
Test name
Test status
Simulation time 291823097999 ps
CPU time 425.27 seconds
Started May 30 03:16:28 PM PDT 24
Finished May 30 03:23:35 PM PDT 24
Peak memory 210316 kb
Host smart-a05569ae-af70-4126-80b4-dcd6a725b798
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423138723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.
423138723
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.789384217
Short name T129
Test name
Test status
Simulation time 161060164247 ps
CPU time 368.38 seconds
Started May 30 03:17:51 PM PDT 24
Finished May 30 03:24:01 PM PDT 24
Peak memory 201792 kb
Host smart-41d53348-f077-432e-9763-ba65d7b51f37
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=789384217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.789384217
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1026382892
Short name T30
Test name
Test status
Simulation time 81846036494 ps
CPU time 100.63 seconds
Started May 30 03:14:35 PM PDT 24
Finished May 30 03:16:17 PM PDT 24
Peak memory 210084 kb
Host smart-b8f43428-cf60-4588-a5fb-066cda72d4f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026382892 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1026382892
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2590843547
Short name T305
Test name
Test status
Simulation time 514620038277 ps
CPU time 304.34 seconds
Started May 30 03:21:48 PM PDT 24
Finished May 30 03:26:54 PM PDT 24
Peak memory 201792 kb
Host smart-00545466-42a6-45c0-82d8-fe3dfd46971a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590843547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2590843547
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.123888716
Short name T274
Test name
Test status
Simulation time 166646649412 ps
CPU time 362.15 seconds
Started May 30 03:23:37 PM PDT 24
Finished May 30 03:29:40 PM PDT 24
Peak memory 201804 kb
Host smart-ef588aad-c84f-421c-ba87-05c8f7606ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123888716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.123888716
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.174636937
Short name T18
Test name
Test status
Simulation time 472249033159 ps
CPU time 259.45 seconds
Started May 30 03:24:44 PM PDT 24
Finished May 30 03:29:04 PM PDT 24
Peak memory 218596 kb
Host smart-982b0679-0561-4035-9ad4-cc866eaaa467
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174636937 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.174636937
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.820433581
Short name T297
Test name
Test status
Simulation time 389657453746 ps
CPU time 230.92 seconds
Started May 30 03:24:53 PM PDT 24
Finished May 30 03:28:44 PM PDT 24
Peak memory 201812 kb
Host smart-e780fe19-2ec2-4494-afb1-155891207a4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820433581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
820433581
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1118624107
Short name T222
Test name
Test status
Simulation time 487536989515 ps
CPU time 283.89 seconds
Started May 30 03:20:42 PM PDT 24
Finished May 30 03:25:27 PM PDT 24
Peak memory 201804 kb
Host smart-c42654f6-65c3-41ea-9690-2db1ce0173cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118624107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1118624107
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.269167261
Short name T205
Test name
Test status
Simulation time 350389520204 ps
CPU time 216.38 seconds
Started May 30 03:21:30 PM PDT 24
Finished May 30 03:25:08 PM PDT 24
Peak memory 201812 kb
Host smart-82262b25-bdd0-4c5e-8781-cb27b8e0ee63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269167261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.269167261
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2083740768
Short name T296
Test name
Test status
Simulation time 492942128887 ps
CPU time 118.36 seconds
Started May 30 03:21:47 PM PDT 24
Finished May 30 03:23:47 PM PDT 24
Peak memory 201892 kb
Host smart-a0fcff2b-c452-4b3e-9604-9584b4107735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083740768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2083740768
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1649398927
Short name T320
Test name
Test status
Simulation time 8801287539 ps
CPU time 8.28 seconds
Started May 30 03:11:21 PM PDT 24
Finished May 30 03:11:31 PM PDT 24
Peak memory 201988 kb
Host smart-e2353365-fa05-47bb-8dbe-bb92246a4daf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649398927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1649398927
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3523210637
Short name T266
Test name
Test status
Simulation time 328072575829 ps
CPU time 737.54 seconds
Started May 30 03:16:26 PM PDT 24
Finished May 30 03:28:45 PM PDT 24
Peak memory 201772 kb
Host smart-86dd669d-8a44-4689-8e04-7ad818c15ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523210637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3523210637
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.320540107
Short name T265
Test name
Test status
Simulation time 499750116721 ps
CPU time 295.16 seconds
Started May 30 03:18:17 PM PDT 24
Finished May 30 03:23:13 PM PDT 24
Peak memory 201816 kb
Host smart-046507a7-0621-4869-9408-493e8f90cf7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320540107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.
320540107
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2032686613
Short name T243
Test name
Test status
Simulation time 439314084615 ps
CPU time 71.52 seconds
Started May 30 03:19:36 PM PDT 24
Finished May 30 03:20:48 PM PDT 24
Peak memory 201804 kb
Host smart-8f384594-58c3-4c4f-8561-70b4191f10e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032686613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2032686613
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2922183724
Short name T196
Test name
Test status
Simulation time 496338215708 ps
CPU time 307.8 seconds
Started May 30 03:20:31 PM PDT 24
Finished May 30 03:25:41 PM PDT 24
Peak memory 201752 kb
Host smart-55f98e80-92f9-4280-8f03-d9181bc4db0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922183724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2922183724
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3048771425
Short name T188
Test name
Test status
Simulation time 282839312453 ps
CPU time 637.97 seconds
Started May 30 03:20:31 PM PDT 24
Finished May 30 03:31:11 PM PDT 24
Peak memory 211872 kb
Host smart-0f34bd1a-cdc2-49d3-896b-6373393f1be2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048771425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3048771425
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1199599167
Short name T283
Test name
Test status
Simulation time 167891971953 ps
CPU time 200.03 seconds
Started May 30 03:20:53 PM PDT 24
Finished May 30 03:24:14 PM PDT 24
Peak memory 201760 kb
Host smart-2cddec2b-d4e2-4eff-9612-b4f41358a777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199599167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1199599167
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1975847656
Short name T218
Test name
Test status
Simulation time 138860842304 ps
CPU time 185.14 seconds
Started May 30 03:21:28 PM PDT 24
Finished May 30 03:24:35 PM PDT 24
Peak memory 210408 kb
Host smart-e8155c75-7cb0-4f8f-99c0-2be0162d6895
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975847656 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1975847656
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3330205745
Short name T227
Test name
Test status
Simulation time 496421886317 ps
CPU time 1056.54 seconds
Started May 30 03:23:08 PM PDT 24
Finished May 30 03:40:46 PM PDT 24
Peak memory 201788 kb
Host smart-d0635346-14b1-4068-af2c-213f29410f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330205745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3330205745
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.176968214
Short name T221
Test name
Test status
Simulation time 284843042273 ps
CPU time 505.4 seconds
Started May 30 03:24:04 PM PDT 24
Finished May 30 03:32:31 PM PDT 24
Peak memory 201856 kb
Host smart-f985b1fa-67ac-49aa-af5a-1d6450cc74af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176968214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.176968214
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2339076461
Short name T176
Test name
Test status
Simulation time 158863486414 ps
CPU time 192.08 seconds
Started May 30 03:14:48 PM PDT 24
Finished May 30 03:18:02 PM PDT 24
Peak memory 201828 kb
Host smart-a2a22831-f07a-4073-8613-cb332254ef26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339076461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2339076461
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3700610044
Short name T854
Test name
Test status
Simulation time 587047839 ps
CPU time 2.33 seconds
Started May 30 03:11:12 PM PDT 24
Finished May 30 03:11:16 PM PDT 24
Peak memory 201984 kb
Host smart-6585955c-2d17-40f3-b26e-ef8e88c7d09f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700610044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3700610044
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3731193391
Short name T152
Test name
Test status
Simulation time 538900351403 ps
CPU time 1318.43 seconds
Started May 30 03:14:18 PM PDT 24
Finished May 30 03:36:18 PM PDT 24
Peak memory 201904 kb
Host smart-97f1fa61-71bd-4484-b50e-6b004a574961
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731193391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3731193391
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3271185570
Short name T309
Test name
Test status
Simulation time 618170914779 ps
CPU time 1511.46 seconds
Started May 30 03:16:05 PM PDT 24
Finished May 30 03:41:18 PM PDT 24
Peak memory 201892 kb
Host smart-8e7bb29e-f484-4602-9896-7a5e44ef0565
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271185570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3271185570
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2514717310
Short name T324
Test name
Test status
Simulation time 80172041897 ps
CPU time 247.5 seconds
Started May 30 03:16:27 PM PDT 24
Finished May 30 03:20:36 PM PDT 24
Peak memory 202116 kb
Host smart-54f62171-c236-4e20-8114-fa5c32f9a39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514717310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2514717310
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1600716489
Short name T321
Test name
Test status
Simulation time 103863085943 ps
CPU time 336.39 seconds
Started May 30 03:17:37 PM PDT 24
Finished May 30 03:23:15 PM PDT 24
Peak memory 202180 kb
Host smart-926a6640-745e-408e-86b6-c25d29442105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600716489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1600716489
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2514309106
Short name T300
Test name
Test status
Simulation time 490413727927 ps
CPU time 563.96 seconds
Started May 30 03:22:12 PM PDT 24
Finished May 30 03:31:38 PM PDT 24
Peak memory 201892 kb
Host smart-0c7349ef-c0d7-4cfe-bc43-860d4e47268a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514309106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2514309106
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3162171546
Short name T231
Test name
Test status
Simulation time 321022644532 ps
CPU time 773.09 seconds
Started May 30 03:23:47 PM PDT 24
Finished May 30 03:36:41 PM PDT 24
Peak memory 201800 kb
Host smart-69c70d0e-1a06-4259-8513-064ba392baec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162171546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3162171546
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.4135160884
Short name T258
Test name
Test status
Simulation time 526555791315 ps
CPU time 1287.41 seconds
Started May 30 03:14:49 PM PDT 24
Finished May 30 03:36:18 PM PDT 24
Peak memory 201812 kb
Host smart-5fd27792-5f5d-469e-ae61-70a90ebc4c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135160884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.4135160884
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.818950888
Short name T904
Test name
Test status
Simulation time 702139159 ps
CPU time 3.66 seconds
Started May 30 03:11:10 PM PDT 24
Finished May 30 03:11:14 PM PDT 24
Peak memory 201896 kb
Host smart-5a0caf21-82e6-42bf-b901-ed16885388f5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818950888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.818950888
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2557783038
Short name T824
Test name
Test status
Simulation time 52420365041 ps
CPU time 129.26 seconds
Started May 30 03:11:12 PM PDT 24
Finished May 30 03:13:22 PM PDT 24
Peak memory 202012 kb
Host smart-8511b52d-7e54-47e6-bb35-106a9a5b4310
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557783038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2557783038
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3591796800
Short name T920
Test name
Test status
Simulation time 1193797783 ps
CPU time 1.81 seconds
Started May 30 03:11:09 PM PDT 24
Finished May 30 03:11:11 PM PDT 24
Peak memory 201752 kb
Host smart-6ffa6ac5-ca90-48a5-ac29-2c18fe67f4a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591796800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3591796800
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3246601908
Short name T901
Test name
Test status
Simulation time 484486843 ps
CPU time 1.03 seconds
Started May 30 03:11:09 PM PDT 24
Finished May 30 03:11:11 PM PDT 24
Peak memory 201804 kb
Host smart-3b66cc12-8198-40e0-a450-85ec98bea56e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246601908 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3246601908
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2452082462
Short name T834
Test name
Test status
Simulation time 310682842 ps
CPU time 0.99 seconds
Started May 30 03:11:07 PM PDT 24
Finished May 30 03:11:09 PM PDT 24
Peak memory 201748 kb
Host smart-6a8cf64f-5adb-47ee-a50d-97b28b642cb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452082462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2452082462
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.916828656
Short name T836
Test name
Test status
Simulation time 2103175598 ps
CPU time 5.68 seconds
Started May 30 03:11:12 PM PDT 24
Finished May 30 03:11:18 PM PDT 24
Peak memory 201732 kb
Host smart-2100b450-1b39-4396-a9a6-fe69df819574
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916828656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.916828656
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.132738344
Short name T835
Test name
Test status
Simulation time 8350517040 ps
CPU time 11.57 seconds
Started May 30 03:11:10 PM PDT 24
Finished May 30 03:11:23 PM PDT 24
Peak memory 201904 kb
Host smart-668b93da-54f4-4ad2-83d6-17c4db4af095
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132738344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.132738344
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1875826867
Short name T95
Test name
Test status
Simulation time 1020491579 ps
CPU time 4.61 seconds
Started May 30 03:11:21 PM PDT 24
Finished May 30 03:11:27 PM PDT 24
Peak memory 201852 kb
Host smart-ab385b53-99f1-462b-8c35-4584da65d919
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875826867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1875826867
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3974763465
Short name T98
Test name
Test status
Simulation time 47120606391 ps
CPU time 74.24 seconds
Started May 30 03:11:22 PM PDT 24
Finished May 30 03:12:38 PM PDT 24
Peak memory 202008 kb
Host smart-51bd8717-b7d6-4f3d-9261-c4b9640cbb1a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974763465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3974763465
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2527218599
Short name T825
Test name
Test status
Simulation time 1411273412 ps
CPU time 1.71 seconds
Started May 30 03:11:10 PM PDT 24
Finished May 30 03:11:12 PM PDT 24
Peak memory 201684 kb
Host smart-88e343b5-31d2-426d-8a5b-85abf454f7d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527218599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2527218599
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3282166483
Short name T822
Test name
Test status
Simulation time 481881388 ps
CPU time 1.05 seconds
Started May 30 03:11:22 PM PDT 24
Finished May 30 03:11:25 PM PDT 24
Peak memory 201784 kb
Host smart-3d0e2b10-ef02-42f8-aedd-05f738ebe1d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282166483 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3282166483
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3086614305
Short name T107
Test name
Test status
Simulation time 585133230 ps
CPU time 1.12 seconds
Started May 30 03:11:22 PM PDT 24
Finished May 30 03:11:25 PM PDT 24
Peak memory 201728 kb
Host smart-aa605005-dcf5-4dc9-a990-729fdfb737c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086614305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3086614305
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1826336096
Short name T899
Test name
Test status
Simulation time 411156633 ps
CPU time 0.87 seconds
Started May 30 03:11:08 PM PDT 24
Finished May 30 03:11:10 PM PDT 24
Peak memory 201736 kb
Host smart-ae85afb4-9972-4393-a547-4bae0c7b67bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826336096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1826336096
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3242512147
Short name T44
Test name
Test status
Simulation time 2140637784 ps
CPU time 2.16 seconds
Started May 30 03:11:27 PM PDT 24
Finished May 30 03:11:30 PM PDT 24
Peak memory 201664 kb
Host smart-d03ae0fa-8ff9-46e2-92b3-1ffc11999ce2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242512147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3242512147
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1714543356
Short name T50
Test name
Test status
Simulation time 404326390 ps
CPU time 2.21 seconds
Started May 30 03:11:08 PM PDT 24
Finished May 30 03:11:11 PM PDT 24
Peak memory 201968 kb
Host smart-074f9178-6548-4781-b499-6c9a12e394fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714543356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1714543356
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3960307949
Short name T48
Test name
Test status
Simulation time 4306941065 ps
CPU time 11.6 seconds
Started May 30 03:11:10 PM PDT 24
Finished May 30 03:11:23 PM PDT 24
Peak memory 201948 kb
Host smart-ab11374a-2304-4c69-a11b-41ff74f2f4e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960307949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3960307949
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1937468298
Short name T849
Test name
Test status
Simulation time 559730091 ps
CPU time 1.38 seconds
Started May 30 03:12:20 PM PDT 24
Finished May 30 03:12:22 PM PDT 24
Peak memory 201772 kb
Host smart-65e622a8-db99-4009-80fa-295d4cb8d89c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937468298 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1937468298
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1426101022
Short name T102
Test name
Test status
Simulation time 498608643 ps
CPU time 1.03 seconds
Started May 30 03:12:16 PM PDT 24
Finished May 30 03:12:18 PM PDT 24
Peak memory 201720 kb
Host smart-3275a991-8a02-4d5c-ab70-fd0b484d2786
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426101022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1426101022
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3264493380
Short name T812
Test name
Test status
Simulation time 404236202 ps
CPU time 0.86 seconds
Started May 30 03:12:13 PM PDT 24
Finished May 30 03:12:16 PM PDT 24
Peak memory 201700 kb
Host smart-9f69c6c3-a937-4055-8ca6-59f89ef88f60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264493380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3264493380
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2433311298
Short name T43
Test name
Test status
Simulation time 4924475822 ps
CPU time 6.4 seconds
Started May 30 03:12:14 PM PDT 24
Finished May 30 03:12:22 PM PDT 24
Peak memory 202036 kb
Host smart-ee2cfcce-a325-4ce2-8aa2-549c236cdb58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433311298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2433311298
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4103539911
Short name T56
Test name
Test status
Simulation time 704030869 ps
CPU time 1.89 seconds
Started May 30 03:12:14 PM PDT 24
Finished May 30 03:12:18 PM PDT 24
Peak memory 201948 kb
Host smart-c16cb8bd-d74e-4436-a8e4-a912c325c4b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103539911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.4103539911
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3715748930
Short name T49
Test name
Test status
Simulation time 4168617427 ps
CPU time 5.06 seconds
Started May 30 03:12:20 PM PDT 24
Finished May 30 03:12:26 PM PDT 24
Peak memory 201944 kb
Host smart-acc5cb77-d518-4302-89fe-94b1614dcff7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715748930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3715748930
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.4087009040
Short name T907
Test name
Test status
Simulation time 448376184 ps
CPU time 1.47 seconds
Started May 30 03:12:12 PM PDT 24
Finished May 30 03:12:15 PM PDT 24
Peak memory 201752 kb
Host smart-307a4ed4-f2f7-4468-ae1b-203b631275e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087009040 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.4087009040
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2010240601
Short name T97
Test name
Test status
Simulation time 535589510 ps
CPU time 1.03 seconds
Started May 30 03:12:13 PM PDT 24
Finished May 30 03:12:16 PM PDT 24
Peak memory 201704 kb
Host smart-e522fae4-aa2d-4913-80f6-ecba05442797
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010240601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2010240601
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.4030982071
Short name T918
Test name
Test status
Simulation time 413363901 ps
CPU time 1.3 seconds
Started May 30 03:12:15 PM PDT 24
Finished May 30 03:12:18 PM PDT 24
Peak memory 201716 kb
Host smart-0d56ab52-8976-45f6-b4ef-a9eef8b62e01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030982071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.4030982071
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1040755681
Short name T113
Test name
Test status
Simulation time 2270955937 ps
CPU time 4.96 seconds
Started May 30 03:12:13 PM PDT 24
Finished May 30 03:12:20 PM PDT 24
Peak memory 201756 kb
Host smart-909066dd-58d8-4d59-8b5c-2a3345191715
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040755681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1040755681
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.4133976159
Short name T831
Test name
Test status
Simulation time 464064991 ps
CPU time 1.72 seconds
Started May 30 03:12:15 PM PDT 24
Finished May 30 03:12:18 PM PDT 24
Peak memory 202052 kb
Host smart-f1b55cb9-3406-4d95-bac6-2bdf481443a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133976159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.4133976159
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2014280476
Short name T47
Test name
Test status
Simulation time 8160993803 ps
CPU time 7.32 seconds
Started May 30 03:12:20 PM PDT 24
Finished May 30 03:12:28 PM PDT 24
Peak memory 202032 kb
Host smart-4508dfba-b5ff-4240-ae4c-bf1a918f580d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014280476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2014280476
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.672461107
Short name T833
Test name
Test status
Simulation time 462694530 ps
CPU time 1.39 seconds
Started May 30 03:12:24 PM PDT 24
Finished May 30 03:12:26 PM PDT 24
Peak memory 201792 kb
Host smart-8a3606ae-f160-47c4-970d-aa8a83fdd472
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672461107 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.672461107
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.825924981
Short name T106
Test name
Test status
Simulation time 431461720 ps
CPU time 1.78 seconds
Started May 30 03:12:26 PM PDT 24
Finished May 30 03:12:29 PM PDT 24
Peak memory 201712 kb
Host smart-b40f9b72-299f-43fd-b1de-8f34368fe6bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825924981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.825924981
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.615525873
Short name T881
Test name
Test status
Simulation time 401873316 ps
CPU time 1.62 seconds
Started May 30 03:12:26 PM PDT 24
Finished May 30 03:12:29 PM PDT 24
Peak memory 201720 kb
Host smart-b1e1bb45-b3b6-49f0-9ed2-0f9c46da0d58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615525873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.615525873
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.726963312
Short name T903
Test name
Test status
Simulation time 2135686284 ps
CPU time 2.54 seconds
Started May 30 03:12:28 PM PDT 24
Finished May 30 03:12:32 PM PDT 24
Peak memory 201740 kb
Host smart-a36fc7c7-f8f1-4bdb-b88e-5fbb2a0425a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726963312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.726963312
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1068349527
Short name T912
Test name
Test status
Simulation time 512124354 ps
CPU time 1.74 seconds
Started May 30 03:12:28 PM PDT 24
Finished May 30 03:12:32 PM PDT 24
Peak memory 201960 kb
Host smart-4b459467-73b1-4ec3-92ff-537020db0ac3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068349527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1068349527
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3812420679
Short name T908
Test name
Test status
Simulation time 4598528784 ps
CPU time 7.91 seconds
Started May 30 03:12:25 PM PDT 24
Finished May 30 03:12:35 PM PDT 24
Peak memory 201988 kb
Host smart-00661303-2736-4084-ad58-d4acd51fab89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812420679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3812420679
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.4061649175
Short name T67
Test name
Test status
Simulation time 437936111 ps
CPU time 1.88 seconds
Started May 30 03:12:27 PM PDT 24
Finished May 30 03:12:30 PM PDT 24
Peak memory 201748 kb
Host smart-cb213dbb-9935-4568-a65e-c1e2ed2b861b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061649175 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.4061649175
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.267937981
Short name T94
Test name
Test status
Simulation time 482666578 ps
CPU time 1.82 seconds
Started May 30 03:12:27 PM PDT 24
Finished May 30 03:12:30 PM PDT 24
Peak memory 201700 kb
Host smart-34112543-db79-45f0-a879-e7148cc4076c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267937981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.267937981
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2699728401
Short name T805
Test name
Test status
Simulation time 495568278 ps
CPU time 0.96 seconds
Started May 30 03:12:25 PM PDT 24
Finished May 30 03:12:27 PM PDT 24
Peak memory 201692 kb
Host smart-602c813e-999e-4e23-93b6-5a3acdda82c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699728401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2699728401
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2237231976
Short name T112
Test name
Test status
Simulation time 3727008754 ps
CPU time 5.05 seconds
Started May 30 03:12:25 PM PDT 24
Finished May 30 03:12:31 PM PDT 24
Peak memory 202084 kb
Host smart-912ab5b5-adb2-4f04-aa4a-23a449899bfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237231976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2237231976
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3349481786
Short name T877
Test name
Test status
Simulation time 388741709 ps
CPU time 2.99 seconds
Started May 30 03:12:25 PM PDT 24
Finished May 30 03:12:30 PM PDT 24
Peak memory 210156 kb
Host smart-0ad7b1fc-dc88-4740-b8e0-255f2ed36113
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349481786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3349481786
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2247310513
Short name T875
Test name
Test status
Simulation time 8148961346 ps
CPU time 22.73 seconds
Started May 30 03:12:26 PM PDT 24
Finished May 30 03:12:50 PM PDT 24
Peak memory 201988 kb
Host smart-d6a88808-8ba2-43d6-aeb2-615520021122
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247310513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2247310513
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2161903615
Short name T848
Test name
Test status
Simulation time 527757440 ps
CPU time 1.57 seconds
Started May 30 03:12:39 PM PDT 24
Finished May 30 03:12:42 PM PDT 24
Peak memory 201740 kb
Host smart-6f401b46-7986-4e2d-b188-b87db098fdbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161903615 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2161903615
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.392471174
Short name T114
Test name
Test status
Simulation time 427463017 ps
CPU time 0.97 seconds
Started May 30 03:12:27 PM PDT 24
Finished May 30 03:12:30 PM PDT 24
Peak memory 201704 kb
Host smart-0e201d0f-b132-4bd5-942b-53e9d33323a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392471174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.392471174
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2361612158
Short name T860
Test name
Test status
Simulation time 500560246 ps
CPU time 1.23 seconds
Started May 30 03:12:29 PM PDT 24
Finished May 30 03:12:31 PM PDT 24
Peak memory 201648 kb
Host smart-7764ec0e-53a0-45ca-a039-7b3f8f945d30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361612158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2361612158
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3620896119
Short name T867
Test name
Test status
Simulation time 3961458254 ps
CPU time 3.11 seconds
Started May 30 03:12:27 PM PDT 24
Finished May 30 03:12:32 PM PDT 24
Peak memory 202028 kb
Host smart-ca582b72-922e-42fd-b1b7-4f33a4ef2218
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620896119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3620896119
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4262228049
Short name T837
Test name
Test status
Simulation time 573354017 ps
CPU time 2.47 seconds
Started May 30 03:12:27 PM PDT 24
Finished May 30 03:12:31 PM PDT 24
Peak memory 218232 kb
Host smart-94e2b38a-4b28-477a-b83f-960246f58846
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262228049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.4262228049
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.343844397
Short name T869
Test name
Test status
Simulation time 8279090553 ps
CPU time 9.09 seconds
Started May 30 03:12:25 PM PDT 24
Finished May 30 03:12:36 PM PDT 24
Peak memory 201936 kb
Host smart-689481d9-49ac-4560-867f-cce6d67b2497
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343844397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_in
tg_err.343844397
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3082563264
Short name T874
Test name
Test status
Simulation time 554552018 ps
CPU time 1.01 seconds
Started May 30 03:12:40 PM PDT 24
Finished May 30 03:12:43 PM PDT 24
Peak memory 201716 kb
Host smart-0dd07dac-7799-4bd5-8ae8-48c6484154ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082563264 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3082563264
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.103465216
Short name T910
Test name
Test status
Simulation time 473378655 ps
CPU time 1.97 seconds
Started May 30 03:12:40 PM PDT 24
Finished May 30 03:12:44 PM PDT 24
Peak memory 201684 kb
Host smart-31d305da-d92e-4453-93ed-dc2bccec6227
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103465216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.103465216
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3866230531
Short name T868
Test name
Test status
Simulation time 495802012 ps
CPU time 0.72 seconds
Started May 30 03:12:39 PM PDT 24
Finished May 30 03:12:41 PM PDT 24
Peak memory 201668 kb
Host smart-c8445ee0-bb66-4eac-adc5-947aeda9c325
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866230531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3866230531
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2263770819
Short name T919
Test name
Test status
Simulation time 4906832484 ps
CPU time 6.65 seconds
Started May 30 03:12:41 PM PDT 24
Finished May 30 03:12:49 PM PDT 24
Peak memory 202008 kb
Host smart-140958e3-a8a0-4efc-a856-b4bed1346aea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263770819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2263770819
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2159412143
Short name T69
Test name
Test status
Simulation time 967472448 ps
CPU time 3.16 seconds
Started May 30 03:12:40 PM PDT 24
Finished May 30 03:12:45 PM PDT 24
Peak memory 211212 kb
Host smart-07ad0289-fd50-45f6-a824-b50a74acebf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159412143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.2159412143
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.96544748
Short name T897
Test name
Test status
Simulation time 8618682319 ps
CPU time 7.1 seconds
Started May 30 03:12:38 PM PDT 24
Finished May 30 03:12:47 PM PDT 24
Peak memory 202024 kb
Host smart-5b031f4c-f698-4e33-8e90-1dfb3f69cc6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96544748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_int
g_err.96544748
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1996353838
Short name T70
Test name
Test status
Simulation time 399274236 ps
CPU time 1.03 seconds
Started May 30 03:12:38 PM PDT 24
Finished May 30 03:12:41 PM PDT 24
Peak memory 201724 kb
Host smart-0170432e-d4ea-46c2-ac11-08dfc95cd7da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996353838 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1996353838
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1140534814
Short name T855
Test name
Test status
Simulation time 388086624 ps
CPU time 1.62 seconds
Started May 30 03:12:37 PM PDT 24
Finished May 30 03:12:40 PM PDT 24
Peak memory 201736 kb
Host smart-3d9e77c4-f25d-430f-bf2a-3194326cb38d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140534814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1140534814
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.388212265
Short name T900
Test name
Test status
Simulation time 440462730 ps
CPU time 0.85 seconds
Started May 30 03:12:40 PM PDT 24
Finished May 30 03:12:43 PM PDT 24
Peak memory 201720 kb
Host smart-b7d180cf-2512-439a-aa03-292ec55b19ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388212265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.388212265
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1481329915
Short name T891
Test name
Test status
Simulation time 2597532627 ps
CPU time 2.5 seconds
Started May 30 03:12:38 PM PDT 24
Finished May 30 03:12:42 PM PDT 24
Peak memory 201748 kb
Host smart-225ea375-474b-41bb-8d58-b3ca0f261c41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481329915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1481329915
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.559140305
Short name T850
Test name
Test status
Simulation time 432463266 ps
CPU time 2.95 seconds
Started May 30 03:12:39 PM PDT 24
Finished May 30 03:12:43 PM PDT 24
Peak memory 201992 kb
Host smart-59666410-8931-462d-bbce-430d064b2b8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559140305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.559140305
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.233875277
Short name T838
Test name
Test status
Simulation time 8375607406 ps
CPU time 11.78 seconds
Started May 30 03:12:40 PM PDT 24
Finished May 30 03:12:53 PM PDT 24
Peak memory 201984 kb
Host smart-bdc85037-9889-438a-aa9e-5971c9ebaddc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233875277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.233875277
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.4208017876
Short name T911
Test name
Test status
Simulation time 832436795 ps
CPU time 0.97 seconds
Started May 30 03:12:57 PM PDT 24
Finished May 30 03:12:59 PM PDT 24
Peak memory 201780 kb
Host smart-0f1e5587-396f-46e5-a91b-b5356d345c38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208017876 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.4208017876
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3259138062
Short name T100
Test name
Test status
Simulation time 517173862 ps
CPU time 2.07 seconds
Started May 30 03:12:56 PM PDT 24
Finished May 30 03:12:59 PM PDT 24
Peak memory 201692 kb
Host smart-39d2cf72-6808-4d14-9d65-eaf984915cfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259138062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3259138062
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3672408067
Short name T845
Test name
Test status
Simulation time 501786215 ps
CPU time 1.27 seconds
Started May 30 03:12:39 PM PDT 24
Finished May 30 03:12:41 PM PDT 24
Peak memory 201692 kb
Host smart-feb51038-0bec-4048-8ebe-101a401d1f17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672408067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3672408067
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1602869271
Short name T917
Test name
Test status
Simulation time 4104733007 ps
CPU time 3.75 seconds
Started May 30 03:12:56 PM PDT 24
Finished May 30 03:13:01 PM PDT 24
Peak memory 201932 kb
Host smart-ac03b3ba-6201-4fe4-a5c8-987e030cdacd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602869271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1602869271
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.4258186345
Short name T66
Test name
Test status
Simulation time 9019365513 ps
CPU time 11.41 seconds
Started May 30 03:12:41 PM PDT 24
Finished May 30 03:12:54 PM PDT 24
Peak memory 202000 kb
Host smart-09d892d9-e8c5-4c21-9811-ef64daa941dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258186345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.4258186345
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3911455994
Short name T895
Test name
Test status
Simulation time 529525598 ps
CPU time 2.24 seconds
Started May 30 03:12:56 PM PDT 24
Finished May 30 03:12:59 PM PDT 24
Peak memory 201768 kb
Host smart-a0064664-995c-46f5-9ca5-4b9e92e7bc5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911455994 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3911455994
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1485971760
Short name T885
Test name
Test status
Simulation time 426620577 ps
CPU time 0.93 seconds
Started May 30 03:12:56 PM PDT 24
Finished May 30 03:12:58 PM PDT 24
Peak memory 201692 kb
Host smart-2c8b7943-0f94-448f-8a8a-8feb54d664a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485971760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1485971760
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3442110008
Short name T807
Test name
Test status
Simulation time 367822572 ps
CPU time 0.84 seconds
Started May 30 03:12:55 PM PDT 24
Finished May 30 03:12:57 PM PDT 24
Peak memory 201740 kb
Host smart-b620f47b-8f5b-4597-9fd5-9ef0ee7dfd7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442110008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3442110008
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3161106879
Short name T859
Test name
Test status
Simulation time 4583393847 ps
CPU time 5.25 seconds
Started May 30 03:12:56 PM PDT 24
Finished May 30 03:13:02 PM PDT 24
Peak memory 201964 kb
Host smart-ce845582-f169-4536-96ca-8f17eb475a57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161106879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3161106879
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.238390809
Short name T861
Test name
Test status
Simulation time 402575678 ps
CPU time 3.07 seconds
Started May 30 03:12:55 PM PDT 24
Finished May 30 03:13:00 PM PDT 24
Peak memory 210220 kb
Host smart-04a3fa3e-5d01-4b3a-80b7-eaeaaae839d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238390809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.238390809
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2391278548
Short name T72
Test name
Test status
Simulation time 4272332855 ps
CPU time 12.29 seconds
Started May 30 03:12:54 PM PDT 24
Finished May 30 03:13:08 PM PDT 24
Peak memory 201960 kb
Host smart-75cf100c-aed4-47a2-a644-b65f679cba52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391278548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2391278548
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2484569397
Short name T51
Test name
Test status
Simulation time 400566539 ps
CPU time 1.33 seconds
Started May 30 03:12:56 PM PDT 24
Finished May 30 03:12:59 PM PDT 24
Peak memory 201776 kb
Host smart-0b074361-fbd7-440b-9c45-53f1142feadb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484569397 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2484569397
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.926262714
Short name T896
Test name
Test status
Simulation time 544558963 ps
CPU time 1.53 seconds
Started May 30 03:12:54 PM PDT 24
Finished May 30 03:12:57 PM PDT 24
Peak memory 201744 kb
Host smart-cf63ba4e-37bb-44d0-b1c9-67dd3691e6d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926262714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.926262714
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1546103073
Short name T846
Test name
Test status
Simulation time 535895881 ps
CPU time 1.22 seconds
Started May 30 03:12:55 PM PDT 24
Finished May 30 03:12:58 PM PDT 24
Peak memory 201732 kb
Host smart-c237576c-90c5-4c55-8ca3-6357c902f08b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546103073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1546103073
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.385806398
Short name T894
Test name
Test status
Simulation time 3595342501 ps
CPU time 3.7 seconds
Started May 30 03:12:55 PM PDT 24
Finished May 30 03:13:00 PM PDT 24
Peak memory 201944 kb
Host smart-425a1d07-fc89-4d43-b975-4a3dcba39385
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385806398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.385806398
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2071602396
Short name T880
Test name
Test status
Simulation time 714557802 ps
CPU time 3.49 seconds
Started May 30 03:12:55 PM PDT 24
Finished May 30 03:12:59 PM PDT 24
Peak memory 211252 kb
Host smart-50e79bb6-d52c-4a95-b18e-6073993af796
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071602396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2071602396
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1119188245
Short name T101
Test name
Test status
Simulation time 1291529717 ps
CPU time 5.35 seconds
Started May 30 03:11:37 PM PDT 24
Finished May 30 03:11:44 PM PDT 24
Peak memory 201860 kb
Host smart-7bb46a6b-e69e-4db1-98c6-41e8906d916a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119188245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1119188245
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2174630919
Short name T863
Test name
Test status
Simulation time 53007140830 ps
CPU time 62 seconds
Started May 30 03:11:37 PM PDT 24
Finished May 30 03:12:41 PM PDT 24
Peak memory 201976 kb
Host smart-adb745d4-ccc6-444c-a808-993f0caff46a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174630919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2174630919
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.4237052858
Short name T103
Test name
Test status
Simulation time 865593364 ps
CPU time 1.82 seconds
Started May 30 03:11:22 PM PDT 24
Finished May 30 03:11:26 PM PDT 24
Peak memory 201728 kb
Host smart-8fb1f508-205e-4d46-854c-f664d3cb1af7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237052858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.4237052858
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3882130522
Short name T828
Test name
Test status
Simulation time 457803087 ps
CPU time 1.79 seconds
Started May 30 03:11:37 PM PDT 24
Finished May 30 03:11:40 PM PDT 24
Peak memory 201744 kb
Host smart-05501ea7-48c4-4a9d-aa01-39e98b2f97c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882130522 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3882130522
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2710666342
Short name T892
Test name
Test status
Simulation time 503082132 ps
CPU time 1.92 seconds
Started May 30 03:11:23 PM PDT 24
Finished May 30 03:11:26 PM PDT 24
Peak memory 201668 kb
Host smart-dc2257c7-5be2-44d5-b289-2d3c7868a672
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710666342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2710666342
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2096843781
Short name T886
Test name
Test status
Simulation time 378499552 ps
CPU time 1.53 seconds
Started May 30 03:11:22 PM PDT 24
Finished May 30 03:11:25 PM PDT 24
Peak memory 201736 kb
Host smart-5e92acf2-21cd-44c5-a173-831b9092984d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096843781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2096843781
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3965001833
Short name T847
Test name
Test status
Simulation time 2226410620 ps
CPU time 5.7 seconds
Started May 30 03:11:37 PM PDT 24
Finished May 30 03:11:45 PM PDT 24
Peak memory 201772 kb
Host smart-09bae6d1-e98b-4232-858f-e86caf257c87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965001833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3965001833
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.568335940
Short name T64
Test name
Test status
Simulation time 378061430 ps
CPU time 2.71 seconds
Started May 30 03:11:23 PM PDT 24
Finished May 30 03:11:27 PM PDT 24
Peak memory 218224 kb
Host smart-c661574d-5733-42a7-b509-0f8963c1b013
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568335940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.568335940
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3968642800
Short name T827
Test name
Test status
Simulation time 480851804 ps
CPU time 1.81 seconds
Started May 30 03:12:54 PM PDT 24
Finished May 30 03:12:57 PM PDT 24
Peak memory 201668 kb
Host smart-e6c6f003-d13d-4202-84e0-ba333c8cf414
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968642800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3968642800
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2987569301
Short name T916
Test name
Test status
Simulation time 460377447 ps
CPU time 1.8 seconds
Started May 30 03:12:56 PM PDT 24
Finished May 30 03:12:59 PM PDT 24
Peak memory 201728 kb
Host smart-3e39182f-ec17-4f03-b342-962ab7dccd71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987569301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2987569301
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.910781054
Short name T888
Test name
Test status
Simulation time 506070358 ps
CPU time 0.93 seconds
Started May 30 03:12:55 PM PDT 24
Finished May 30 03:12:57 PM PDT 24
Peak memory 201668 kb
Host smart-56b29b1d-38af-453e-90c8-28f15a7499b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910781054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.910781054
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3376864447
Short name T883
Test name
Test status
Simulation time 426755715 ps
CPU time 1.65 seconds
Started May 30 03:12:54 PM PDT 24
Finished May 30 03:12:56 PM PDT 24
Peak memory 201720 kb
Host smart-c8311754-7844-4aaf-8c46-3116e250500d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376864447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3376864447
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1735828608
Short name T865
Test name
Test status
Simulation time 531850778 ps
CPU time 0.84 seconds
Started May 30 03:13:08 PM PDT 24
Finished May 30 03:13:10 PM PDT 24
Peak memory 201676 kb
Host smart-8832e813-4f57-4144-b918-e3857fc1b88c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735828608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1735828608
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3438294895
Short name T803
Test name
Test status
Simulation time 406486444 ps
CPU time 1.65 seconds
Started May 30 03:13:08 PM PDT 24
Finished May 30 03:13:13 PM PDT 24
Peak memory 201676 kb
Host smart-210f49e8-1f75-4892-b892-bf4b868c6af1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438294895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3438294895
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3179215108
Short name T832
Test name
Test status
Simulation time 429736300 ps
CPU time 0.91 seconds
Started May 30 03:13:13 PM PDT 24
Finished May 30 03:13:16 PM PDT 24
Peak memory 201648 kb
Host smart-146d6ce0-88e4-4961-a087-409191ad9027
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179215108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3179215108
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.153308738
Short name T856
Test name
Test status
Simulation time 518331866 ps
CPU time 1.69 seconds
Started May 30 03:13:08 PM PDT 24
Finished May 30 03:13:13 PM PDT 24
Peak memory 201712 kb
Host smart-59e48b41-d109-4b72-bc9d-b6739e40eef5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153308738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.153308738
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2154073286
Short name T839
Test name
Test status
Simulation time 339158578 ps
CPU time 0.82 seconds
Started May 30 03:13:08 PM PDT 24
Finished May 30 03:13:10 PM PDT 24
Peak memory 201724 kb
Host smart-e47716cf-77d2-4e69-86a4-7397ea353032
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154073286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2154073286
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4201277461
Short name T804
Test name
Test status
Simulation time 345370307 ps
CPU time 1.16 seconds
Started May 30 03:13:09 PM PDT 24
Finished May 30 03:13:12 PM PDT 24
Peak memory 201668 kb
Host smart-b64143b4-f52b-4398-99ed-815317329009
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201277461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.4201277461
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3004753552
Short name T104
Test name
Test status
Simulation time 807780336 ps
CPU time 2.88 seconds
Started May 30 03:11:38 PM PDT 24
Finished May 30 03:11:43 PM PDT 24
Peak memory 201912 kb
Host smart-8b4a1150-92b4-41cc-a678-a74a17db9392
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004753552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3004753552
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1548952296
Short name T115
Test name
Test status
Simulation time 819964903 ps
CPU time 2.61 seconds
Started May 30 03:11:37 PM PDT 24
Finished May 30 03:11:41 PM PDT 24
Peak memory 201724 kb
Host smart-0d24e247-2a05-479b-b479-b3c8452b0fa1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548952296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1548952296
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1147303371
Short name T893
Test name
Test status
Simulation time 440385860 ps
CPU time 1.09 seconds
Started May 30 03:11:38 PM PDT 24
Finished May 30 03:11:41 PM PDT 24
Peak memory 201756 kb
Host smart-f6b62f7f-f197-4e6e-95a1-a690245ef636
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147303371 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1147303371
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3684509714
Short name T890
Test name
Test status
Simulation time 534068765 ps
CPU time 1.91 seconds
Started May 30 03:11:37 PM PDT 24
Finished May 30 03:11:41 PM PDT 24
Peak memory 201696 kb
Host smart-809c4745-28e7-4d33-a181-8a6c930d3402
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684509714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3684509714
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4035656657
Short name T840
Test name
Test status
Simulation time 557629594 ps
CPU time 0.89 seconds
Started May 30 03:11:37 PM PDT 24
Finished May 30 03:11:39 PM PDT 24
Peak memory 201736 kb
Host smart-d582964c-243e-4b3b-a3a5-814125f44aba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035656657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.4035656657
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.17636705
Short name T841
Test name
Test status
Simulation time 2169419072 ps
CPU time 6.44 seconds
Started May 30 03:11:37 PM PDT 24
Finished May 30 03:11:45 PM PDT 24
Peak memory 201792 kb
Host smart-0a2d9c17-c804-43c6-b3ea-61453be8276d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17636705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctr
l_same_csr_outstanding.17636705
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3542795966
Short name T843
Test name
Test status
Simulation time 821586118 ps
CPU time 2.41 seconds
Started May 30 03:11:36 PM PDT 24
Finished May 30 03:11:40 PM PDT 24
Peak memory 202036 kb
Host smart-984cfc38-9124-45c1-8902-eeae6bb97718
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542795966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3542795966
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.142664617
Short name T862
Test name
Test status
Simulation time 4449092906 ps
CPU time 11.67 seconds
Started May 30 03:11:38 PM PDT 24
Finished May 30 03:11:51 PM PDT 24
Peak memory 202084 kb
Host smart-d4653a84-adb5-4f36-8fe8-5647a42a9943
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142664617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.142664617
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3639686697
Short name T887
Test name
Test status
Simulation time 390548952 ps
CPU time 0.96 seconds
Started May 30 03:13:07 PM PDT 24
Finished May 30 03:13:09 PM PDT 24
Peak memory 201700 kb
Host smart-f6d54958-a2e0-45a7-a4ee-9955a80c9345
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639686697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3639686697
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1617549208
Short name T811
Test name
Test status
Simulation time 419664447 ps
CPU time 1.24 seconds
Started May 30 03:13:08 PM PDT 24
Finished May 30 03:13:12 PM PDT 24
Peak memory 201676 kb
Host smart-e9d93adb-410e-4b33-9659-52960faf9541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617549208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1617549208
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1100895670
Short name T816
Test name
Test status
Simulation time 348754672 ps
CPU time 0.77 seconds
Started May 30 03:13:07 PM PDT 24
Finished May 30 03:13:09 PM PDT 24
Peak memory 201728 kb
Host smart-200684fa-5138-48d2-8031-81b920261248
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100895670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1100895670
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.542419600
Short name T905
Test name
Test status
Simulation time 481499796 ps
CPU time 2.02 seconds
Started May 30 03:13:08 PM PDT 24
Finished May 30 03:13:12 PM PDT 24
Peak memory 201748 kb
Host smart-36da66af-c50b-4181-ac00-51897e7b3cc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542419600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.542419600
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1112797356
Short name T882
Test name
Test status
Simulation time 530274716 ps
CPU time 1.24 seconds
Started May 30 03:13:09 PM PDT 24
Finished May 30 03:13:13 PM PDT 24
Peak memory 201704 kb
Host smart-54b0a663-75cf-408a-b846-486a6b4ddc25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112797356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1112797356
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.450463404
Short name T815
Test name
Test status
Simulation time 382800186 ps
CPU time 0.85 seconds
Started May 30 03:13:09 PM PDT 24
Finished May 30 03:13:13 PM PDT 24
Peak memory 201716 kb
Host smart-57f151e3-6811-4917-affc-63d093bd72d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450463404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.450463404
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.4275478028
Short name T809
Test name
Test status
Simulation time 282205927 ps
CPU time 1.22 seconds
Started May 30 03:13:10 PM PDT 24
Finished May 30 03:13:14 PM PDT 24
Peak memory 201696 kb
Host smart-b2547e25-de85-40fd-8647-8f4c036238dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275478028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.4275478028
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1949139890
Short name T872
Test name
Test status
Simulation time 332381245 ps
CPU time 0.8 seconds
Started May 30 03:13:10 PM PDT 24
Finished May 30 03:13:14 PM PDT 24
Peak memory 201720 kb
Host smart-667ee072-750f-47be-8081-9d98a9fd5749
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949139890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1949139890
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3359193337
Short name T902
Test name
Test status
Simulation time 417319348 ps
CPU time 0.85 seconds
Started May 30 03:13:09 PM PDT 24
Finished May 30 03:13:13 PM PDT 24
Peak memory 201688 kb
Host smart-cd333c91-e352-4ce7-9b1b-c0e3d8bde7f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359193337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3359193337
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.934489552
Short name T810
Test name
Test status
Simulation time 397876862 ps
CPU time 1.58 seconds
Started May 30 03:13:09 PM PDT 24
Finished May 30 03:13:13 PM PDT 24
Peak memory 201676 kb
Host smart-dfca9a06-ea6a-4c52-9c47-73d25a58a83e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934489552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.934489552
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1053675555
Short name T817
Test name
Test status
Simulation time 846885016 ps
CPU time 3.44 seconds
Started May 30 03:11:48 PM PDT 24
Finished May 30 03:11:52 PM PDT 24
Peak memory 201936 kb
Host smart-e50ea12d-fdf5-4adc-a29e-ba6fe43282d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053675555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1053675555
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2131257834
Short name T105
Test name
Test status
Simulation time 46816405739 ps
CPU time 95.56 seconds
Started May 30 03:11:50 PM PDT 24
Finished May 30 03:13:27 PM PDT 24
Peak memory 201920 kb
Host smart-668c4c81-59f3-4526-a474-cd214282340c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131257834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2131257834
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2615494176
Short name T96
Test name
Test status
Simulation time 860163361 ps
CPU time 2.67 seconds
Started May 30 03:11:48 PM PDT 24
Finished May 30 03:11:52 PM PDT 24
Peak memory 201712 kb
Host smart-f2ce87de-5ff6-4ee0-a251-dedcb9e8ea4e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615494176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2615494176
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1802673656
Short name T873
Test name
Test status
Simulation time 421596382 ps
CPU time 1.25 seconds
Started May 30 03:11:50 PM PDT 24
Finished May 30 03:11:52 PM PDT 24
Peak memory 201780 kb
Host smart-8b78ae5a-05f4-4db5-b4cd-e2de6ae06b4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802673656 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1802673656
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.582569921
Short name T909
Test name
Test status
Simulation time 500926851 ps
CPU time 1.1 seconds
Started May 30 03:11:49 PM PDT 24
Finished May 30 03:11:51 PM PDT 24
Peak memory 201700 kb
Host smart-3bed202c-618c-4e51-834a-9fb3baa3d049
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582569921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.582569921
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2615870667
Short name T876
Test name
Test status
Simulation time 379609422 ps
CPU time 1.6 seconds
Started May 30 03:11:48 PM PDT 24
Finished May 30 03:11:51 PM PDT 24
Peak memory 201756 kb
Host smart-54c30b3c-3859-4348-86db-a55a7eb44234
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615870667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2615870667
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1964206275
Short name T906
Test name
Test status
Simulation time 5261434281 ps
CPU time 7.25 seconds
Started May 30 03:11:50 PM PDT 24
Finished May 30 03:11:59 PM PDT 24
Peak memory 202040 kb
Host smart-53cad3e2-7244-4ea1-b178-f9d2ef2c1d00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964206275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1964206275
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2816321956
Short name T866
Test name
Test status
Simulation time 585333259 ps
CPU time 2.63 seconds
Started May 30 03:11:48 PM PDT 24
Finished May 30 03:11:52 PM PDT 24
Peak memory 202048 kb
Host smart-4ec8490c-0713-4679-b345-07938469e283
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816321956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2816321956
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.4237095605
Short name T71
Test name
Test status
Simulation time 4329728683 ps
CPU time 4.14 seconds
Started May 30 03:11:50 PM PDT 24
Finished May 30 03:11:56 PM PDT 24
Peak memory 202000 kb
Host smart-291706c4-5085-4284-bb42-1c8b4736d8f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237095605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.4237095605
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3267121053
Short name T819
Test name
Test status
Simulation time 449419375 ps
CPU time 1.15 seconds
Started May 30 03:13:09 PM PDT 24
Finished May 30 03:13:13 PM PDT 24
Peak memory 201784 kb
Host smart-d6e3ae20-51bb-4cba-b100-58df37e37021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267121053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3267121053
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2350929353
Short name T813
Test name
Test status
Simulation time 417061360 ps
CPU time 1.09 seconds
Started May 30 03:13:10 PM PDT 24
Finished May 30 03:13:14 PM PDT 24
Peak memory 201728 kb
Host smart-af7d612b-57e8-4493-9c04-298330e685c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350929353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2350929353
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.724518029
Short name T806
Test name
Test status
Simulation time 392516504 ps
CPU time 1.49 seconds
Started May 30 03:13:12 PM PDT 24
Finished May 30 03:13:16 PM PDT 24
Peak memory 201748 kb
Host smart-d86059ea-a592-468e-99b4-0fd206381813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724518029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.724518029
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3202694958
Short name T842
Test name
Test status
Simulation time 442329908 ps
CPU time 1.57 seconds
Started May 30 03:13:11 PM PDT 24
Finished May 30 03:13:15 PM PDT 24
Peak memory 201736 kb
Host smart-50aaaa02-ad1a-44cf-9e15-a17465572f5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202694958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3202694958
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.184254855
Short name T915
Test name
Test status
Simulation time 466575313 ps
CPU time 1.72 seconds
Started May 30 03:13:11 PM PDT 24
Finished May 30 03:13:16 PM PDT 24
Peak memory 201704 kb
Host smart-ec750cb0-e8ef-41e7-9fed-89ef7ed60299
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184254855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.184254855
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1958369353
Short name T820
Test name
Test status
Simulation time 359091476 ps
CPU time 0.73 seconds
Started May 30 03:13:11 PM PDT 24
Finished May 30 03:13:14 PM PDT 24
Peak memory 201724 kb
Host smart-7d3f8bc0-c8e2-4678-be39-00c3c51fe91b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958369353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1958369353
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3543863619
Short name T852
Test name
Test status
Simulation time 413586433 ps
CPU time 1.08 seconds
Started May 30 03:13:11 PM PDT 24
Finished May 30 03:13:15 PM PDT 24
Peak memory 201704 kb
Host smart-8ae0581c-9a01-4f44-9bd8-40991abcdad8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543863619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3543863619
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3418463034
Short name T844
Test name
Test status
Simulation time 503580641 ps
CPU time 1.87 seconds
Started May 30 03:13:11 PM PDT 24
Finished May 30 03:13:16 PM PDT 24
Peak memory 201696 kb
Host smart-6dccecc0-208c-4b2f-9b71-31a9126eb615
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418463034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3418463034
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2215269535
Short name T826
Test name
Test status
Simulation time 490890591 ps
CPU time 1.91 seconds
Started May 30 03:13:11 PM PDT 24
Finished May 30 03:13:15 PM PDT 24
Peak memory 201680 kb
Host smart-4b1f083f-f1e4-4ac3-9ca3-a1395dd756c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215269535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2215269535
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2034775457
Short name T818
Test name
Test status
Simulation time 397761983 ps
CPU time 1.22 seconds
Started May 30 03:13:10 PM PDT 24
Finished May 30 03:13:14 PM PDT 24
Peak memory 201724 kb
Host smart-2a0a4aa6-276e-4669-b3fe-44f3be2f9d60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034775457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2034775457
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.563172913
Short name T913
Test name
Test status
Simulation time 562622373 ps
CPU time 1.32 seconds
Started May 30 03:12:00 PM PDT 24
Finished May 30 03:12:03 PM PDT 24
Peak memory 201780 kb
Host smart-d5d6866d-d771-4f11-9479-a173f152e113
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563172913 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.563172913
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1494418601
Short name T830
Test name
Test status
Simulation time 446452175 ps
CPU time 1.83 seconds
Started May 30 03:12:02 PM PDT 24
Finished May 30 03:12:06 PM PDT 24
Peak memory 201724 kb
Host smart-0533f922-fa18-4d2b-af9b-327c59847df7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494418601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1494418601
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.78861092
Short name T889
Test name
Test status
Simulation time 441445289 ps
CPU time 1.66 seconds
Started May 30 03:11:51 PM PDT 24
Finished May 30 03:11:54 PM PDT 24
Peak memory 201708 kb
Host smart-dd7c05cb-255e-4636-9b3d-b245161bfed3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78861092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.78861092
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2601433697
Short name T110
Test name
Test status
Simulation time 3011193973 ps
CPU time 2.21 seconds
Started May 30 03:12:03 PM PDT 24
Finished May 30 03:12:07 PM PDT 24
Peak memory 201812 kb
Host smart-4d616ccb-5ff9-49be-8e37-e8fb83a54de5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601433697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2601433697
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1465393772
Short name T871
Test name
Test status
Simulation time 362698117 ps
CPU time 2.19 seconds
Started May 30 03:11:50 PM PDT 24
Finished May 30 03:11:54 PM PDT 24
Peak memory 201988 kb
Host smart-6a64badf-c090-4235-94c9-a8928a3de380
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465393772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1465393772
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3528270655
Short name T319
Test name
Test status
Simulation time 8849519250 ps
CPU time 8.12 seconds
Started May 30 03:11:49 PM PDT 24
Finished May 30 03:11:59 PM PDT 24
Peak memory 202008 kb
Host smart-f694c73d-dc97-4132-b0d0-d4e780782351
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528270655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3528270655
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3182596934
Short name T857
Test name
Test status
Simulation time 638722844 ps
CPU time 1.47 seconds
Started May 30 03:12:01 PM PDT 24
Finished May 30 03:12:04 PM PDT 24
Peak memory 210196 kb
Host smart-5ac68b78-0624-438b-b4cd-eeb87ea8408b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182596934 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3182596934
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.753660413
Short name T884
Test name
Test status
Simulation time 482360880 ps
CPU time 1.75 seconds
Started May 30 03:12:02 PM PDT 24
Finished May 30 03:12:06 PM PDT 24
Peak memory 201720 kb
Host smart-c30bf0f2-f4ac-4479-93b3-6cb084c6404e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753660413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.753660413
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2557138182
Short name T814
Test name
Test status
Simulation time 484644017 ps
CPU time 1.25 seconds
Started May 30 03:12:00 PM PDT 24
Finished May 30 03:12:02 PM PDT 24
Peak memory 201708 kb
Host smart-78c4c07b-7ead-41bd-8808-3e1e420e6b9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557138182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2557138182
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3605810288
Short name T823
Test name
Test status
Simulation time 4999959736 ps
CPU time 15.93 seconds
Started May 30 03:12:01 PM PDT 24
Finished May 30 03:12:19 PM PDT 24
Peak memory 201960 kb
Host smart-8ca711c0-35db-4557-be47-264dc6064340
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605810288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3605810288
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2731745086
Short name T58
Test name
Test status
Simulation time 474004330 ps
CPU time 2.53 seconds
Started May 30 03:12:01 PM PDT 24
Finished May 30 03:12:06 PM PDT 24
Peak memory 202020 kb
Host smart-4f0decf8-a003-4266-a907-0b9c09583f76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731745086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2731745086
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1840652905
Short name T65
Test name
Test status
Simulation time 8157554857 ps
CPU time 20.74 seconds
Started May 30 03:12:03 PM PDT 24
Finished May 30 03:12:26 PM PDT 24
Peak memory 201948 kb
Host smart-125b15e0-3433-4e8d-8c8e-42890d849e95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840652905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1840652905
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1739998078
Short name T914
Test name
Test status
Simulation time 572253380 ps
CPU time 2.21 seconds
Started May 30 03:12:01 PM PDT 24
Finished May 30 03:12:06 PM PDT 24
Peak memory 201736 kb
Host smart-5782d3ed-3df5-4e1b-96ee-9619455ba1d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739998078 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.1739998078
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3822655819
Short name T108
Test name
Test status
Simulation time 423985412 ps
CPU time 0.89 seconds
Started May 30 03:12:00 PM PDT 24
Finished May 30 03:12:03 PM PDT 24
Peak memory 201696 kb
Host smart-c8aa509b-7c3e-437e-9369-02d8f2164cfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822655819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3822655819
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3075384334
Short name T808
Test name
Test status
Simulation time 331817962 ps
CPU time 1.02 seconds
Started May 30 03:12:02 PM PDT 24
Finished May 30 03:12:05 PM PDT 24
Peak memory 201724 kb
Host smart-4d52a342-ec0f-4cf2-a505-51a048f91640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075384334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3075384334
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.363704636
Short name T109
Test name
Test status
Simulation time 2044577406 ps
CPU time 10.15 seconds
Started May 30 03:12:02 PM PDT 24
Finished May 30 03:12:14 PM PDT 24
Peak memory 201676 kb
Host smart-b91da35d-d098-40b7-aec0-8f3defae203a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363704636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.363704636
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.168353406
Short name T853
Test name
Test status
Simulation time 534744084 ps
CPU time 3.47 seconds
Started May 30 03:12:01 PM PDT 24
Finished May 30 03:12:06 PM PDT 24
Peak memory 210160 kb
Host smart-576870a9-9f08-4bc2-a3d8-6c203a8d5207
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168353406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.168353406
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.73694721
Short name T870
Test name
Test status
Simulation time 4535388993 ps
CPU time 13.1 seconds
Started May 30 03:12:00 PM PDT 24
Finished May 30 03:12:15 PM PDT 24
Peak memory 201988 kb
Host smart-36f2c0bc-6494-41cb-8fb4-27ff8ccf67a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73694721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_intg
_err.73694721
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3717101965
Short name T59
Test name
Test status
Simulation time 468796409 ps
CPU time 1.37 seconds
Started May 30 03:12:16 PM PDT 24
Finished May 30 03:12:19 PM PDT 24
Peak memory 201972 kb
Host smart-3e6b7031-662d-4077-b82b-f9118768c653
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717101965 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3717101965
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.260293497
Short name T878
Test name
Test status
Simulation time 421275294 ps
CPU time 1.07 seconds
Started May 30 03:12:02 PM PDT 24
Finished May 30 03:12:05 PM PDT 24
Peak memory 201744 kb
Host smart-28aee29e-f41a-4f17-bddc-5f94601f1687
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260293497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.260293497
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2946847638
Short name T879
Test name
Test status
Simulation time 471432939 ps
CPU time 1.79 seconds
Started May 30 03:12:03 PM PDT 24
Finished May 30 03:12:07 PM PDT 24
Peak memory 201728 kb
Host smart-3f0d6ae5-3cfc-46f3-b8fa-62d26aaea371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946847638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2946847638
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2400319465
Short name T829
Test name
Test status
Simulation time 2097201611 ps
CPU time 2 seconds
Started May 30 03:12:02 PM PDT 24
Finished May 30 03:12:06 PM PDT 24
Peak memory 201740 kb
Host smart-f70c430f-7e54-49bf-9e8f-40782a96f81d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400319465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2400319465
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1045133086
Short name T864
Test name
Test status
Simulation time 605829684 ps
CPU time 3.6 seconds
Started May 30 03:12:03 PM PDT 24
Finished May 30 03:12:08 PM PDT 24
Peak memory 201960 kb
Host smart-0165d568-c4aa-407e-8d60-d30d275717fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045133086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1045133086
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1242697186
Short name T68
Test name
Test status
Simulation time 8545487664 ps
CPU time 3.76 seconds
Started May 30 03:12:02 PM PDT 24
Finished May 30 03:12:08 PM PDT 24
Peak memory 201912 kb
Host smart-c1421611-ef92-4bc6-8fb1-bd2321e69b38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242697186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1242697186
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1709671885
Short name T63
Test name
Test status
Simulation time 601773522 ps
CPU time 1.35 seconds
Started May 30 03:12:16 PM PDT 24
Finished May 30 03:12:19 PM PDT 24
Peak memory 201732 kb
Host smart-b155b18d-ea31-4b1f-89af-57316abc53cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709671885 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1709671885
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3606847630
Short name T99
Test name
Test status
Simulation time 496328935 ps
CPU time 1.97 seconds
Started May 30 03:12:13 PM PDT 24
Finished May 30 03:12:16 PM PDT 24
Peak memory 201736 kb
Host smart-b592734b-1734-405f-a02e-afe8e5e4576b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606847630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3606847630
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.720200342
Short name T821
Test name
Test status
Simulation time 338088319 ps
CPU time 0.81 seconds
Started May 30 03:12:13 PM PDT 24
Finished May 30 03:12:15 PM PDT 24
Peak memory 201704 kb
Host smart-67041c62-96bd-4f76-8b4d-145e48cc0d80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720200342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.720200342
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2053807213
Short name T851
Test name
Test status
Simulation time 5628984948 ps
CPU time 22.86 seconds
Started May 30 03:12:16 PM PDT 24
Finished May 30 03:12:41 PM PDT 24
Peak memory 201904 kb
Host smart-1bf84e2d-c734-484b-8d42-781084b79d39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053807213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2053807213
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1979858638
Short name T898
Test name
Test status
Simulation time 549870091 ps
CPU time 3.3 seconds
Started May 30 03:12:20 PM PDT 24
Finished May 30 03:12:24 PM PDT 24
Peak memory 218276 kb
Host smart-59108d31-f5d9-4c8e-bae1-afcab66d0947
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979858638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1979858638
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2906955146
Short name T858
Test name
Test status
Simulation time 8584830999 ps
CPU time 7.86 seconds
Started May 30 03:12:13 PM PDT 24
Finished May 30 03:12:22 PM PDT 24
Peak memory 202008 kb
Host smart-a3c1d982-719d-4738-9a12-d4edeb58ddbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906955146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2906955146
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1762575768
Short name T379
Test name
Test status
Simulation time 532137430 ps
CPU time 0.71 seconds
Started May 30 03:14:28 PM PDT 24
Finished May 30 03:14:29 PM PDT 24
Peak memory 201484 kb
Host smart-fb7704df-10d9-4485-aeb2-c96c3e9408a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762575768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1762575768
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.680411368
Short name T491
Test name
Test status
Simulation time 161907812167 ps
CPU time 377.97 seconds
Started May 30 03:14:26 PM PDT 24
Finished May 30 03:20:45 PM PDT 24
Peak memory 201792 kb
Host smart-8d5e5458-ca06-49fc-a9b9-0fdafa8f2b04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680411368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.680411368
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3867456915
Short name T751
Test name
Test status
Simulation time 187312733536 ps
CPU time 408.9 seconds
Started May 30 03:14:25 PM PDT 24
Finished May 30 03:21:15 PM PDT 24
Peak memory 201872 kb
Host smart-f9797497-8054-41e6-98f6-f2a56c1303b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867456915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3867456915
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1972641453
Short name T758
Test name
Test status
Simulation time 167362462654 ps
CPU time 205.83 seconds
Started May 30 03:14:18 PM PDT 24
Finished May 30 03:17:45 PM PDT 24
Peak memory 201860 kb
Host smart-b8f33e62-356c-483a-8d43-30d1466219a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972641453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1972641453
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1950359805
Short name T673
Test name
Test status
Simulation time 326302166152 ps
CPU time 225.38 seconds
Started May 30 03:14:16 PM PDT 24
Finished May 30 03:18:03 PM PDT 24
Peak memory 201756 kb
Host smart-215c165d-d276-4204-ae66-f86d9789ab3d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950359805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1950359805
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1058848183
Short name T737
Test name
Test status
Simulation time 163525987558 ps
CPU time 412.05 seconds
Started May 30 03:14:15 PM PDT 24
Finished May 30 03:21:08 PM PDT 24
Peak memory 201776 kb
Host smart-e80e40e0-d01b-42a0-a319-9d5f974ec38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058848183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1058848183
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3187729379
Short name T676
Test name
Test status
Simulation time 492091157160 ps
CPU time 298.88 seconds
Started May 30 03:14:18 PM PDT 24
Finished May 30 03:19:19 PM PDT 24
Peak memory 201780 kb
Host smart-8b30f880-2b56-43a3-94d8-52eaf1993ea7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187729379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3187729379
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3717548333
Short name T621
Test name
Test status
Simulation time 207975081856 ps
CPU time 522.31 seconds
Started May 30 03:14:17 PM PDT 24
Finished May 30 03:23:02 PM PDT 24
Peak memory 201788 kb
Host smart-0a84f19f-3830-4a6d-b53f-c52c607ae202
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717548333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3717548333
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1075665153
Short name T647
Test name
Test status
Simulation time 69499329477 ps
CPU time 292.34 seconds
Started May 30 03:14:25 PM PDT 24
Finished May 30 03:19:19 PM PDT 24
Peak memory 202112 kb
Host smart-f4b2fbb0-6ef7-4ca9-9c48-2199f60fd9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075665153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1075665153
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2488673844
Short name T361
Test name
Test status
Simulation time 37032770187 ps
CPU time 47.21 seconds
Started May 30 03:14:28 PM PDT 24
Finished May 30 03:15:17 PM PDT 24
Peak memory 201400 kb
Host smart-f5f8cfe9-35d5-49a4-bc0d-ef8825139ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488673844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2488673844
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3037865178
Short name T502
Test name
Test status
Simulation time 4080519979 ps
CPU time 2.82 seconds
Started May 30 03:14:25 PM PDT 24
Finished May 30 03:14:30 PM PDT 24
Peak memory 201648 kb
Host smart-0644a8ca-dbe0-4cc1-a694-63a8677be3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037865178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3037865178
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.2828778054
Short name T340
Test name
Test status
Simulation time 5665429642 ps
CPU time 12.03 seconds
Started May 30 03:14:20 PM PDT 24
Finished May 30 03:14:34 PM PDT 24
Peak memory 201660 kb
Host smart-5e71db3e-0ae8-4f65-8416-15739eb838d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828778054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2828778054
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.466135927
Short name T760
Test name
Test status
Simulation time 510342052792 ps
CPU time 1192.86 seconds
Started May 30 03:14:33 PM PDT 24
Finished May 30 03:34:27 PM PDT 24
Peak memory 201872 kb
Host smart-3162c53e-f91e-440b-9111-69c36d25790e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466135927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.466135927
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.626006342
Short name T82
Test name
Test status
Simulation time 276808073332 ps
CPU time 72.71 seconds
Started May 30 03:14:26 PM PDT 24
Finished May 30 03:15:40 PM PDT 24
Peak memory 210148 kb
Host smart-681beabd-0202-4251-8263-a91869c0d6dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626006342 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.626006342
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3534318419
Short name T487
Test name
Test status
Simulation time 366945058 ps
CPU time 1.05 seconds
Started May 30 03:14:26 PM PDT 24
Finished May 30 03:14:28 PM PDT 24
Peak memory 201596 kb
Host smart-ec517387-a0b1-4444-b4b9-292a8a7dadcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534318419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3534318419
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.3642861016
Short name T635
Test name
Test status
Simulation time 159627456054 ps
CPU time 46.63 seconds
Started May 30 03:14:32 PM PDT 24
Finished May 30 03:15:20 PM PDT 24
Peak memory 201868 kb
Host smart-ffaaac9e-d75b-4d2b-991f-2205d98f1cc1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642861016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.3642861016
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.872439832
Short name T623
Test name
Test status
Simulation time 532461504550 ps
CPU time 683.91 seconds
Started May 30 03:14:32 PM PDT 24
Finished May 30 03:25:57 PM PDT 24
Peak memory 201748 kb
Host smart-f26b0154-83d6-43fa-9e0d-c76c94c8c06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872439832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.872439832
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.79375928
Short name T156
Test name
Test status
Simulation time 322276425041 ps
CPU time 370.62 seconds
Started May 30 03:14:25 PM PDT 24
Finished May 30 03:20:37 PM PDT 24
Peak memory 201828 kb
Host smart-6aa7f319-9d1e-4c81-9f3e-e133d55a15cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79375928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.79375928
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3507013421
Short name T794
Test name
Test status
Simulation time 486372558192 ps
CPU time 1087.4 seconds
Started May 30 03:14:25 PM PDT 24
Finished May 30 03:32:34 PM PDT 24
Peak memory 201788 kb
Host smart-8cab0a95-61a6-437f-863e-a40288d31470
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507013421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3507013421
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.879642772
Short name T298
Test name
Test status
Simulation time 491735957219 ps
CPU time 1162.25 seconds
Started May 30 03:14:30 PM PDT 24
Finished May 30 03:33:54 PM PDT 24
Peak memory 201800 kb
Host smart-d35c3728-40e1-4ff4-b670-aec066277f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879642772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.879642772
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2272340126
Short name T177
Test name
Test status
Simulation time 334195351506 ps
CPU time 754.89 seconds
Started May 30 03:14:28 PM PDT 24
Finished May 30 03:27:04 PM PDT 24
Peak memory 201528 kb
Host smart-0df003bd-ddeb-4215-b9a9-40f9a934dd06
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272340126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2272340126
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.4101783034
Short name T637
Test name
Test status
Simulation time 212912695608 ps
CPU time 501.09 seconds
Started May 30 03:14:30 PM PDT 24
Finished May 30 03:22:52 PM PDT 24
Peak memory 201820 kb
Host smart-a18d5ac8-298b-44ce-8144-bff2004973f5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101783034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.4101783034
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2015612743
Short name T613
Test name
Test status
Simulation time 68861158501 ps
CPU time 425.98 seconds
Started May 30 03:14:28 PM PDT 24
Finished May 30 03:21:35 PM PDT 24
Peak memory 202104 kb
Host smart-eb8b3073-4b9f-4748-a5b0-910fb79a3649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015612743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2015612743
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1658224165
Short name T632
Test name
Test status
Simulation time 34656331198 ps
CPU time 73.7 seconds
Started May 30 03:14:25 PM PDT 24
Finished May 30 03:15:40 PM PDT 24
Peak memory 201604 kb
Host smart-c41e63d2-58fb-4db9-911c-5c682f4c2e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658224165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1658224165
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3808408401
Short name T797
Test name
Test status
Simulation time 3811266477 ps
CPU time 2.15 seconds
Started May 30 03:14:32 PM PDT 24
Finished May 30 03:14:35 PM PDT 24
Peak memory 201620 kb
Host smart-bf450bc2-f718-4354-9503-775dc4264c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808408401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3808408401
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2444036204
Short name T52
Test name
Test status
Simulation time 8097192862 ps
CPU time 16.48 seconds
Started May 30 03:14:27 PM PDT 24
Finished May 30 03:14:44 PM PDT 24
Peak memory 218524 kb
Host smart-1f0575df-9685-4926-a304-f20d7a7dada1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444036204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2444036204
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1325521926
Short name T446
Test name
Test status
Simulation time 6007814415 ps
CPU time 2.23 seconds
Started May 30 03:14:30 PM PDT 24
Finished May 30 03:14:33 PM PDT 24
Peak memory 201648 kb
Host smart-dd19cd18-be4b-420e-bd7a-8cd7c34124e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325521926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1325521926
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1110682972
Short name T225
Test name
Test status
Simulation time 222335991365 ps
CPU time 33.19 seconds
Started May 30 03:14:33 PM PDT 24
Finished May 30 03:15:07 PM PDT 24
Peak memory 201800 kb
Host smart-d3dd02f7-6826-41a9-9d5d-6b23d3d33a8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110682972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1110682972
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2339984954
Short name T19
Test name
Test status
Simulation time 42218127266 ps
CPU time 51.17 seconds
Started May 30 03:14:30 PM PDT 24
Finished May 30 03:15:22 PM PDT 24
Peak memory 210436 kb
Host smart-7170705e-f035-4c9d-8bd9-96fac2cf7305
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339984954 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2339984954
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1840824248
Short name T513
Test name
Test status
Simulation time 455454199 ps
CPU time 1.72 seconds
Started May 30 03:15:41 PM PDT 24
Finished May 30 03:15:44 PM PDT 24
Peak memory 201512 kb
Host smart-db2eecac-6cdb-4bd6-9ba8-7268848af687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840824248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1840824248
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1964194903
Short name T140
Test name
Test status
Simulation time 355655789912 ps
CPU time 424.76 seconds
Started May 30 03:15:25 PM PDT 24
Finished May 30 03:22:31 PM PDT 24
Peak memory 201868 kb
Host smart-759869a1-4928-44ee-83a8-538cf3633788
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964194903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1964194903
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2089343516
Short name T237
Test name
Test status
Simulation time 169229964729 ps
CPU time 84.41 seconds
Started May 30 03:15:24 PM PDT 24
Finished May 30 03:16:50 PM PDT 24
Peak memory 201816 kb
Host smart-4ebbc90c-f584-43b9-a68a-b62de64babc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089343516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2089343516
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3559688175
Short name T436
Test name
Test status
Simulation time 166166770199 ps
CPU time 101.68 seconds
Started May 30 03:15:15 PM PDT 24
Finished May 30 03:16:58 PM PDT 24
Peak memory 201704 kb
Host smart-132ccfc6-0aa2-4c96-aa14-b0d807f1179f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559688175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3559688175
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.4110372535
Short name T464
Test name
Test status
Simulation time 322980487408 ps
CPU time 227.59 seconds
Started May 30 03:15:25 PM PDT 24
Finished May 30 03:19:14 PM PDT 24
Peak memory 201768 kb
Host smart-a2c0ceac-4431-4b41-93d7-b42f89c83e1f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110372535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.4110372535
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.569259533
Short name T259
Test name
Test status
Simulation time 330785108313 ps
CPU time 795.33 seconds
Started May 30 03:15:11 PM PDT 24
Finished May 30 03:28:28 PM PDT 24
Peak memory 201752 kb
Host smart-429de549-3273-4558-a064-ead698df3a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569259533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.569259533
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.4005666182
Short name T716
Test name
Test status
Simulation time 330417513143 ps
CPU time 219.21 seconds
Started May 30 03:15:10 PM PDT 24
Finished May 30 03:18:51 PM PDT 24
Peak memory 201880 kb
Host smart-0ec55211-2b82-46e8-8095-786894510a40
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005666182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.4005666182
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2947929765
Short name T564
Test name
Test status
Simulation time 602957777571 ps
CPU time 1456.44 seconds
Started May 30 03:15:26 PM PDT 24
Finished May 30 03:39:44 PM PDT 24
Peak memory 201764 kb
Host smart-21436f59-c4fe-4b22-91b6-b2d7ad74c92f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947929765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2947929765
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2025063765
Short name T181
Test name
Test status
Simulation time 72193593643 ps
CPU time 396.29 seconds
Started May 30 03:15:22 PM PDT 24
Finished May 30 03:22:00 PM PDT 24
Peak memory 202072 kb
Host smart-516f5b19-8d3b-415e-9331-289aad2b25bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025063765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2025063765
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.676279518
Short name T501
Test name
Test status
Simulation time 33119948826 ps
CPU time 83.67 seconds
Started May 30 03:15:24 PM PDT 24
Finished May 30 03:16:49 PM PDT 24
Peak memory 201616 kb
Host smart-e8cbc6db-e1f5-4d4d-931b-45995dcd05c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676279518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.676279518
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.4006570010
Short name T392
Test name
Test status
Simulation time 4349002302 ps
CPU time 3.34 seconds
Started May 30 03:15:23 PM PDT 24
Finished May 30 03:15:28 PM PDT 24
Peak memory 201628 kb
Host smart-c43169c3-0f6c-4e7b-8f9f-425d857551d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006570010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.4006570010
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1974446479
Short name T599
Test name
Test status
Simulation time 5945659259 ps
CPU time 15.62 seconds
Started May 30 03:15:15 PM PDT 24
Finished May 30 03:15:32 PM PDT 24
Peak memory 201564 kb
Host smart-cc65d3f3-d82e-4d76-9414-0a4f99e8b75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974446479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1974446479
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1665845553
Short name T486
Test name
Test status
Simulation time 772992991748 ps
CPU time 2476.11 seconds
Started May 30 03:15:38 PM PDT 24
Finished May 30 03:56:56 PM PDT 24
Peak memory 202116 kb
Host smart-d0db1b82-693b-4143-b29b-7aff120c9ae2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665845553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1665845553
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.192368610
Short name T627
Test name
Test status
Simulation time 95817701989 ps
CPU time 40.62 seconds
Started May 30 03:15:26 PM PDT 24
Finished May 30 03:16:08 PM PDT 24
Peak memory 210088 kb
Host smart-de1decae-95e5-4e09-abd2-2b0969fe7238
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192368610 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.192368610
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.330761650
Short name T387
Test name
Test status
Simulation time 327438903 ps
CPU time 0.77 seconds
Started May 30 03:15:41 PM PDT 24
Finished May 30 03:15:43 PM PDT 24
Peak memory 201508 kb
Host smart-76f9b74b-5325-48f6-b0db-a349833df3e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330761650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.330761650
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2040115861
Short name T610
Test name
Test status
Simulation time 349666357785 ps
CPU time 382.62 seconds
Started May 30 03:15:35 PM PDT 24
Finished May 30 03:21:59 PM PDT 24
Peak memory 201824 kb
Host smart-b9f82027-3ee7-44cc-8c13-62c997f6e53c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040115861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2040115861
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1686747497
Short name T158
Test name
Test status
Simulation time 164783076859 ps
CPU time 398.04 seconds
Started May 30 03:15:41 PM PDT 24
Finished May 30 03:22:20 PM PDT 24
Peak memory 201868 kb
Host smart-f692270a-da81-48db-80d3-8ba8e7b9d943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686747497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1686747497
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1994602300
Short name T774
Test name
Test status
Simulation time 480154472130 ps
CPU time 1118.77 seconds
Started May 30 03:15:38 PM PDT 24
Finished May 30 03:34:18 PM PDT 24
Peak memory 201740 kb
Host smart-d958c100-ff81-434f-b611-20466aca2c11
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994602300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1994602300
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.714055456
Short name T780
Test name
Test status
Simulation time 488659487133 ps
CPU time 336.5 seconds
Started May 30 03:15:42 PM PDT 24
Finished May 30 03:21:20 PM PDT 24
Peak memory 201868 kb
Host smart-1b1494dc-d5f1-4558-8a08-5a6d08bc3cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714055456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.714055456
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3642789674
Short name T801
Test name
Test status
Simulation time 158842518542 ps
CPU time 342.76 seconds
Started May 30 03:15:40 PM PDT 24
Finished May 30 03:21:25 PM PDT 24
Peak memory 201756 kb
Host smart-34802403-70a5-4b0b-856e-f47db8302398
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642789674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.3642789674
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3093379891
Short name T315
Test name
Test status
Simulation time 185202473642 ps
CPU time 461.57 seconds
Started May 30 03:15:41 PM PDT 24
Finished May 30 03:23:24 PM PDT 24
Peak memory 201868 kb
Host smart-bb1389e6-b2e1-4170-b8ae-8bb68efd243c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093379891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3093379891
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1783775127
Short name T775
Test name
Test status
Simulation time 597304616066 ps
CPU time 1373.28 seconds
Started May 30 03:15:40 PM PDT 24
Finished May 30 03:38:35 PM PDT 24
Peak memory 201832 kb
Host smart-6d669635-2699-4988-bf92-94b4f4a1d72b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783775127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1783775127
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2660309461
Short name T636
Test name
Test status
Simulation time 134939797583 ps
CPU time 459.06 seconds
Started May 30 03:15:39 PM PDT 24
Finished May 30 03:23:19 PM PDT 24
Peak memory 202184 kb
Host smart-8f2fd4b4-17c1-446d-914c-d5255751f83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660309461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2660309461
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3443018630
Short name T655
Test name
Test status
Simulation time 38357221177 ps
CPU time 24.01 seconds
Started May 30 03:15:40 PM PDT 24
Finished May 30 03:16:06 PM PDT 24
Peak memory 201636 kb
Host smart-bd3f5975-8f7d-4554-9a03-5027eb9b6bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443018630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3443018630
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1774134450
Short name T675
Test name
Test status
Simulation time 3920963093 ps
CPU time 1.66 seconds
Started May 30 03:15:38 PM PDT 24
Finished May 30 03:15:42 PM PDT 24
Peak memory 201604 kb
Host smart-b02fe8aa-c918-42f1-807c-20adde1656f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774134450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1774134450
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3715644683
Short name T577
Test name
Test status
Simulation time 5829142518 ps
CPU time 4.31 seconds
Started May 30 03:15:39 PM PDT 24
Finished May 30 03:15:45 PM PDT 24
Peak memory 201668 kb
Host smart-d8dfa851-9ab7-433d-928d-bff9c72d5413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715644683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3715644683
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3950895335
Short name T38
Test name
Test status
Simulation time 581802470822 ps
CPU time 1569.8 seconds
Started May 30 03:15:40 PM PDT 24
Finished May 30 03:41:52 PM PDT 24
Peak memory 202112 kb
Host smart-7927fc88-09c5-4813-9b04-ef77604ce516
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950895335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3950895335
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2472025666
Short name T17
Test name
Test status
Simulation time 101007115266 ps
CPU time 313.14 seconds
Started May 30 03:15:42 PM PDT 24
Finished May 30 03:20:56 PM PDT 24
Peak memory 210404 kb
Host smart-4afb8cf3-e57d-4e05-b07e-c483da79cf2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472025666 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2472025666
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3944860157
Short name T649
Test name
Test status
Simulation time 410173292 ps
CPU time 1.07 seconds
Started May 30 03:15:56 PM PDT 24
Finished May 30 03:15:58 PM PDT 24
Peak memory 201476 kb
Host smart-c0ea262c-051a-4ac0-9992-7c7589a2a2c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944860157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3944860157
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1774373200
Short name T287
Test name
Test status
Simulation time 200341467102 ps
CPU time 136.63 seconds
Started May 30 03:15:46 PM PDT 24
Finished May 30 03:18:04 PM PDT 24
Peak memory 201824 kb
Host smart-6e27e63d-4125-4d5b-b91d-355204413e18
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774373200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1774373200
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2533810307
Short name T211
Test name
Test status
Simulation time 163470561330 ps
CPU time 390.52 seconds
Started May 30 03:15:55 PM PDT 24
Finished May 30 03:22:27 PM PDT 24
Peak memory 201876 kb
Host smart-ada7bdd7-6fb4-41b6-8326-bfada1c157c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533810307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2533810307
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3884802393
Short name T540
Test name
Test status
Simulation time 160645499145 ps
CPU time 340.25 seconds
Started May 30 03:15:51 PM PDT 24
Finished May 30 03:21:33 PM PDT 24
Peak memory 201788 kb
Host smart-58a2e83d-866c-4fcd-bff1-c4d87f22dd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884802393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3884802393
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2543919812
Short name T400
Test name
Test status
Simulation time 161390120268 ps
CPU time 342 seconds
Started May 30 03:15:49 PM PDT 24
Finished May 30 03:21:32 PM PDT 24
Peak memory 201816 kb
Host smart-c14bdc1d-af9a-4c04-b2b3-54dae3672a54
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543919812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2543919812
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1209868481
Short name T476
Test name
Test status
Simulation time 498128718647 ps
CPU time 1122.43 seconds
Started May 30 03:15:50 PM PDT 24
Finished May 30 03:34:34 PM PDT 24
Peak memory 201840 kb
Host smart-63902acb-16ae-4421-b08c-23a75749787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209868481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1209868481
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1899335584
Short name T745
Test name
Test status
Simulation time 489805202107 ps
CPU time 69.39 seconds
Started May 30 03:15:50 PM PDT 24
Finished May 30 03:17:01 PM PDT 24
Peak memory 201780 kb
Host smart-e05c3c27-b6b7-4425-badf-2049456f41fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899335584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1899335584
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3409711879
Short name T450
Test name
Test status
Simulation time 172381855846 ps
CPU time 102.49 seconds
Started May 30 03:15:50 PM PDT 24
Finished May 30 03:17:34 PM PDT 24
Peak memory 201880 kb
Host smart-ca757d6c-cfde-4305-b96d-5be6c922a7a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409711879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3409711879
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.781940180
Short name T415
Test name
Test status
Simulation time 203386642017 ps
CPU time 494.41 seconds
Started May 30 03:15:48 PM PDT 24
Finished May 30 03:24:04 PM PDT 24
Peak memory 201776 kb
Host smart-a5a64b00-10df-422a-b37b-11ac5c601392
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781940180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
adc_ctrl_filters_wakeup_fixed.781940180
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1000433251
Short name T741
Test name
Test status
Simulation time 117154617045 ps
CPU time 398.12 seconds
Started May 30 03:15:55 PM PDT 24
Finished May 30 03:22:35 PM PDT 24
Peak memory 202164 kb
Host smart-17031c03-31ac-4b04-bf10-24cd551e3327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000433251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1000433251
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.724055293
Short name T570
Test name
Test status
Simulation time 28883707734 ps
CPU time 45.94 seconds
Started May 30 03:15:55 PM PDT 24
Finished May 30 03:16:43 PM PDT 24
Peak memory 201636 kb
Host smart-3eb5e52b-888c-4073-9ddb-27777e7407c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724055293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.724055293
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.156096605
Short name T342
Test name
Test status
Simulation time 3630093833 ps
CPU time 1.27 seconds
Started May 30 03:15:55 PM PDT 24
Finished May 30 03:15:57 PM PDT 24
Peak memory 201580 kb
Host smart-f5d9d50c-1973-4d32-83b0-deb0e3fae25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156096605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.156096605
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3747360074
Short name T531
Test name
Test status
Simulation time 5733959202 ps
CPU time 15.58 seconds
Started May 30 03:15:47 PM PDT 24
Finished May 30 03:16:03 PM PDT 24
Peak memory 201644 kb
Host smart-1075ec49-314a-4bde-a00c-fc93416934c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747360074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3747360074
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1642595369
Short name T84
Test name
Test status
Simulation time 23019374538 ps
CPU time 70.17 seconds
Started May 30 03:15:58 PM PDT 24
Finished May 30 03:17:10 PM PDT 24
Peak memory 216572 kb
Host smart-38cb30db-3ce0-45a1-b5bf-ac299de0a3c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642595369 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1642595369
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.840005233
Short name T403
Test name
Test status
Simulation time 404647081 ps
CPU time 1.23 seconds
Started May 30 03:16:22 PM PDT 24
Finished May 30 03:16:24 PM PDT 24
Peak memory 201516 kb
Host smart-e9d9dd68-3a21-48aa-ba75-e2055cbc9c2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840005233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.840005233
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.259864525
Short name T293
Test name
Test status
Simulation time 533775103835 ps
CPU time 217.03 seconds
Started May 30 03:16:05 PM PDT 24
Finished May 30 03:19:44 PM PDT 24
Peak memory 201840 kb
Host smart-2558a918-5586-448d-9e7a-93f750f5f73e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259864525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.259864525
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3893386606
Short name T639
Test name
Test status
Simulation time 331672195249 ps
CPU time 780.85 seconds
Started May 30 03:16:06 PM PDT 24
Finished May 30 03:29:09 PM PDT 24
Peak memory 201896 kb
Host smart-b4fc09fb-88ec-4974-9829-118d7aa20486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893386606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3893386606
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.4276650908
Short name T638
Test name
Test status
Simulation time 169398377486 ps
CPU time 376.3 seconds
Started May 30 03:16:06 PM PDT 24
Finished May 30 03:22:24 PM PDT 24
Peak memory 201780 kb
Host smart-6e0cae34-45b8-4d5e-8210-363e558dbf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276650908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.4276650908
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2533918747
Short name T445
Test name
Test status
Simulation time 320622187068 ps
CPU time 224.92 seconds
Started May 30 03:16:06 PM PDT 24
Finished May 30 03:19:52 PM PDT 24
Peak memory 201792 kb
Host smart-3a7e3901-b850-4678-a796-49173aa3162a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533918747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2533918747
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1995469260
Short name T782
Test name
Test status
Simulation time 485150044601 ps
CPU time 286.35 seconds
Started May 30 03:16:07 PM PDT 24
Finished May 30 03:20:55 PM PDT 24
Peak memory 201800 kb
Host smart-43556fde-113f-499c-921d-d588b635e0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995469260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1995469260
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.177261272
Short name T178
Test name
Test status
Simulation time 162696092513 ps
CPU time 103.06 seconds
Started May 30 03:16:05 PM PDT 24
Finished May 30 03:17:50 PM PDT 24
Peak memory 201828 kb
Host smart-bb379bd9-a913-444e-bdad-b0894fafc697
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=177261272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixe
d.177261272
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1984604316
Short name T542
Test name
Test status
Simulation time 614016307518 ps
CPU time 706.3 seconds
Started May 30 03:16:06 PM PDT 24
Finished May 30 03:27:55 PM PDT 24
Peak memory 201808 kb
Host smart-91438436-1049-4579-8872-40e734e25fd9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984604316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.1984604316
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2095357358
Short name T604
Test name
Test status
Simulation time 121687740773 ps
CPU time 586.1 seconds
Started May 30 03:16:22 PM PDT 24
Finished May 30 03:26:09 PM PDT 24
Peak memory 202168 kb
Host smart-15797b68-eaeb-4469-a4ef-f3a2226755cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095357358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2095357358
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.1030839215
Short name T522
Test name
Test status
Simulation time 45360166732 ps
CPU time 28.25 seconds
Started May 30 03:16:22 PM PDT 24
Finished May 30 03:16:52 PM PDT 24
Peak memory 201640 kb
Host smart-d8eec929-aede-4b98-ae83-f838f445fcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030839215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.1030839215
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.3688558042
Short name T709
Test name
Test status
Simulation time 5307049201 ps
CPU time 13.47 seconds
Started May 30 03:16:21 PM PDT 24
Finished May 30 03:16:35 PM PDT 24
Peak memory 201592 kb
Host smart-1748486e-5645-43eb-a2ca-780d1d563843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688558042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3688558042
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1307392544
Short name T411
Test name
Test status
Simulation time 5924199825 ps
CPU time 7.56 seconds
Started May 30 03:16:05 PM PDT 24
Finished May 30 03:16:15 PM PDT 24
Peak memory 201624 kb
Host smart-ba79c1b4-629e-4af1-8ee2-b942b510a00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307392544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1307392544
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3208706038
Short name T499
Test name
Test status
Simulation time 285595580756 ps
CPU time 474.87 seconds
Started May 30 03:16:21 PM PDT 24
Finished May 30 03:24:17 PM PDT 24
Peak memory 211980 kb
Host smart-66477352-8a9d-438a-944b-b3cdb3201ddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208706038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3208706038
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3745570348
Short name T586
Test name
Test status
Simulation time 475400729994 ps
CPU time 220.54 seconds
Started May 30 03:16:22 PM PDT 24
Finished May 30 03:20:04 PM PDT 24
Peak memory 217972 kb
Host smart-67ac3baf-6c85-4fae-bda8-41a5f1b0b6f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745570348 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3745570348
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1541563925
Short name T248
Test name
Test status
Simulation time 167890928499 ps
CPU time 195.82 seconds
Started May 30 03:16:27 PM PDT 24
Finished May 30 03:19:44 PM PDT 24
Peak memory 201896 kb
Host smart-302851f7-8407-4ccd-b45e-240fa9f2b46d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541563925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1541563925
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1332005756
Short name T313
Test name
Test status
Simulation time 570046656084 ps
CPU time 233.25 seconds
Started May 30 03:16:27 PM PDT 24
Finished May 30 03:20:21 PM PDT 24
Peak memory 201784 kb
Host smart-c0a0d758-716b-4a4e-901f-bdb489585470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332005756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1332005756
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1078412809
Short name T314
Test name
Test status
Simulation time 494660065023 ps
CPU time 365.64 seconds
Started May 30 03:16:22 PM PDT 24
Finished May 30 03:22:29 PM PDT 24
Peak memory 201864 kb
Host smart-c7081eb6-51a7-458e-bff1-7b669cad7768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078412809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1078412809
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1162317645
Short name T548
Test name
Test status
Simulation time 164581466875 ps
CPU time 65.27 seconds
Started May 30 03:16:23 PM PDT 24
Finished May 30 03:17:30 PM PDT 24
Peak memory 201812 kb
Host smart-10754407-e26b-429b-b48f-93ffb6c25548
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162317645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1162317645
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.592791020
Short name T484
Test name
Test status
Simulation time 164109216765 ps
CPU time 96.99 seconds
Started May 30 03:16:21 PM PDT 24
Finished May 30 03:17:59 PM PDT 24
Peak memory 201876 kb
Host smart-78119ab3-b942-4399-9225-8207d6f3a5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592791020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.592791020
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.219560220
Short name T770
Test name
Test status
Simulation time 329383879056 ps
CPU time 723.84 seconds
Started May 30 03:16:22 PM PDT 24
Finished May 30 03:28:27 PM PDT 24
Peak memory 201780 kb
Host smart-1dc8a69b-b99e-484c-816c-d587d947835e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=219560220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.219560220
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.432639603
Short name T242
Test name
Test status
Simulation time 368838833161 ps
CPU time 851.48 seconds
Started May 30 03:16:22 PM PDT 24
Finished May 30 03:30:35 PM PDT 24
Peak memory 201836 kb
Host smart-83564fac-3f83-40a5-9e60-42e4bf959e11
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432639603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.432639603
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.267578511
Short name T523
Test name
Test status
Simulation time 207632397980 ps
CPU time 238.79 seconds
Started May 30 03:16:28 PM PDT 24
Finished May 30 03:20:27 PM PDT 24
Peak memory 201784 kb
Host smart-848f8157-0e3c-4268-b224-41b29918b962
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267578511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.267578511
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1443285014
Short name T393
Test name
Test status
Simulation time 43356190782 ps
CPU time 47.31 seconds
Started May 30 03:16:25 PM PDT 24
Finished May 30 03:17:14 PM PDT 24
Peak memory 201620 kb
Host smart-a6c30fc3-8e18-4430-bea5-388cf2f1566f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443285014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1443285014
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1591604337
Short name T363
Test name
Test status
Simulation time 5177522516 ps
CPU time 3.68 seconds
Started May 30 03:16:28 PM PDT 24
Finished May 30 03:16:33 PM PDT 24
Peak memory 201620 kb
Host smart-9586217c-878b-4137-b451-16144f7785b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591604337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1591604337
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.759603426
Short name T697
Test name
Test status
Simulation time 5820942398 ps
CPU time 8.25 seconds
Started May 30 03:16:21 PM PDT 24
Finished May 30 03:16:30 PM PDT 24
Peak memory 201648 kb
Host smart-57936ca8-432b-4821-b727-ef9b8e67f053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759603426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.759603426
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.509798117
Short name T792
Test name
Test status
Simulation time 480018757651 ps
CPU time 249.49 seconds
Started May 30 03:16:27 PM PDT 24
Finished May 30 03:20:38 PM PDT 24
Peak memory 210700 kb
Host smart-c5f6948a-d5e6-4908-a97f-34404af6cb41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509798117 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.509798117
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2121537734
Short name T472
Test name
Test status
Simulation time 613383224 ps
CPU time 0.69 seconds
Started May 30 03:16:48 PM PDT 24
Finished May 30 03:16:51 PM PDT 24
Peak memory 201480 kb
Host smart-089580ba-8cd9-4f16-a181-73200b325bbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121537734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2121537734
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.692507106
Short name T528
Test name
Test status
Simulation time 354718966405 ps
CPU time 835.02 seconds
Started May 30 03:16:39 PM PDT 24
Finished May 30 03:30:35 PM PDT 24
Peak memory 201804 kb
Host smart-ecab42c3-8a4b-4c9e-8c17-137ad4b2bc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692507106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.692507106
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.2067556868
Short name T301
Test name
Test status
Simulation time 330496059709 ps
CPU time 790.02 seconds
Started May 30 03:16:29 PM PDT 24
Finished May 30 03:29:40 PM PDT 24
Peak memory 201800 kb
Host smart-fc40286b-e9d8-4f0b-b2fd-95800e3c0004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067556868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2067556868
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.4273328680
Short name T503
Test name
Test status
Simulation time 163788277707 ps
CPU time 105.71 seconds
Started May 30 03:16:27 PM PDT 24
Finished May 30 03:18:14 PM PDT 24
Peak memory 201816 kb
Host smart-50917d5b-16df-42aa-8f3a-4f547ccbcc40
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273328680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.4273328680
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3728492622
Short name T357
Test name
Test status
Simulation time 497404337146 ps
CPU time 314.17 seconds
Started May 30 03:16:26 PM PDT 24
Finished May 30 03:21:41 PM PDT 24
Peak memory 201788 kb
Host smart-81adf3e6-93f4-463b-865a-5a1409770844
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728492622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3728492622
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.470391850
Short name T157
Test name
Test status
Simulation time 367766925595 ps
CPU time 210.47 seconds
Started May 30 03:16:26 PM PDT 24
Finished May 30 03:19:57 PM PDT 24
Peak memory 201900 kb
Host smart-d828d3ec-fb8d-4ca1-a824-3bc8df5c21d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470391850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.470391850
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.29821616
Short name T535
Test name
Test status
Simulation time 102487334489 ps
CPU time 576.77 seconds
Started May 30 03:16:40 PM PDT 24
Finished May 30 03:26:18 PM PDT 24
Peak memory 202104 kb
Host smart-a06575f0-8a5f-4493-a510-9f1aa1a4eefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29821616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.29821616
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1683915858
Short name T133
Test name
Test status
Simulation time 31668752154 ps
CPU time 76.91 seconds
Started May 30 03:16:38 PM PDT 24
Finished May 30 03:17:56 PM PDT 24
Peak memory 201628 kb
Host smart-a3010cd9-bb2d-4f9e-93d5-b3ddfa041b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683915858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1683915858
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1449661868
Short name T132
Test name
Test status
Simulation time 4515358988 ps
CPU time 6.19 seconds
Started May 30 03:16:38 PM PDT 24
Finished May 30 03:16:46 PM PDT 24
Peak memory 201536 kb
Host smart-e16eed1c-e931-4f3b-8109-d4231dbf2926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449661868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1449661868
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.945735049
Short name T619
Test name
Test status
Simulation time 5922365182 ps
CPU time 2.11 seconds
Started May 30 03:16:27 PM PDT 24
Finished May 30 03:16:30 PM PDT 24
Peak memory 201644 kb
Host smart-0608c986-c97c-418a-bad8-2506bea548e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945735049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.945735049
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.3677373835
Short name T532
Test name
Test status
Simulation time 719285200738 ps
CPU time 1706.07 seconds
Started May 30 03:16:39 PM PDT 24
Finished May 30 03:45:06 PM PDT 24
Peak memory 201804 kb
Host smart-ccfbdfc5-1478-4fcc-bbe1-0e55b899eae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677373835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.3677373835
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.2517320602
Short name T88
Test name
Test status
Simulation time 110973669352 ps
CPU time 92.93 seconds
Started May 30 03:16:38 PM PDT 24
Finished May 30 03:18:12 PM PDT 24
Peak memory 210416 kb
Host smart-692032f1-5a7e-4d3e-a875-e23cc10a63e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517320602 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.2517320602
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2435594291
Short name T331
Test name
Test status
Simulation time 311147496 ps
CPU time 0.79 seconds
Started May 30 03:17:01 PM PDT 24
Finished May 30 03:17:03 PM PDT 24
Peak memory 201516 kb
Host smart-d39be8c4-5417-4ecc-974a-f7383079c9f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435594291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2435594291
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2028303486
Short name T302
Test name
Test status
Simulation time 510957372811 ps
CPU time 597.58 seconds
Started May 30 03:17:01 PM PDT 24
Finished May 30 03:27:00 PM PDT 24
Peak memory 201856 kb
Host smart-ae33c351-b2b9-4e8a-8720-e1ed523197dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028303486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2028303486
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.4116292328
Short name T219
Test name
Test status
Simulation time 346592014354 ps
CPU time 895.25 seconds
Started May 30 03:17:02 PM PDT 24
Finished May 30 03:31:59 PM PDT 24
Peak memory 201804 kb
Host smart-6e29e793-4e8c-4056-a38c-7c76ebcf4231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116292328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.4116292328
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2295947919
Short name T212
Test name
Test status
Simulation time 497176205411 ps
CPU time 565.47 seconds
Started May 30 03:16:48 PM PDT 24
Finished May 30 03:26:16 PM PDT 24
Peak memory 201816 kb
Host smart-c0eeb589-e8de-47b5-9772-dc100b3cfdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295947919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2295947919
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.860017793
Short name T92
Test name
Test status
Simulation time 165202802819 ps
CPU time 79.22 seconds
Started May 30 03:16:47 PM PDT 24
Finished May 30 03:18:09 PM PDT 24
Peak memory 201772 kb
Host smart-f2583749-eaa4-4875-8182-5b1e724b7af7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=860017793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrup
t_fixed.860017793
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3717889373
Short name T563
Test name
Test status
Simulation time 166511577394 ps
CPU time 396.38 seconds
Started May 30 03:16:48 PM PDT 24
Finished May 30 03:23:27 PM PDT 24
Peak memory 201788 kb
Host smart-3c3fa3f3-600d-4bea-bb7d-dcd129c0f76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717889373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3717889373
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3379691793
Short name T492
Test name
Test status
Simulation time 161958492044 ps
CPU time 362.18 seconds
Started May 30 03:16:47 PM PDT 24
Finished May 30 03:22:51 PM PDT 24
Peak memory 201788 kb
Host smart-3eec7544-16c4-45cd-85dc-c7ebadf06972
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379691793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3379691793
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1632879592
Short name T536
Test name
Test status
Simulation time 594745644352 ps
CPU time 345.37 seconds
Started May 30 03:16:47 PM PDT 24
Finished May 30 03:22:34 PM PDT 24
Peak memory 201788 kb
Host smart-27ecc384-2abd-4bd1-a5f9-2eb3828757df
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632879592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1632879592
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.943324815
Short name T731
Test name
Test status
Simulation time 27871018142 ps
CPU time 31.93 seconds
Started May 30 03:17:01 PM PDT 24
Finished May 30 03:17:34 PM PDT 24
Peak memory 201616 kb
Host smart-bdb65b37-a921-4a13-8f98-46982f38b04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943324815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.943324815
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.304306944
Short name T550
Test name
Test status
Simulation time 4999889523 ps
CPU time 12.19 seconds
Started May 30 03:17:03 PM PDT 24
Finished May 30 03:17:16 PM PDT 24
Peak memory 201620 kb
Host smart-d8aa58c2-3bca-466e-98c2-be4739fa2fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304306944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.304306944
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3472638874
Short name T489
Test name
Test status
Simulation time 5938117666 ps
CPU time 7.6 seconds
Started May 30 03:16:47 PM PDT 24
Finished May 30 03:16:57 PM PDT 24
Peak memory 201644 kb
Host smart-d32dc643-3bca-4dba-8b5e-b7daee33c9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472638874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3472638874
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.4081776375
Short name T765
Test name
Test status
Simulation time 346105690088 ps
CPU time 866.19 seconds
Started May 30 03:17:02 PM PDT 24
Finished May 30 03:31:30 PM PDT 24
Peak memory 201772 kb
Host smart-9219e698-826f-4079-a95a-2835a3f8bca6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081776375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.4081776375
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1316426892
Short name T16
Test name
Test status
Simulation time 191780207040 ps
CPU time 131.39 seconds
Started May 30 03:17:03 PM PDT 24
Finished May 30 03:19:15 PM PDT 24
Peak memory 210432 kb
Host smart-ba26c7be-c2f5-4fd6-8be0-c13ee2c32852
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316426892 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1316426892
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2149420066
Short name T573
Test name
Test status
Simulation time 315314070 ps
CPU time 0.93 seconds
Started May 30 03:17:24 PM PDT 24
Finished May 30 03:17:26 PM PDT 24
Peak memory 201492 kb
Host smart-a13ea282-3bdf-4ff0-934e-829024eb4a67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149420066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2149420066
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3644240674
Short name T10
Test name
Test status
Simulation time 164817221749 ps
CPU time 384.27 seconds
Started May 30 03:17:12 PM PDT 24
Finished May 30 03:23:38 PM PDT 24
Peak memory 201852 kb
Host smart-13737913-f101-4578-ae73-ab7e73cabd75
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644240674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3644240674
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1036784573
Short name T253
Test name
Test status
Simulation time 328660551916 ps
CPU time 686 seconds
Started May 30 03:17:12 PM PDT 24
Finished May 30 03:28:39 PM PDT 24
Peak memory 201816 kb
Host smart-b1590cbc-2ac4-494c-92fa-7b4b19ae9fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036784573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1036784573
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.4212796907
Short name T214
Test name
Test status
Simulation time 493572447131 ps
CPU time 219.23 seconds
Started May 30 03:17:14 PM PDT 24
Finished May 30 03:20:54 PM PDT 24
Peak memory 201792 kb
Host smart-78e33100-93c6-42eb-a174-f536c9568a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212796907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.4212796907
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1572871580
Short name T377
Test name
Test status
Simulation time 484838739917 ps
CPU time 298.03 seconds
Started May 30 03:17:12 PM PDT 24
Finished May 30 03:22:12 PM PDT 24
Peak memory 201768 kb
Host smart-5bc2e09f-0f9b-4061-bda4-a5861407be05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572871580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1572871580
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1699932365
Short name T199
Test name
Test status
Simulation time 494366593903 ps
CPU time 571.01 seconds
Started May 30 03:17:13 PM PDT 24
Finished May 30 03:26:45 PM PDT 24
Peak memory 201792 kb
Host smart-9a986322-cf33-4816-bae8-cf9e2f4edd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699932365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1699932365
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2320495917
Short name T477
Test name
Test status
Simulation time 493079317774 ps
CPU time 1189.07 seconds
Started May 30 03:17:13 PM PDT 24
Finished May 30 03:37:03 PM PDT 24
Peak memory 201800 kb
Host smart-610d4eba-b8eb-48ee-bd7e-31452d1f5721
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320495917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2320495917
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3217831820
Short name T793
Test name
Test status
Simulation time 342084506320 ps
CPU time 75.88 seconds
Started May 30 03:17:13 PM PDT 24
Finished May 30 03:18:30 PM PDT 24
Peak memory 201816 kb
Host smart-b9fe2c5c-c079-43b4-93cb-f335c2b31d62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217831820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3217831820
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3953387532
Short name T427
Test name
Test status
Simulation time 203873233162 ps
CPU time 124.57 seconds
Started May 30 03:17:12 PM PDT 24
Finished May 30 03:19:17 PM PDT 24
Peak memory 201820 kb
Host smart-b2965711-7e22-45c8-8fa2-05e6cff483e8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953387532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3953387532
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2333821011
Short name T603
Test name
Test status
Simulation time 139361322594 ps
CPU time 711 seconds
Started May 30 03:17:11 PM PDT 24
Finished May 30 03:29:03 PM PDT 24
Peak memory 202040 kb
Host smart-cc68e921-49ce-44b5-b9f9-4cdde3332d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333821011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2333821011
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1316611440
Short name T628
Test name
Test status
Simulation time 30226486914 ps
CPU time 64.43 seconds
Started May 30 03:17:13 PM PDT 24
Finished May 30 03:18:19 PM PDT 24
Peak memory 201628 kb
Host smart-d2399fa4-252f-4f8c-8d4a-4ffa26b9cd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316611440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1316611440
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2196326153
Short name T631
Test name
Test status
Simulation time 4802452169 ps
CPU time 3.59 seconds
Started May 30 03:17:12 PM PDT 24
Finished May 30 03:17:17 PM PDT 24
Peak memory 201592 kb
Host smart-0f8bf1fa-0b83-49f6-847c-5366b5c420f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196326153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2196326153
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3595946461
Short name T118
Test name
Test status
Simulation time 5751130478 ps
CPU time 2.47 seconds
Started May 30 03:17:14 PM PDT 24
Finished May 30 03:17:18 PM PDT 24
Peak memory 201656 kb
Host smart-bcf310e8-d274-441b-bbfd-4ffd5c2bff39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595946461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3595946461
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1574160485
Short name T89
Test name
Test status
Simulation time 326933299104 ps
CPU time 670.32 seconds
Started May 30 03:17:27 PM PDT 24
Finished May 30 03:28:38 PM PDT 24
Peak memory 201836 kb
Host smart-d761eebd-2c83-47f3-a0e1-7414844084f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574160485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1574160485
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2209991227
Short name T713
Test name
Test status
Simulation time 273863102787 ps
CPU time 167.37 seconds
Started May 30 03:17:14 PM PDT 24
Finished May 30 03:20:02 PM PDT 24
Peak memory 210504 kb
Host smart-25de8049-59ac-4b90-9cbb-4e1c099e4f95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209991227 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2209991227
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1608130901
Short name T339
Test name
Test status
Simulation time 399005104 ps
CPU time 1.52 seconds
Started May 30 03:17:36 PM PDT 24
Finished May 30 03:17:39 PM PDT 24
Peak memory 201520 kb
Host smart-94f7de0e-9806-4ff8-9d36-ec202b38145b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608130901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1608130901
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2278735101
Short name T707
Test name
Test status
Simulation time 162279382275 ps
CPU time 94.67 seconds
Started May 30 03:17:36 PM PDT 24
Finished May 30 03:19:11 PM PDT 24
Peak memory 201876 kb
Host smart-af01534f-9e6f-45d9-a90b-8a0c5b388688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278735101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2278735101
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2032942360
Short name T271
Test name
Test status
Simulation time 489077111198 ps
CPU time 550.72 seconds
Started May 30 03:17:26 PM PDT 24
Finished May 30 03:26:38 PM PDT 24
Peak memory 201816 kb
Host smart-934c77c3-b2a5-42bf-9b39-8613f32c3de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032942360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2032942360
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1575491236
Short name T378
Test name
Test status
Simulation time 164711433089 ps
CPU time 419.18 seconds
Started May 30 03:17:26 PM PDT 24
Finished May 30 03:24:26 PM PDT 24
Peak memory 201800 kb
Host smart-77148e77-6ccd-4b42-8392-be4c722bdeaf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575491236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1575491236
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3531403059
Short name T749
Test name
Test status
Simulation time 327748104713 ps
CPU time 363.3 seconds
Started May 30 03:17:23 PM PDT 24
Finished May 30 03:23:27 PM PDT 24
Peak memory 201788 kb
Host smart-74446892-5953-41c9-aec9-05f942c3244a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531403059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3531403059
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2066986685
Short name T665
Test name
Test status
Simulation time 182870674962 ps
CPU time 105.24 seconds
Started May 30 03:17:27 PM PDT 24
Finished May 30 03:19:13 PM PDT 24
Peak memory 201912 kb
Host smart-61a93cfd-44e3-4a48-990b-75c8be11dafe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066986685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2066986685
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2321966250
Short name T560
Test name
Test status
Simulation time 398234740425 ps
CPU time 251.85 seconds
Started May 30 03:17:23 PM PDT 24
Finished May 30 03:21:36 PM PDT 24
Peak memory 201816 kb
Host smart-806faeea-25fa-45b1-82b4-14d809dd9130
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321966250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2321966250
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.861019029
Short name T389
Test name
Test status
Simulation time 29751551143 ps
CPU time 18.39 seconds
Started May 30 03:17:36 PM PDT 24
Finished May 30 03:17:55 PM PDT 24
Peak memory 201640 kb
Host smart-92d06894-4f81-4b2c-a701-ac7305d4fadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861019029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.861019029
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2811386403
Short name T351
Test name
Test status
Simulation time 4167176077 ps
CPU time 3.03 seconds
Started May 30 03:17:36 PM PDT 24
Finished May 30 03:17:40 PM PDT 24
Peak memory 201620 kb
Host smart-14d717d4-6349-4be7-9f2a-b116bfd8e232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811386403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2811386403
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1422677942
Short name T787
Test name
Test status
Simulation time 6154628901 ps
CPU time 5.14 seconds
Started May 30 03:17:26 PM PDT 24
Finished May 30 03:17:32 PM PDT 24
Peak memory 201668 kb
Host smart-b3467fa0-9574-4a8a-926e-092e8254d419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422677942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1422677942
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.3560531110
Short name T24
Test name
Test status
Simulation time 169296844780 ps
CPU time 310.66 seconds
Started May 30 03:17:39 PM PDT 24
Finished May 30 03:22:51 PM PDT 24
Peak memory 201744 kb
Host smart-27b435b6-e863-41e3-9fd2-cfcafb49a79e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560531110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.3560531110
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3859107543
Short name T646
Test name
Test status
Simulation time 204361204233 ps
CPU time 61.34 seconds
Started May 30 03:17:39 PM PDT 24
Finished May 30 03:18:42 PM PDT 24
Peak memory 210108 kb
Host smart-792edfa9-abf0-4202-93ce-76392698d176
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859107543 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3859107543
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.150489270
Short name T375
Test name
Test status
Simulation time 523317343 ps
CPU time 1.01 seconds
Started May 30 03:18:01 PM PDT 24
Finished May 30 03:18:03 PM PDT 24
Peak memory 201520 kb
Host smart-7b4394bb-f24b-47f6-9f6d-598bf1a342e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150489270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.150489270
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1470286709
Short name T318
Test name
Test status
Simulation time 163080427143 ps
CPU time 38.71 seconds
Started May 30 03:17:51 PM PDT 24
Finished May 30 03:18:30 PM PDT 24
Peak memory 201768 kb
Host smart-db166f0b-89a8-4b63-a459-803c390abb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470286709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1470286709
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.462138875
Short name T471
Test name
Test status
Simulation time 335211392906 ps
CPU time 404.64 seconds
Started May 30 03:17:38 PM PDT 24
Finished May 30 03:24:25 PM PDT 24
Peak memory 201732 kb
Host smart-16387023-0d99-43bf-83ae-f99169435de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462138875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.462138875
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3224743869
Short name T408
Test name
Test status
Simulation time 164627694314 ps
CPU time 412.88 seconds
Started May 30 03:17:51 PM PDT 24
Finished May 30 03:24:45 PM PDT 24
Peak memory 201772 kb
Host smart-baecf09e-4e8d-4b7a-b832-e2d4f932f83e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224743869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3224743869
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.987224342
Short name T457
Test name
Test status
Simulation time 399313584253 ps
CPU time 210.5 seconds
Started May 30 03:17:53 PM PDT 24
Finished May 30 03:21:24 PM PDT 24
Peak memory 201804 kb
Host smart-208c9d65-4590-4aad-af23-2fbbac34187b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987224342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.987224342
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.4175238248
Short name T674
Test name
Test status
Simulation time 82796585799 ps
CPU time 263.3 seconds
Started May 30 03:18:01 PM PDT 24
Finished May 30 03:22:25 PM PDT 24
Peak memory 202188 kb
Host smart-7b03ef09-395b-498f-9641-4c4830e6f062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175238248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.4175238248
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3026521438
Short name T466
Test name
Test status
Simulation time 27869542517 ps
CPU time 11 seconds
Started May 30 03:18:02 PM PDT 24
Finished May 30 03:18:15 PM PDT 24
Peak memory 201592 kb
Host smart-4e7b5c84-18c5-4c1f-8740-2b6c31785e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026521438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3026521438
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.700608006
Short name T433
Test name
Test status
Simulation time 4727524727 ps
CPU time 11.92 seconds
Started May 30 03:18:00 PM PDT 24
Finished May 30 03:18:13 PM PDT 24
Peak memory 201612 kb
Host smart-4362034e-f5a7-4a84-9a04-c514a440082e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700608006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.700608006
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.434230868
Short name T87
Test name
Test status
Simulation time 5714194367 ps
CPU time 14.52 seconds
Started May 30 03:17:36 PM PDT 24
Finished May 30 03:17:51 PM PDT 24
Peak memory 201620 kb
Host smart-47f1eeb0-3b7f-48c6-845f-2f25dcd1bb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434230868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.434230868
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.26877896
Short name T754
Test name
Test status
Simulation time 179765084212 ps
CPU time 431.94 seconds
Started May 30 03:18:02 PM PDT 24
Finished May 30 03:25:15 PM PDT 24
Peak memory 201788 kb
Host smart-0d2bb1ff-6975-4ed9-a3bf-24b55520319e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26877896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.26877896
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1952228284
Short name T81
Test name
Test status
Simulation time 31836747161 ps
CPU time 113.42 seconds
Started May 30 03:18:01 PM PDT 24
Finished May 30 03:19:55 PM PDT 24
Peak memory 210424 kb
Host smart-8ce8f4ce-906a-4fc9-a674-12c471b86a7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952228284 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1952228284
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.4167182550
Short name T543
Test name
Test status
Simulation time 403911590 ps
CPU time 0.89 seconds
Started May 30 03:14:38 PM PDT 24
Finished May 30 03:14:40 PM PDT 24
Peak memory 201516 kb
Host smart-06b49b25-ab9c-4c8c-bd4a-e1d69425d76b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167182550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.4167182550
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.124650047
Short name T203
Test name
Test status
Simulation time 353338602149 ps
CPU time 444.86 seconds
Started May 30 03:14:31 PM PDT 24
Finished May 30 03:21:57 PM PDT 24
Peak memory 201736 kb
Host smart-d8c7c059-752d-4647-a706-802e20d4ae5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124650047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.124650047
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.711365640
Short name T796
Test name
Test status
Simulation time 336057030122 ps
CPU time 180.49 seconds
Started May 30 03:14:32 PM PDT 24
Finished May 30 03:17:34 PM PDT 24
Peak memory 201812 kb
Host smart-d09b9032-2e74-4a46-9e5a-12a7f2e5f6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711365640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.711365640
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2015249907
Short name T213
Test name
Test status
Simulation time 163001380963 ps
CPU time 74.37 seconds
Started May 30 03:14:27 PM PDT 24
Finished May 30 03:15:42 PM PDT 24
Peak memory 201824 kb
Host smart-386b3022-426d-4d8e-824f-23fc279fd617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015249907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2015249907
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1712150720
Short name T159
Test name
Test status
Simulation time 322784901998 ps
CPU time 192.57 seconds
Started May 30 03:14:33 PM PDT 24
Finished May 30 03:17:47 PM PDT 24
Peak memory 201792 kb
Host smart-9193d966-bd94-48de-89e0-f45ec4706b53
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712150720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1712150720
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3153380905
Short name T292
Test name
Test status
Simulation time 334451227460 ps
CPU time 763.19 seconds
Started May 30 03:14:29 PM PDT 24
Finished May 30 03:27:13 PM PDT 24
Peak memory 201784 kb
Host smart-3d6095ed-fabe-4dd1-8658-0720ca7394ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153380905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3153380905
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3311103942
Short name T505
Test name
Test status
Simulation time 163269476663 ps
CPU time 102.66 seconds
Started May 30 03:14:33 PM PDT 24
Finished May 30 03:16:17 PM PDT 24
Peak memory 201732 kb
Host smart-17fa266d-c3b7-4212-952e-a31c33b68089
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311103942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3311103942
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.236929486
Short name T708
Test name
Test status
Simulation time 543402619852 ps
CPU time 1255.95 seconds
Started May 30 03:14:28 PM PDT 24
Finished May 30 03:35:26 PM PDT 24
Peak memory 201812 kb
Host smart-c04cae9c-1a54-49cf-9760-429f47919277
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236929486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.236929486
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2894383268
Short name T626
Test name
Test status
Simulation time 388468341065 ps
CPU time 935.8 seconds
Started May 30 03:14:29 PM PDT 24
Finished May 30 03:30:06 PM PDT 24
Peak memory 201812 kb
Host smart-1ecc8ae9-2bb2-43d2-8ff2-0c44d4e982ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894383268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2894383268
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.4263718358
Short name T190
Test name
Test status
Simulation time 102668099946 ps
CPU time 532.15 seconds
Started May 30 03:14:37 PM PDT 24
Finished May 30 03:23:31 PM PDT 24
Peak memory 202216 kb
Host smart-49168121-a965-4027-82bd-9e7e723ebc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263718358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.4263718358
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3508189776
Short name T561
Test name
Test status
Simulation time 24804027272 ps
CPU time 53.33 seconds
Started May 30 03:14:37 PM PDT 24
Finished May 30 03:15:32 PM PDT 24
Peak memory 201576 kb
Host smart-16ed5921-cea0-48ad-9aa5-d7cba09b0cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508189776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3508189776
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1380068272
Short name T116
Test name
Test status
Simulation time 3318325090 ps
CPU time 2.52 seconds
Started May 30 03:14:26 PM PDT 24
Finished May 30 03:14:30 PM PDT 24
Peak memory 201600 kb
Host smart-2c812590-f4a4-4f3e-9a71-1462a5a94a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380068272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1380068272
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2305695602
Short name T73
Test name
Test status
Simulation time 8144564171 ps
CPU time 5.64 seconds
Started May 30 03:14:35 PM PDT 24
Finished May 30 03:14:42 PM PDT 24
Peak memory 218372 kb
Host smart-dcd04754-0d2f-43d9-878b-831f9d355bf9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305695602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2305695602
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.796212485
Short name T333
Test name
Test status
Simulation time 5641060328 ps
CPU time 14.74 seconds
Started May 30 03:14:33 PM PDT 24
Finished May 30 03:14:49 PM PDT 24
Peak memory 201636 kb
Host smart-e7da06b5-5ef6-40ce-8973-42751fd0fecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796212485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.796212485
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1781570802
Short name T566
Test name
Test status
Simulation time 236794995604 ps
CPU time 489.03 seconds
Started May 30 03:14:37 PM PDT 24
Finished May 30 03:22:48 PM PDT 24
Peak memory 201876 kb
Host smart-ae1edfda-f26c-44fc-b0cd-45d6f86005bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781570802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1781570802
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3357257363
Short name T641
Test name
Test status
Simulation time 95336640027 ps
CPU time 61.94 seconds
Started May 30 03:14:36 PM PDT 24
Finished May 30 03:15:39 PM PDT 24
Peak memory 218332 kb
Host smart-de130e4f-8626-4d43-b4fd-79dc79d4e797
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357257363 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3357257363
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3401891596
Short name T508
Test name
Test status
Simulation time 439505119 ps
CPU time 0.84 seconds
Started May 30 03:18:21 PM PDT 24
Finished May 30 03:18:23 PM PDT 24
Peak memory 201516 kb
Host smart-0a5a5e3e-0656-4201-881a-f32198326812
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401891596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3401891596
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2609079262
Short name T766
Test name
Test status
Simulation time 159082521143 ps
CPU time 367.37 seconds
Started May 30 03:18:17 PM PDT 24
Finished May 30 03:24:25 PM PDT 24
Peak memory 201744 kb
Host smart-909dfb4c-3eb7-49dc-833e-f497a6b710ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609079262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2609079262
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3156477426
Short name T260
Test name
Test status
Simulation time 164225880398 ps
CPU time 111.49 seconds
Started May 30 03:18:04 PM PDT 24
Finished May 30 03:19:56 PM PDT 24
Peak memory 201800 kb
Host smart-083ff32c-ae3d-462f-b9a7-7e3f784a738f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156477426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3156477426
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3401316183
Short name T690
Test name
Test status
Simulation time 484603050359 ps
CPU time 1000.86 seconds
Started May 30 03:18:11 PM PDT 24
Finished May 30 03:34:53 PM PDT 24
Peak memory 201800 kb
Host smart-213a7e2f-5c01-4d83-b0e6-f7e3f975d5e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401316183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3401316183
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3934447295
Short name T394
Test name
Test status
Simulation time 159975071303 ps
CPU time 101.52 seconds
Started May 30 03:18:02 PM PDT 24
Finished May 30 03:19:45 PM PDT 24
Peak memory 201792 kb
Host smart-51dd0f35-c80c-4e34-bd23-1fa74a04d96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934447295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3934447295
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.53760887
Short name T556
Test name
Test status
Simulation time 335631764949 ps
CPU time 358.77 seconds
Started May 30 03:18:02 PM PDT 24
Finished May 30 03:24:02 PM PDT 24
Peak memory 201828 kb
Host smart-336ebce6-5100-4b6e-a87f-d4a1d86adb4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=53760887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixed
.53760887
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2458896877
Short name T643
Test name
Test status
Simulation time 568189391696 ps
CPU time 330.79 seconds
Started May 30 03:18:12 PM PDT 24
Finished May 30 03:23:44 PM PDT 24
Peak memory 201848 kb
Host smart-d6c8b981-4b36-47db-b725-5adb7d8550a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458896877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2458896877
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3188268950
Short name T12
Test name
Test status
Simulation time 394462926220 ps
CPU time 242.29 seconds
Started May 30 03:18:18 PM PDT 24
Finished May 30 03:22:21 PM PDT 24
Peak memory 201748 kb
Host smart-9f1c0eca-d4aa-41b7-ad18-b8beb55019f2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188268950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3188268950
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.4132326706
Short name T498
Test name
Test status
Simulation time 125193513754 ps
CPU time 638.07 seconds
Started May 30 03:18:14 PM PDT 24
Finished May 30 03:28:53 PM PDT 24
Peak memory 202168 kb
Host smart-4e7dc7a8-2156-4216-9040-dd00d392d2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132326706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.4132326706
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2662002907
Short name T507
Test name
Test status
Simulation time 24640186766 ps
CPU time 32.46 seconds
Started May 30 03:18:12 PM PDT 24
Finished May 30 03:18:46 PM PDT 24
Peak memory 201624 kb
Host smart-344364e5-bd3b-4370-bc13-449df3a751d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662002907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2662002907
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2487425150
Short name T488
Test name
Test status
Simulation time 3125115831 ps
CPU time 8.11 seconds
Started May 30 03:18:12 PM PDT 24
Finished May 30 03:18:21 PM PDT 24
Peak memory 201628 kb
Host smart-86b09c77-66a8-4abf-a45e-6b9b855c1758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487425150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2487425150
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3419140229
Short name T574
Test name
Test status
Simulation time 5954553863 ps
CPU time 3.06 seconds
Started May 30 03:18:05 PM PDT 24
Finished May 30 03:18:09 PM PDT 24
Peak memory 201632 kb
Host smart-98052a10-1962-4b2e-b863-bb3f0ffeeb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419140229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3419140229
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2840922596
Short name T783
Test name
Test status
Simulation time 69485983667 ps
CPU time 186.28 seconds
Started May 30 03:18:17 PM PDT 24
Finished May 30 03:21:25 PM PDT 24
Peak memory 217636 kb
Host smart-b03990ed-c944-4abf-8ba2-854a007bcd15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840922596 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2840922596
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2608958520
Short name T345
Test name
Test status
Simulation time 495031763 ps
CPU time 1.74 seconds
Started May 30 03:18:33 PM PDT 24
Finished May 30 03:18:35 PM PDT 24
Peak memory 201500 kb
Host smart-347caa19-83f6-4e3d-9d4d-c78d47b9a0a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608958520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2608958520
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3248371058
Short name T289
Test name
Test status
Simulation time 190628517545 ps
CPU time 109.02 seconds
Started May 30 03:18:23 PM PDT 24
Finished May 30 03:20:13 PM PDT 24
Peak memory 201780 kb
Host smart-da6adba5-481c-4fed-b82d-31cb4ebcd882
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248371058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3248371058
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2608354828
Short name T77
Test name
Test status
Simulation time 343831203822 ps
CPU time 53.61 seconds
Started May 30 03:18:36 PM PDT 24
Finished May 30 03:19:30 PM PDT 24
Peak memory 201816 kb
Host smart-499d4cc1-b624-4331-9d7e-00c47012b363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608354828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2608354828
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2465732911
Short name T705
Test name
Test status
Simulation time 493314967613 ps
CPU time 1068.79 seconds
Started May 30 03:18:23 PM PDT 24
Finished May 30 03:36:13 PM PDT 24
Peak memory 201744 kb
Host smart-155c5ca3-e976-4b35-b206-fe32a606b806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465732911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2465732911
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3171821663
Short name T384
Test name
Test status
Simulation time 493147638639 ps
CPU time 1040.98 seconds
Started May 30 03:18:23 PM PDT 24
Finished May 30 03:35:45 PM PDT 24
Peak memory 201804 kb
Host smart-d2fb11eb-c2bc-41a2-9e9f-4144119a7255
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171821663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3171821663
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2045727347
Short name T606
Test name
Test status
Simulation time 161528577461 ps
CPU time 43.62 seconds
Started May 30 03:18:21 PM PDT 24
Finished May 30 03:19:06 PM PDT 24
Peak memory 201812 kb
Host smart-6128d782-c564-483f-8666-3cf4691a85d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045727347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2045727347
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.723734615
Short name T454
Test name
Test status
Simulation time 166488574234 ps
CPU time 375.9 seconds
Started May 30 03:18:23 PM PDT 24
Finished May 30 03:24:40 PM PDT 24
Peak memory 201828 kb
Host smart-3bba8bbe-40f0-40f8-b4d7-2e181f775f22
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=723734615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixe
d.723734615
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1163451097
Short name T738
Test name
Test status
Simulation time 544507317510 ps
CPU time 299.5 seconds
Started May 30 03:18:23 PM PDT 24
Finished May 30 03:23:24 PM PDT 24
Peak memory 201772 kb
Host smart-401e0eda-38d8-4573-ae1b-d343b25871cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163451097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1163451097
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3849985411
Short name T788
Test name
Test status
Simulation time 602749772219 ps
CPU time 1312.25 seconds
Started May 30 03:18:25 PM PDT 24
Finished May 30 03:40:19 PM PDT 24
Peak memory 201756 kb
Host smart-74e091f0-9d9e-4e66-aed5-017ef7969589
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849985411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3849985411
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3652492712
Short name T729
Test name
Test status
Simulation time 110142376806 ps
CPU time 445.53 seconds
Started May 30 03:18:34 PM PDT 24
Finished May 30 03:26:01 PM PDT 24
Peak memory 202200 kb
Host smart-0d665448-bdec-46a0-bbd8-aed70a3be567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652492712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3652492712
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1205389953
Short name T544
Test name
Test status
Simulation time 26902522048 ps
CPU time 63.8 seconds
Started May 30 03:18:36 PM PDT 24
Finished May 30 03:19:40 PM PDT 24
Peak memory 201632 kb
Host smart-7de008e2-0a04-4708-883c-67e4f5673461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205389953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1205389953
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.633327403
Short name T565
Test name
Test status
Simulation time 3129165952 ps
CPU time 4.49 seconds
Started May 30 03:18:35 PM PDT 24
Finished May 30 03:18:40 PM PDT 24
Peak memory 201584 kb
Host smart-b64b4c6e-603f-46c4-b568-e2aedeb2db7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633327403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.633327403
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1531934702
Short name T432
Test name
Test status
Simulation time 5991912628 ps
CPU time 1.67 seconds
Started May 30 03:18:24 PM PDT 24
Finished May 30 03:18:26 PM PDT 24
Peak memory 201640 kb
Host smart-1421f71d-4017-43ee-b4fd-803008c34104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531934702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1531934702
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2529851706
Short name T122
Test name
Test status
Simulation time 335727763222 ps
CPU time 102.27 seconds
Started May 30 03:18:34 PM PDT 24
Finished May 30 03:20:17 PM PDT 24
Peak memory 201852 kb
Host smart-e53c575c-6aca-4fee-b172-05c5a0b60df3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529851706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2529851706
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2650549529
Short name T31
Test name
Test status
Simulation time 25043278179 ps
CPU time 61.43 seconds
Started May 30 03:18:34 PM PDT 24
Finished May 30 03:19:36 PM PDT 24
Peak memory 210408 kb
Host smart-0db7178c-87f7-4b9c-ad5d-efbb185e0349
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650549529 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2650549529
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1022573283
Short name T789
Test name
Test status
Simulation time 502633495 ps
CPU time 0.89 seconds
Started May 30 03:18:46 PM PDT 24
Finished May 30 03:18:49 PM PDT 24
Peak memory 201504 kb
Host smart-cc0e9a50-2d2f-454f-9a98-e9c1adb34326
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022573283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1022573283
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1970965106
Short name T795
Test name
Test status
Simulation time 320756457941 ps
CPU time 223.47 seconds
Started May 30 03:18:46 PM PDT 24
Finished May 30 03:22:31 PM PDT 24
Peak memory 201796 kb
Host smart-d715aa70-0f8d-4c09-bab9-02091050d78b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970965106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1970965106
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2531291178
Short name T595
Test name
Test status
Simulation time 489549908485 ps
CPU time 1124.8 seconds
Started May 30 03:18:47 PM PDT 24
Finished May 30 03:37:33 PM PDT 24
Peak memory 201976 kb
Host smart-4ec2e5ec-c966-42b0-965e-2e01d5e4d2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531291178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2531291178
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.17735232
Short name T148
Test name
Test status
Simulation time 160122948202 ps
CPU time 198.76 seconds
Started May 30 03:18:48 PM PDT 24
Finished May 30 03:22:08 PM PDT 24
Peak memory 201748 kb
Host smart-59ba86f9-18e0-4c55-bfba-93e310c8cf9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=17735232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt
_fixed.17735232
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3418246743
Short name T761
Test name
Test status
Simulation time 324809689272 ps
CPU time 802.36 seconds
Started May 30 03:18:35 PM PDT 24
Finished May 30 03:31:58 PM PDT 24
Peak memory 201776 kb
Host smart-927deb86-3335-4d2a-9398-a92f8774421b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418246743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3418246743
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3013347491
Short name T360
Test name
Test status
Simulation time 493251302436 ps
CPU time 1247.49 seconds
Started May 30 03:18:47 PM PDT 24
Finished May 30 03:39:36 PM PDT 24
Peak memory 201844 kb
Host smart-37f86ae2-a9d7-4225-8844-edf922f9d5ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013347491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3013347491
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3195367562
Short name T790
Test name
Test status
Simulation time 597768475928 ps
CPU time 729.39 seconds
Started May 30 03:18:48 PM PDT 24
Finished May 30 03:30:59 PM PDT 24
Peak memory 201876 kb
Host smart-3149ae73-2269-44e7-9956-af50f90ef944
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195367562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3195367562
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3021054701
Short name T511
Test name
Test status
Simulation time 109392758101 ps
CPU time 593.15 seconds
Started May 30 03:18:46 PM PDT 24
Finished May 30 03:28:40 PM PDT 24
Peak memory 202204 kb
Host smart-9a7193d8-aac7-4f68-9c8e-a6bd3275f745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021054701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3021054701
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.389263816
Short name T419
Test name
Test status
Simulation time 39313165277 ps
CPU time 38.4 seconds
Started May 30 03:18:49 PM PDT 24
Finished May 30 03:19:29 PM PDT 24
Peak memory 201612 kb
Host smart-c9518f4c-8e14-4c7b-ad0c-6bc4f892e30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389263816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.389263816
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2138218936
Short name T547
Test name
Test status
Simulation time 4800617346 ps
CPU time 12.36 seconds
Started May 30 03:18:47 PM PDT 24
Finished May 30 03:19:00 PM PDT 24
Peak memory 201624 kb
Host smart-9444a15e-582a-42f7-8611-0bb36cd06cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138218936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2138218936
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.966073115
Short name T554
Test name
Test status
Simulation time 5823140012 ps
CPU time 13.97 seconds
Started May 30 03:18:34 PM PDT 24
Finished May 30 03:18:49 PM PDT 24
Peak memory 201620 kb
Host smart-aaa46e87-80ee-412e-a5bf-6f964d5657ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966073115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.966073115
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2433426120
Short name T6
Test name
Test status
Simulation time 495707250048 ps
CPU time 266.53 seconds
Started May 30 03:18:48 PM PDT 24
Finished May 30 03:23:16 PM PDT 24
Peak memory 201868 kb
Host smart-79e282f1-5a30-4938-9563-46f22e8924f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433426120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2433426120
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2016253553
Short name T250
Test name
Test status
Simulation time 52001751442 ps
CPU time 61.08 seconds
Started May 30 03:18:47 PM PDT 24
Finished May 30 03:19:49 PM PDT 24
Peak memory 211216 kb
Host smart-b3aad727-82bc-4c01-bc73-fcc773c472b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016253553 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2016253553
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1523045891
Short name T418
Test name
Test status
Simulation time 295563013 ps
CPU time 1.25 seconds
Started May 30 03:19:28 PM PDT 24
Finished May 30 03:19:30 PM PDT 24
Peak memory 201516 kb
Host smart-bceecb90-760d-4f07-8630-6169dec7a8e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523045891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1523045891
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.174211971
Short name T75
Test name
Test status
Simulation time 214913181357 ps
CPU time 118.52 seconds
Started May 30 03:18:58 PM PDT 24
Finished May 30 03:20:58 PM PDT 24
Peak memory 201820 kb
Host smart-86eff867-8957-48da-8fb7-b1835fad4737
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174211971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.174211971
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2764062441
Short name T652
Test name
Test status
Simulation time 359986650081 ps
CPU time 459.18 seconds
Started May 30 03:18:55 PM PDT 24
Finished May 30 03:26:36 PM PDT 24
Peak memory 201804 kb
Host smart-ff09fd43-0450-49c1-836b-2cb8b65aaba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764062441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2764062441
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.267097876
Short name T404
Test name
Test status
Simulation time 330381169374 ps
CPU time 197.31 seconds
Started May 30 03:18:56 PM PDT 24
Finished May 30 03:22:14 PM PDT 24
Peak memory 201784 kb
Host smart-0d75e7d8-105f-4ee8-a9b4-f659c0c156ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=267097876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.267097876
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.1958943550
Short name T416
Test name
Test status
Simulation time 493445492908 ps
CPU time 1096.15 seconds
Started May 30 03:18:55 PM PDT 24
Finished May 30 03:37:12 PM PDT 24
Peak memory 201872 kb
Host smart-2b94fe65-040c-4696-8465-8d45772eea3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958943550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1958943550
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3403088454
Short name T481
Test name
Test status
Simulation time 491653553999 ps
CPU time 1186.94 seconds
Started May 30 03:18:58 PM PDT 24
Finished May 30 03:38:46 PM PDT 24
Peak memory 201756 kb
Host smart-a6cecdce-c088-4d74-860b-50a1323ab54f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403088454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3403088454
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1385532555
Short name T291
Test name
Test status
Simulation time 355940007127 ps
CPU time 837.86 seconds
Started May 30 03:18:58 PM PDT 24
Finished May 30 03:32:56 PM PDT 24
Peak memory 201844 kb
Host smart-8a52836d-30db-4393-8ca0-5ef4325f62a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385532555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1385532555
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2885936433
Short name T702
Test name
Test status
Simulation time 197117389045 ps
CPU time 218.09 seconds
Started May 30 03:18:56 PM PDT 24
Finished May 30 03:22:35 PM PDT 24
Peak memory 201808 kb
Host smart-8aa1d84a-ef6b-4873-9ecf-575ed62f78ef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885936433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.2885936433
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2767595608
Short name T440
Test name
Test status
Simulation time 106630277231 ps
CPU time 555.23 seconds
Started May 30 03:19:16 PM PDT 24
Finished May 30 03:28:32 PM PDT 24
Peak memory 202068 kb
Host smart-41f84709-1faa-452f-adc0-572c7370bbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767595608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2767595608
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2005457364
Short name T769
Test name
Test status
Simulation time 44276042315 ps
CPU time 102.04 seconds
Started May 30 03:19:13 PM PDT 24
Finished May 30 03:20:57 PM PDT 24
Peak memory 201632 kb
Host smart-64fc23d2-eeb7-4daf-b89f-e90fdfbb4666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005457364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2005457364
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.238191054
Short name T739
Test name
Test status
Simulation time 3974815568 ps
CPU time 1.94 seconds
Started May 30 03:19:13 PM PDT 24
Finished May 30 03:19:16 PM PDT 24
Peak memory 201656 kb
Host smart-27f0b22e-2d51-4563-ad59-94908a7564e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238191054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.238191054
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.4201210921
Short name T430
Test name
Test status
Simulation time 5635908681 ps
CPU time 3.45 seconds
Started May 30 03:18:59 PM PDT 24
Finished May 30 03:19:03 PM PDT 24
Peak memory 201652 kb
Host smart-8610e62d-d938-4c32-8758-a0f337254e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201210921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.4201210921
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.810868264
Short name T21
Test name
Test status
Simulation time 57913923400 ps
CPU time 68.76 seconds
Started May 30 03:19:14 PM PDT 24
Finished May 30 03:20:24 PM PDT 24
Peak memory 210104 kb
Host smart-d1e09740-adf6-4442-9194-b1fce60c802a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810868264 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.810868264
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3176556373
Short name T742
Test name
Test status
Simulation time 533170376 ps
CPU time 1.3 seconds
Started May 30 03:19:35 PM PDT 24
Finished May 30 03:19:37 PM PDT 24
Peak memory 201520 kb
Host smart-b6e8a845-1d59-48e3-b7c7-12adf7e26b70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176556373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3176556373
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2388165184
Short name T235
Test name
Test status
Simulation time 190843672154 ps
CPU time 31.65 seconds
Started May 30 03:19:27 PM PDT 24
Finished May 30 03:20:00 PM PDT 24
Peak memory 201852 kb
Host smart-bfa55f1d-b293-4596-a3f2-70048ee5e6de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388165184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2388165184
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1150736746
Short name T150
Test name
Test status
Simulation time 511608787919 ps
CPU time 144.74 seconds
Started May 30 03:19:24 PM PDT 24
Finished May 30 03:21:50 PM PDT 24
Peak memory 201804 kb
Host smart-a370f810-141a-45cc-8885-f38f4479c234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150736746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1150736746
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2183526352
Short name T216
Test name
Test status
Simulation time 334432298018 ps
CPU time 427.23 seconds
Started May 30 03:19:27 PM PDT 24
Finished May 30 03:26:36 PM PDT 24
Peak memory 201892 kb
Host smart-ed0fa70b-6449-4ec4-9aec-00463602bb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183526352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2183526352
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3763742021
Short name T374
Test name
Test status
Simulation time 326901753335 ps
CPU time 359.83 seconds
Started May 30 03:19:28 PM PDT 24
Finished May 30 03:25:29 PM PDT 24
Peak memory 201808 kb
Host smart-02301bee-7b23-4065-a433-d9cfe992fdf8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763742021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3763742021
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3064074671
Short name T752
Test name
Test status
Simulation time 482992249845 ps
CPU time 528.04 seconds
Started May 30 03:19:25 PM PDT 24
Finished May 30 03:28:14 PM PDT 24
Peak memory 201860 kb
Host smart-0a58d62c-50e3-42be-986d-fd4bb30038a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064074671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3064074671
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.800495110
Short name T683
Test name
Test status
Simulation time 487982709287 ps
CPU time 280.68 seconds
Started May 30 03:19:24 PM PDT 24
Finished May 30 03:24:06 PM PDT 24
Peak memory 201780 kb
Host smart-68af620c-8435-41bc-bcf3-fa91bf230b59
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=800495110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.800495110
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3677995900
Short name T290
Test name
Test status
Simulation time 187735755349 ps
CPU time 427.86 seconds
Started May 30 03:19:24 PM PDT 24
Finished May 30 03:26:33 PM PDT 24
Peak memory 201800 kb
Host smart-0d99f37b-6e8e-489f-95d0-8aeae0ce3990
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677995900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3677995900
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2108113465
Short name T381
Test name
Test status
Simulation time 586902973890 ps
CPU time 1314.71 seconds
Started May 30 03:19:26 PM PDT 24
Finished May 30 03:41:22 PM PDT 24
Peak memory 201816 kb
Host smart-aef981e9-3c2f-43e2-a7b6-17912ad82e6f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108113465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2108113465
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1342207144
Short name T562
Test name
Test status
Simulation time 98758851091 ps
CPU time 474.79 seconds
Started May 30 03:19:25 PM PDT 24
Finished May 30 03:27:21 PM PDT 24
Peak memory 202148 kb
Host smart-bb6febfe-b8e6-4a17-9927-bc41d7e7175b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342207144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1342207144
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.883120417
Short name T672
Test name
Test status
Simulation time 27917535877 ps
CPU time 31.37 seconds
Started May 30 03:19:25 PM PDT 24
Finished May 30 03:19:57 PM PDT 24
Peak memory 201580 kb
Host smart-f777f147-4147-4e85-8a11-0b473b87f811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883120417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.883120417
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.3846427548
Short name T509
Test name
Test status
Simulation time 2847547736 ps
CPU time 2.39 seconds
Started May 30 03:19:24 PM PDT 24
Finished May 30 03:19:27 PM PDT 24
Peak memory 201624 kb
Host smart-d14c0aa9-36c6-4959-ae22-1bbba3bd32d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846427548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.3846427548
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2541678510
Short name T119
Test name
Test status
Simulation time 5953085207 ps
CPU time 8.11 seconds
Started May 30 03:19:25 PM PDT 24
Finished May 30 03:19:34 PM PDT 24
Peak memory 201632 kb
Host smart-ed2b71aa-edeb-4cf2-92be-fc4fdc0743d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541678510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2541678510
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.324639786
Short name T25
Test name
Test status
Simulation time 498194662555 ps
CPU time 1093.39 seconds
Started May 30 03:19:27 PM PDT 24
Finished May 30 03:37:41 PM PDT 24
Peak memory 201816 kb
Host smart-562f2032-d36b-4f6d-b91d-8b919866d8b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324639786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
324639786
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3548185705
Short name T439
Test name
Test status
Simulation time 7783499359 ps
CPU time 19.53 seconds
Started May 30 03:19:27 PM PDT 24
Finished May 30 03:19:48 PM PDT 24
Peak memory 201984 kb
Host smart-be7e7b96-0728-4e9c-b645-c92397c07672
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548185705 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3548185705
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2741441651
Short name T630
Test name
Test status
Simulation time 308393570 ps
CPU time 1.36 seconds
Started May 30 03:19:45 PM PDT 24
Finished May 30 03:19:47 PM PDT 24
Peak memory 201516 kb
Host smart-74e26998-b870-457f-9c28-10265f3c6b9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741441651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2741441651
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3872537676
Short name T605
Test name
Test status
Simulation time 160875807822 ps
CPU time 93.83 seconds
Started May 30 03:19:36 PM PDT 24
Finished May 30 03:21:11 PM PDT 24
Peak memory 201884 kb
Host smart-59180ad3-774f-4b7c-85c5-3a20a846f4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872537676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3872537676
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2343342900
Short name T698
Test name
Test status
Simulation time 325051032370 ps
CPU time 304.93 seconds
Started May 30 03:19:35 PM PDT 24
Finished May 30 03:24:41 PM PDT 24
Peak memory 201808 kb
Host smart-bf2211b3-2ba3-4197-9b5d-3e32c0789537
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343342900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2343342900
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.72945369
Short name T168
Test name
Test status
Simulation time 337421941972 ps
CPU time 71.45 seconds
Started May 30 03:19:37 PM PDT 24
Finished May 30 03:20:49 PM PDT 24
Peak memory 201824 kb
Host smart-987e3e5b-5df1-4896-b0c6-e560f37c8196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72945369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.72945369
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3230104644
Short name T335
Test name
Test status
Simulation time 486729811603 ps
CPU time 1202.43 seconds
Started May 30 03:19:35 PM PDT 24
Finished May 30 03:39:38 PM PDT 24
Peak memory 201752 kb
Host smart-7b7c06dc-9781-4176-ab7d-a2fe6c5f3004
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230104644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3230104644
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.448867814
Short name T607
Test name
Test status
Simulation time 400202928383 ps
CPU time 919.62 seconds
Started May 30 03:19:47 PM PDT 24
Finished May 30 03:35:07 PM PDT 24
Peak memory 201784 kb
Host smart-5ee2b114-f261-41c7-b6c5-42fe23f5ebab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448867814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.448867814
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.3915604583
Short name T326
Test name
Test status
Simulation time 81443664185 ps
CPU time 338.32 seconds
Started May 30 03:19:46 PM PDT 24
Finished May 30 03:25:26 PM PDT 24
Peak memory 202196 kb
Host smart-cfbbd0c1-abf2-40ba-b985-6efd2a91e13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915604583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.3915604583
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1555823045
Short name T435
Test name
Test status
Simulation time 45966727578 ps
CPU time 20.34 seconds
Started May 30 03:19:47 PM PDT 24
Finished May 30 03:20:08 PM PDT 24
Peak memory 201640 kb
Host smart-18272664-8ed5-4b4a-ac56-f11517ca6b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555823045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1555823045
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.111578087
Short name T594
Test name
Test status
Simulation time 3305603080 ps
CPU time 4.51 seconds
Started May 30 03:19:45 PM PDT 24
Finished May 30 03:19:50 PM PDT 24
Peak memory 201584 kb
Host smart-0f977eda-e8e4-4a21-ba4a-09233d25ccb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111578087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.111578087
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3124712211
Short name T763
Test name
Test status
Simulation time 5867447966 ps
CPU time 5.82 seconds
Started May 30 03:19:35 PM PDT 24
Finished May 30 03:19:42 PM PDT 24
Peak memory 201636 kb
Host smart-d7d7a11a-42a3-41be-9b4d-dd1e121a720b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124712211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3124712211
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.2607962964
Short name T746
Test name
Test status
Simulation time 176197887898 ps
CPU time 110.23 seconds
Started May 30 03:19:45 PM PDT 24
Finished May 30 03:21:36 PM PDT 24
Peak memory 201868 kb
Host smart-198a6754-863d-4431-9d60-0b314a17915a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607962964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.2607962964
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2531831668
Short name T238
Test name
Test status
Simulation time 56828879996 ps
CPU time 127.87 seconds
Started May 30 03:19:46 PM PDT 24
Finished May 30 03:21:55 PM PDT 24
Peak memory 210424 kb
Host smart-54e26070-591f-4060-8fa1-e0afa8c08e34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531831668 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2531831668
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1464834925
Short name T475
Test name
Test status
Simulation time 515701074 ps
CPU time 0.72 seconds
Started May 30 03:20:07 PM PDT 24
Finished May 30 03:20:09 PM PDT 24
Peak memory 201468 kb
Host smart-ee55437e-cc20-4d5e-927e-5150fe3071a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464834925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1464834925
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2167303706
Short name T262
Test name
Test status
Simulation time 203066009589 ps
CPU time 497.25 seconds
Started May 30 03:19:57 PM PDT 24
Finished May 30 03:28:17 PM PDT 24
Peak memory 201892 kb
Host smart-5e817b54-ac32-4d7c-bcef-0b8291e24b0e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167303706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2167303706
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.430415688
Short name T267
Test name
Test status
Simulation time 325890897716 ps
CPU time 796.82 seconds
Started May 30 03:19:57 PM PDT 24
Finished May 30 03:33:16 PM PDT 24
Peak memory 201784 kb
Host smart-b9b393e4-4764-42c4-ba2d-afa5a9236201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430415688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.430415688
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.665802682
Short name T732
Test name
Test status
Simulation time 491729581661 ps
CPU time 271.32 seconds
Started May 30 03:19:56 PM PDT 24
Finished May 30 03:24:29 PM PDT 24
Peak memory 201844 kb
Host smart-91830f29-d19a-4131-984e-e34fbc3272ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=665802682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.665802682
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1163227271
Short name T308
Test name
Test status
Simulation time 493651841412 ps
CPU time 316.79 seconds
Started May 30 03:19:57 PM PDT 24
Finished May 30 03:25:16 PM PDT 24
Peak memory 201804 kb
Host smart-fc2a9c60-03e2-4cbf-9e79-0da3ea796e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163227271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1163227271
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2100706162
Short name T494
Test name
Test status
Simulation time 491166976074 ps
CPU time 223.54 seconds
Started May 30 03:19:56 PM PDT 24
Finished May 30 03:23:42 PM PDT 24
Peak memory 201772 kb
Host smart-9e023046-882d-4458-8296-3882d6988791
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100706162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2100706162
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3409324688
Short name T682
Test name
Test status
Simulation time 182030306876 ps
CPU time 108.58 seconds
Started May 30 03:19:56 PM PDT 24
Finished May 30 03:21:47 PM PDT 24
Peak memory 201900 kb
Host smart-c24772c4-3de3-4d32-a6a4-69678317b55b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409324688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3409324688
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1011960698
Short name T383
Test name
Test status
Simulation time 401237837255 ps
CPU time 844.52 seconds
Started May 30 03:19:57 PM PDT 24
Finished May 30 03:34:04 PM PDT 24
Peak memory 201832 kb
Host smart-4fcae647-0f02-482d-abfd-5e27bc5c57ca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011960698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1011960698
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3746870670
Short name T598
Test name
Test status
Simulation time 124654154497 ps
CPU time 556.22 seconds
Started May 30 03:19:56 PM PDT 24
Finished May 30 03:29:14 PM PDT 24
Peak memory 202196 kb
Host smart-b5f6ef75-ea02-4f0f-9217-2cc572c70f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746870670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3746870670
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.4212571664
Short name T146
Test name
Test status
Simulation time 45250736954 ps
CPU time 16.46 seconds
Started May 30 03:19:56 PM PDT 24
Finished May 30 03:20:14 PM PDT 24
Peak memory 201604 kb
Host smart-d3e82908-7345-430a-9efd-16134a8d5bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212571664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.4212571664
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1982598315
Short name T587
Test name
Test status
Simulation time 2838371565 ps
CPU time 6.88 seconds
Started May 30 03:19:57 PM PDT 24
Finished May 30 03:20:06 PM PDT 24
Peak memory 201608 kb
Host smart-879a0973-884c-497a-a46f-0ce1ba625760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982598315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1982598315
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3753136508
Short name T723
Test name
Test status
Simulation time 5758202930 ps
CPU time 14.61 seconds
Started May 30 03:19:57 PM PDT 24
Finished May 30 03:20:14 PM PDT 24
Peak memory 201604 kb
Host smart-bf574356-ab65-4afd-845c-2de53c02d59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753136508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3753136508
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.4083756624
Short name T29
Test name
Test status
Simulation time 44373597999 ps
CPU time 92.72 seconds
Started May 30 03:19:56 PM PDT 24
Finished May 30 03:21:31 PM PDT 24
Peak memory 202108 kb
Host smart-772df001-7365-4f56-806a-4747fd34cb52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083756624 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.4083756624
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1077899812
Short name T366
Test name
Test status
Simulation time 490509548 ps
CPU time 0.97 seconds
Started May 30 03:20:18 PM PDT 24
Finished May 30 03:20:21 PM PDT 24
Peak memory 201516 kb
Host smart-784d910b-037b-454f-b77b-45cc25ab1294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077899812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1077899812
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3218608934
Short name T670
Test name
Test status
Simulation time 191609835505 ps
CPU time 240.06 seconds
Started May 30 03:20:19 PM PDT 24
Finished May 30 03:24:20 PM PDT 24
Peak memory 201828 kb
Host smart-b3eb6cc6-2860-4914-8315-10ee6bd82ac8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218608934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3218608934
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2940866113
Short name T650
Test name
Test status
Simulation time 328217863022 ps
CPU time 195.64 seconds
Started May 30 03:20:19 PM PDT 24
Finished May 30 03:23:35 PM PDT 24
Peak memory 201816 kb
Host smart-cdd8ae4c-5c0f-4a86-8731-32a86f402e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940866113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2940866113
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.746237427
Short name T493
Test name
Test status
Simulation time 161846095982 ps
CPU time 395.55 seconds
Started May 30 03:20:19 PM PDT 24
Finished May 30 03:26:56 PM PDT 24
Peak memory 201796 kb
Host smart-c1f0cd30-17a4-4f36-9e03-ca98b490cf7c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=746237427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.746237427
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2371454961
Short name T571
Test name
Test status
Simulation time 328294292228 ps
CPU time 389.54 seconds
Started May 30 03:20:08 PM PDT 24
Finished May 30 03:26:38 PM PDT 24
Peak memory 201736 kb
Host smart-911beac2-126a-4430-bef9-7154127e5f53
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371454961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2371454961
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.4221405519
Short name T768
Test name
Test status
Simulation time 565766494055 ps
CPU time 116.51 seconds
Started May 30 03:20:19 PM PDT 24
Finished May 30 03:22:17 PM PDT 24
Peak memory 201888 kb
Host smart-cad4259a-b45c-4460-9273-1c04e750b06e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221405519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.4221405519
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3908604283
Short name T343
Test name
Test status
Simulation time 206102788224 ps
CPU time 498.9 seconds
Started May 30 03:20:18 PM PDT 24
Finished May 30 03:28:38 PM PDT 24
Peak memory 201808 kb
Host smart-8ef242ae-4803-4665-a4f8-ae5d2bccd410
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908604283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.3908604283
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.673006625
Short name T191
Test name
Test status
Simulation time 105473005252 ps
CPU time 541.92 seconds
Started May 30 03:20:19 PM PDT 24
Finished May 30 03:29:22 PM PDT 24
Peak memory 202140 kb
Host smart-941d03d5-1c26-4b4d-9333-b8446bb4d00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673006625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.673006625
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2497099437
Short name T519
Test name
Test status
Simulation time 34977353306 ps
CPU time 6.81 seconds
Started May 30 03:20:18 PM PDT 24
Finished May 30 03:20:26 PM PDT 24
Peak memory 201652 kb
Host smart-ce1836ca-f494-410f-b172-e7d565314c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497099437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2497099437
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2664659409
Short name T692
Test name
Test status
Simulation time 4277833075 ps
CPU time 10.41 seconds
Started May 30 03:20:18 PM PDT 24
Finished May 30 03:20:29 PM PDT 24
Peak memory 201624 kb
Host smart-a40d10fb-1c3c-4d31-ba54-67e2836f233b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664659409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2664659409
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1220392989
Short name T802
Test name
Test status
Simulation time 5590576706 ps
CPU time 15.74 seconds
Started May 30 03:20:07 PM PDT 24
Finished May 30 03:20:24 PM PDT 24
Peak memory 201652 kb
Host smart-7075b882-1199-4715-9fa0-c8226894798b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220392989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1220392989
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1762811942
Short name T179
Test name
Test status
Simulation time 265225604567 ps
CPU time 248.22 seconds
Started May 30 03:20:18 PM PDT 24
Finished May 30 03:24:28 PM PDT 24
Peak memory 217820 kb
Host smart-bd777a87-8bbf-414d-8372-636904ffe9ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762811942 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1762811942
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2803892139
Short name T380
Test name
Test status
Simulation time 468561464 ps
CPU time 1.73 seconds
Started May 30 03:20:31 PM PDT 24
Finished May 30 03:20:35 PM PDT 24
Peak memory 201480 kb
Host smart-ef2a97ae-aa1c-4a36-a377-ef25ea914697
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803892139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2803892139
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3647038072
Short name T169
Test name
Test status
Simulation time 335214884136 ps
CPU time 111.07 seconds
Started May 30 03:20:32 PM PDT 24
Finished May 30 03:22:25 PM PDT 24
Peak memory 201756 kb
Host smart-704c7d4e-97c5-417f-918e-513a72d6e638
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647038072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3647038072
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.4197720961
Short name T247
Test name
Test status
Simulation time 397038838498 ps
CPU time 83.21 seconds
Started May 30 03:20:32 PM PDT 24
Finished May 30 03:21:57 PM PDT 24
Peak memory 201796 kb
Host smart-6596491c-b414-46d2-bed3-9193e831a26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197720961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.4197720961
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.4189043900
Short name T800
Test name
Test status
Simulation time 164431579736 ps
CPU time 205.59 seconds
Started May 30 03:20:32 PM PDT 24
Finished May 30 03:24:00 PM PDT 24
Peak memory 201640 kb
Host smart-b53321b2-2b85-404f-badc-e235ff1fe651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189043900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.4189043900
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2710319923
Short name T385
Test name
Test status
Simulation time 331433728138 ps
CPU time 804.75 seconds
Started May 30 03:20:31 PM PDT 24
Finished May 30 03:33:58 PM PDT 24
Peak memory 201856 kb
Host smart-fb89c379-867f-4ace-b2ac-3234bf3740b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710319923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2710319923
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1408798296
Short name T359
Test name
Test status
Simulation time 163494876003 ps
CPU time 96.12 seconds
Started May 30 03:20:31 PM PDT 24
Finished May 30 03:22:09 PM PDT 24
Peak memory 201760 kb
Host smart-92ca78a4-7764-4466-b974-bb0ded4da203
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408798296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1408798296
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.768423329
Short name T358
Test name
Test status
Simulation time 388115835178 ps
CPU time 245.31 seconds
Started May 30 03:20:33 PM PDT 24
Finished May 30 03:24:40 PM PDT 24
Peak memory 201804 kb
Host smart-9baed07b-1e2f-47dc-89e3-5bbf804f4845
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768423329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.768423329
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.40433897
Short name T424
Test name
Test status
Simulation time 117238278254 ps
CPU time 382.4 seconds
Started May 30 03:20:32 PM PDT 24
Finished May 30 03:26:56 PM PDT 24
Peak memory 202108 kb
Host smart-83041950-612f-4d0a-80e2-134b498ddc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40433897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.40433897
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3873074985
Short name T779
Test name
Test status
Simulation time 42500074450 ps
CPU time 29.94 seconds
Started May 30 03:20:31 PM PDT 24
Finished May 30 03:21:03 PM PDT 24
Peak memory 201676 kb
Host smart-72642e6d-ae05-4a7e-b4f8-1846a6f3939f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873074985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3873074985
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3358176375
Short name T735
Test name
Test status
Simulation time 4565572132 ps
CPU time 5.85 seconds
Started May 30 03:20:31 PM PDT 24
Finished May 30 03:20:39 PM PDT 24
Peak memory 201644 kb
Host smart-864ddffe-0b80-4b52-9e52-cf4499adf55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358176375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3358176375
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1257248210
Short name T131
Test name
Test status
Simulation time 6127652652 ps
CPU time 7.87 seconds
Started May 30 03:20:19 PM PDT 24
Finished May 30 03:20:28 PM PDT 24
Peak memory 201596 kb
Host smart-5caf7396-fbaf-43d1-a1e6-b26ceb9536ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257248210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1257248210
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2302616587
Short name T91
Test name
Test status
Simulation time 42845274037 ps
CPU time 104.4 seconds
Started May 30 03:20:32 PM PDT 24
Finished May 30 03:22:18 PM PDT 24
Peak memory 211864 kb
Host smart-cad7b28f-8082-4d93-a334-6af9ed16904e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302616587 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2302616587
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3486159243
Short name T376
Test name
Test status
Simulation time 393313263 ps
CPU time 1.55 seconds
Started May 30 03:20:44 PM PDT 24
Finished May 30 03:20:46 PM PDT 24
Peak memory 201520 kb
Host smart-04fea967-3d5e-4ee8-b123-832473fa7f86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486159243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3486159243
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.556940371
Short name T527
Test name
Test status
Simulation time 199112847299 ps
CPU time 181.48 seconds
Started May 30 03:20:42 PM PDT 24
Finished May 30 03:23:45 PM PDT 24
Peak memory 201816 kb
Host smart-b7a42758-44c9-466a-9bd4-09f174e57578
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556940371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.556940371
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2934401683
Short name T558
Test name
Test status
Simulation time 556986107279 ps
CPU time 643.57 seconds
Started May 30 03:20:44 PM PDT 24
Finished May 30 03:31:28 PM PDT 24
Peak memory 201800 kb
Host smart-08a5fe80-5e96-4327-b67c-e1d32cf18ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934401683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2934401683
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2254571934
Short name T23
Test name
Test status
Simulation time 156646531232 ps
CPU time 72.51 seconds
Started May 30 03:20:44 PM PDT 24
Finished May 30 03:21:57 PM PDT 24
Peak memory 201816 kb
Host smart-118ac92a-b9a8-4bd1-a10c-3a41274b8aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254571934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2254571934
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2547828501
Short name T9
Test name
Test status
Simulation time 161650538068 ps
CPU time 198.49 seconds
Started May 30 03:20:42 PM PDT 24
Finished May 30 03:24:02 PM PDT 24
Peak memory 201860 kb
Host smart-502ecd60-395f-40d6-afc8-4c1b9e0d1efa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547828501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2547828501
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3773534272
Short name T455
Test name
Test status
Simulation time 328979418914 ps
CPU time 177.01 seconds
Started May 30 03:20:43 PM PDT 24
Finished May 30 03:23:41 PM PDT 24
Peak memory 201768 kb
Host smart-75fbb177-bb3e-4779-8cbc-fa4e2f7330c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773534272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3773534272
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3961380813
Short name T170
Test name
Test status
Simulation time 422362312299 ps
CPU time 149.45 seconds
Started May 30 03:20:43 PM PDT 24
Finished May 30 03:23:13 PM PDT 24
Peak memory 201764 kb
Host smart-35316687-bb89-4283-9a06-3d32ad060874
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961380813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3961380813
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3890019644
Short name T467
Test name
Test status
Simulation time 420766130266 ps
CPU time 249.18 seconds
Started May 30 03:20:41 PM PDT 24
Finished May 30 03:24:51 PM PDT 24
Peak memory 201804 kb
Host smart-88896e0e-1fe1-4a8b-bce1-bd4d5e670125
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890019644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3890019644
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3842576605
Short name T322
Test name
Test status
Simulation time 92522194063 ps
CPU time 376.77 seconds
Started May 30 03:20:42 PM PDT 24
Finished May 30 03:27:00 PM PDT 24
Peak memory 202200 kb
Host smart-27d91f1e-320e-43f8-a640-7431020bb349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842576605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3842576605
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.3303349848
Short name T414
Test name
Test status
Simulation time 44316710244 ps
CPU time 99.79 seconds
Started May 30 03:20:43 PM PDT 24
Finished May 30 03:22:24 PM PDT 24
Peak memory 201608 kb
Host smart-3fe558a8-2007-4a49-afcf-3648aa5f7984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303349848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3303349848
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3834616702
Short name T580
Test name
Test status
Simulation time 2804320196 ps
CPU time 7.34 seconds
Started May 30 03:20:44 PM PDT 24
Finished May 30 03:20:52 PM PDT 24
Peak memory 201632 kb
Host smart-e2cc3ce8-aa5a-4504-8eb5-750d3bb982f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834616702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3834616702
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2045607555
Short name T671
Test name
Test status
Simulation time 5947852790 ps
CPU time 7.19 seconds
Started May 30 03:20:43 PM PDT 24
Finished May 30 03:20:51 PM PDT 24
Peak memory 201588 kb
Host smart-8c87d060-14e8-48fa-92ae-8621ae180b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045607555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2045607555
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.4064780530
Short name T506
Test name
Test status
Simulation time 248043646302 ps
CPU time 762.84 seconds
Started May 30 03:20:45 PM PDT 24
Finished May 30 03:33:28 PM PDT 24
Peak memory 202052 kb
Host smart-9ca65a27-aff0-415e-9a02-c1c17e1274de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064780530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.4064780530
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1716595870
Short name T588
Test name
Test status
Simulation time 49817034098 ps
CPU time 56.05 seconds
Started May 30 03:20:42 PM PDT 24
Finished May 30 03:21:39 PM PDT 24
Peak memory 201972 kb
Host smart-40e8b2b7-24ca-41ff-8a5b-7222c1299949
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716595870 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1716595870
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.350707344
Short name T656
Test name
Test status
Simulation time 497893013 ps
CPU time 0.88 seconds
Started May 30 03:14:46 PM PDT 24
Finished May 30 03:14:48 PM PDT 24
Peak memory 201468 kb
Host smart-fcdaaadc-39f5-4081-b223-2cba203b5279
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350707344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.350707344
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1712295784
Short name T201
Test name
Test status
Simulation time 157984286439 ps
CPU time 92.82 seconds
Started May 30 03:14:38 PM PDT 24
Finished May 30 03:16:12 PM PDT 24
Peak memory 201884 kb
Host smart-391314c6-dacb-4d2e-b5b5-87f363103690
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712295784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1712295784
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2674702406
Short name T423
Test name
Test status
Simulation time 169274834778 ps
CPU time 385.13 seconds
Started May 30 03:14:35 PM PDT 24
Finished May 30 03:21:02 PM PDT 24
Peak memory 201820 kb
Host smart-640f4d6f-01eb-44ef-8a76-6ec99d1a58ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674702406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2674702406
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2687375753
Short name T699
Test name
Test status
Simulation time 329662985916 ps
CPU time 201.02 seconds
Started May 30 03:14:39 PM PDT 24
Finished May 30 03:18:01 PM PDT 24
Peak memory 201792 kb
Host smart-60333855-5fa8-4c3a-b207-1a9002b843e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687375753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2687375753
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.509516306
Short name T11
Test name
Test status
Simulation time 327017891998 ps
CPU time 125.37 seconds
Started May 30 03:14:36 PM PDT 24
Finished May 30 03:16:42 PM PDT 24
Peak memory 201804 kb
Host smart-d05b4a26-6af4-4628-ad9f-a8c5ccc1c30b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=509516306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.509516306
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1658327003
Short name T281
Test name
Test status
Simulation time 170822485113 ps
CPU time 101.27 seconds
Started May 30 03:14:37 PM PDT 24
Finished May 30 03:16:20 PM PDT 24
Peak memory 201772 kb
Host smart-f9eaede5-82e2-449a-bb44-d58f890ded57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658327003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1658327003
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3080202422
Short name T437
Test name
Test status
Simulation time 488935241220 ps
CPU time 557.67 seconds
Started May 30 03:14:36 PM PDT 24
Finished May 30 03:23:55 PM PDT 24
Peak memory 201884 kb
Host smart-e6ab34cb-c3b7-4a2e-ac02-08e4239e05f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080202422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3080202422
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1962496093
Short name T286
Test name
Test status
Simulation time 534445162044 ps
CPU time 339.69 seconds
Started May 30 03:14:37 PM PDT 24
Finished May 30 03:20:18 PM PDT 24
Peak memory 201916 kb
Host smart-6385f148-19f2-4064-bc6d-b793c07124e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962496093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1962496093
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2791370000
Short name T388
Test name
Test status
Simulation time 206047509953 ps
CPU time 251.65 seconds
Started May 30 03:14:36 PM PDT 24
Finished May 30 03:18:49 PM PDT 24
Peak memory 201788 kb
Host smart-625c61e8-f8df-474a-b352-114d97c4ea28
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791370000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2791370000
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.2004474779
Short name T669
Test name
Test status
Simulation time 92506583613 ps
CPU time 287.51 seconds
Started May 30 03:14:38 PM PDT 24
Finished May 30 03:19:27 PM PDT 24
Peak memory 202124 kb
Host smart-5f81213a-3146-4436-9eb5-57be1210a50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004474779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2004474779
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2983417039
Short name T329
Test name
Test status
Simulation time 42841562349 ps
CPU time 90.38 seconds
Started May 30 03:14:35 PM PDT 24
Finished May 30 03:16:07 PM PDT 24
Peak memory 201592 kb
Host smart-12a33e95-69ee-4f0e-a7aa-037b90c01893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983417039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2983417039
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1325172059
Short name T426
Test name
Test status
Simulation time 3962747563 ps
CPU time 9.47 seconds
Started May 30 03:14:35 PM PDT 24
Finished May 30 03:14:46 PM PDT 24
Peak memory 201636 kb
Host smart-95958ffa-1968-498a-885c-f8f17a740e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325172059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1325172059
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1736014160
Short name T53
Test name
Test status
Simulation time 4156938760 ps
CPU time 5.85 seconds
Started May 30 03:14:36 PM PDT 24
Finished May 30 03:14:43 PM PDT 24
Peak memory 217308 kb
Host smart-b7a236cd-6b82-488f-9ce8-5ed7f1d26349
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736014160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1736014160
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1033386253
Short name T128
Test name
Test status
Simulation time 5956244534 ps
CPU time 14.26 seconds
Started May 30 03:14:36 PM PDT 24
Finished May 30 03:14:52 PM PDT 24
Peak memory 201636 kb
Host smart-fa3ebab2-0353-41d4-ba14-43fb1681e3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033386253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1033386253
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2322978102
Short name T757
Test name
Test status
Simulation time 170820766811 ps
CPU time 417.95 seconds
Started May 30 03:14:36 PM PDT 24
Finished May 30 03:21:35 PM PDT 24
Peak memory 201816 kb
Host smart-d8c694d0-d50e-42e2-9fbb-d55eca401acd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322978102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2322978102
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3835620666
Short name T61
Test name
Test status
Simulation time 402482541 ps
CPU time 0.86 seconds
Started May 30 03:21:03 PM PDT 24
Finished May 30 03:21:05 PM PDT 24
Peak memory 201508 kb
Host smart-52952fc4-a627-40b1-ba7e-1593cdbdcc83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835620666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3835620666
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1835840334
Short name T277
Test name
Test status
Simulation time 163111711125 ps
CPU time 398.16 seconds
Started May 30 03:20:52 PM PDT 24
Finished May 30 03:27:32 PM PDT 24
Peak memory 201788 kb
Host smart-03f82352-8e12-4072-9406-bb92153f7937
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835840334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1835840334
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.4217837620
Short name T236
Test name
Test status
Simulation time 208189479765 ps
CPU time 127.29 seconds
Started May 30 03:20:52 PM PDT 24
Finished May 30 03:23:01 PM PDT 24
Peak memory 201816 kb
Host smart-41291cf7-848c-437c-be00-ee4bc6558bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217837620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.4217837620
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3463215619
Short name T772
Test name
Test status
Simulation time 327119669489 ps
CPU time 303.92 seconds
Started May 30 03:20:52 PM PDT 24
Finished May 30 03:25:57 PM PDT 24
Peak memory 201796 kb
Host smart-9be8fb32-c698-46f8-941b-51d070da4bc9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463215619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3463215619
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3219896287
Short name T620
Test name
Test status
Simulation time 337738815972 ps
CPU time 797.17 seconds
Started May 30 03:20:43 PM PDT 24
Finished May 30 03:34:01 PM PDT 24
Peak memory 201868 kb
Host smart-1c5fb962-fae5-4c5b-9907-482e6c3f162c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219896287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3219896287
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1688303863
Short name T451
Test name
Test status
Simulation time 164553201523 ps
CPU time 317.44 seconds
Started May 30 03:20:43 PM PDT 24
Finished May 30 03:26:02 PM PDT 24
Peak memory 201900 kb
Host smart-0fbe1554-fffd-4e5e-bf15-214b64cba038
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688303863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1688303863
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.17749410
Short name T695
Test name
Test status
Simulation time 173056955690 ps
CPU time 396.93 seconds
Started May 30 03:20:52 PM PDT 24
Finished May 30 03:27:30 PM PDT 24
Peak memory 201892 kb
Host smart-cfc1a2e8-b800-46cd-a0b1-5903be061269
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17749410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_w
akeup.17749410
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1842438300
Short name T458
Test name
Test status
Simulation time 204545310225 ps
CPU time 469.77 seconds
Started May 30 03:20:53 PM PDT 24
Finished May 30 03:28:44 PM PDT 24
Peak memory 201784 kb
Host smart-01be54d4-aec2-4986-a5f2-df3653059b12
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842438300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1842438300
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3954119490
Short name T688
Test name
Test status
Simulation time 93712441864 ps
CPU time 320.87 seconds
Started May 30 03:21:01 PM PDT 24
Finished May 30 03:26:23 PM PDT 24
Peak memory 202128 kb
Host smart-0b61f695-1b5f-4f6f-9557-6c9b1be1eaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954119490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3954119490
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1994799688
Short name T412
Test name
Test status
Simulation time 20319479977 ps
CPU time 50.85 seconds
Started May 30 03:21:02 PM PDT 24
Finished May 30 03:21:54 PM PDT 24
Peak memory 201608 kb
Host smart-43d160d0-f071-44dc-a10a-6c14604c6856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994799688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1994799688
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.2151779830
Short name T354
Test name
Test status
Simulation time 3435924395 ps
CPU time 8.71 seconds
Started May 30 03:20:52 PM PDT 24
Finished May 30 03:21:02 PM PDT 24
Peak memory 201600 kb
Host smart-4faa1e83-f3ec-4821-b3cc-6fda720d7221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151779830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2151779830
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1392800569
Short name T516
Test name
Test status
Simulation time 5921903416 ps
CPU time 15.5 seconds
Started May 30 03:20:41 PM PDT 24
Finished May 30 03:20:57 PM PDT 24
Peak memory 201600 kb
Host smart-65a9bf80-37df-453b-b75e-a02656fc8591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392800569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1392800569
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.814621783
Short name T651
Test name
Test status
Simulation time 372225554452 ps
CPU time 416.86 seconds
Started May 30 03:21:02 PM PDT 24
Finished May 30 03:28:00 PM PDT 24
Peak memory 201824 kb
Host smart-d22b60fa-8601-463f-9b61-76032d4044f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814621783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.
814621783
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2982275873
Short name T420
Test name
Test status
Simulation time 500254083 ps
CPU time 1.77 seconds
Started May 30 03:21:28 PM PDT 24
Finished May 30 03:21:32 PM PDT 24
Peak memory 201516 kb
Host smart-bd5138ef-8606-4915-bd79-45684028b44d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982275873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2982275873
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.4175663852
Short name T162
Test name
Test status
Simulation time 319127782968 ps
CPU time 372.45 seconds
Started May 30 03:21:20 PM PDT 24
Finished May 30 03:27:34 PM PDT 24
Peak memory 201812 kb
Host smart-201154b0-1701-4804-b657-5d69aa095833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175663852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.4175663852
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1420687785
Short name T336
Test name
Test status
Simulation time 492660562601 ps
CPU time 331.85 seconds
Started May 30 03:21:20 PM PDT 24
Finished May 30 03:26:53 PM PDT 24
Peak memory 201808 kb
Host smart-d7b8cac1-4350-4b57-b5c8-b22440dbfc3e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420687785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1420687785
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.846319531
Short name T572
Test name
Test status
Simulation time 482192970614 ps
CPU time 556.83 seconds
Started May 30 03:21:03 PM PDT 24
Finished May 30 03:30:21 PM PDT 24
Peak memory 201732 kb
Host smart-5bf08344-396b-4677-8bdd-d0cc1c9edec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846319531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.846319531
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.4247031341
Short name T712
Test name
Test status
Simulation time 162718152120 ps
CPU time 378.38 seconds
Started May 30 03:21:02 PM PDT 24
Finished May 30 03:27:22 PM PDT 24
Peak memory 201812 kb
Host smart-f67b3bf5-862e-4214-8169-3b7744da5507
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247031341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.4247031341
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1769062804
Short name T217
Test name
Test status
Simulation time 524567144429 ps
CPU time 1212.46 seconds
Started May 30 03:21:20 PM PDT 24
Finished May 30 03:41:34 PM PDT 24
Peak memory 201900 kb
Host smart-c18d0f4f-0085-4626-9922-be467629ecfb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769062804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1769062804
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1541983049
Short name T615
Test name
Test status
Simulation time 617045282650 ps
CPU time 379.96 seconds
Started May 30 03:21:20 PM PDT 24
Finished May 30 03:27:41 PM PDT 24
Peak memory 201808 kb
Host smart-4fffbfff-3596-4dcf-b911-5703ec986c69
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541983049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1541983049
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2634499524
Short name T3
Test name
Test status
Simulation time 113590440502 ps
CPU time 576.73 seconds
Started May 30 03:21:28 PM PDT 24
Finished May 30 03:31:06 PM PDT 24
Peak memory 202124 kb
Host smart-a55bc135-8de8-4e8b-a579-82624a6d5d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634499524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2634499524
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.505690077
Short name T337
Test name
Test status
Simulation time 40053718161 ps
CPU time 6.54 seconds
Started May 30 03:21:20 PM PDT 24
Finished May 30 03:21:28 PM PDT 24
Peak memory 201640 kb
Host smart-3dc3d34f-32e0-465b-824f-bc0e1acd8c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505690077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.505690077
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.769934383
Short name T391
Test name
Test status
Simulation time 4094094303 ps
CPU time 2.04 seconds
Started May 30 03:21:20 PM PDT 24
Finished May 30 03:21:24 PM PDT 24
Peak memory 201584 kb
Host smart-19f76dbe-9877-41f7-a4f0-ca67797fb7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769934383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.769934383
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3828290414
Short name T517
Test name
Test status
Simulation time 5647794073 ps
CPU time 7.06 seconds
Started May 30 03:21:02 PM PDT 24
Finished May 30 03:21:10 PM PDT 24
Peak memory 201652 kb
Host smart-084a1f00-36ce-4e52-b6df-a27528fd3934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828290414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3828290414
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.4144822096
Short name T20
Test name
Test status
Simulation time 375921904178 ps
CPU time 644.19 seconds
Started May 30 03:21:28 PM PDT 24
Finished May 30 03:32:14 PM PDT 24
Peak memory 210488 kb
Host smart-8bf794c5-87e8-4323-9a7c-8973cf4e2a1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144822096 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.4144822096
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1797689316
Short name T526
Test name
Test status
Simulation time 412551228 ps
CPU time 1.07 seconds
Started May 30 03:21:32 PM PDT 24
Finished May 30 03:21:34 PM PDT 24
Peak memory 201504 kb
Host smart-987e8792-0d46-49a2-8f63-38f4283ebbc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797689316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1797689316
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.876957280
Short name T254
Test name
Test status
Simulation time 507533283363 ps
CPU time 160.38 seconds
Started May 30 03:21:30 PM PDT 24
Finished May 30 03:24:12 PM PDT 24
Peak memory 201828 kb
Host smart-9d531d4b-65ba-4bc0-989b-e66b1e43f8cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876957280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.876957280
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.855354743
Short name T685
Test name
Test status
Simulation time 323845234332 ps
CPU time 362.84 seconds
Started May 30 03:21:31 PM PDT 24
Finished May 30 03:27:36 PM PDT 24
Peak memory 201792 kb
Host smart-6f921251-4714-4a07-beba-0720db2e11d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855354743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.855354743
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.553899923
Short name T724
Test name
Test status
Simulation time 160348439671 ps
CPU time 394.51 seconds
Started May 30 03:21:30 PM PDT 24
Finished May 30 03:28:06 PM PDT 24
Peak memory 201784 kb
Host smart-7286f860-665b-4d6f-86e5-5777501f1a44
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=553899923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.553899923
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.413177091
Short name T272
Test name
Test status
Simulation time 496004838536 ps
CPU time 563.59 seconds
Started May 30 03:21:29 PM PDT 24
Finished May 30 03:30:54 PM PDT 24
Peak memory 201848 kb
Host smart-92451002-6606-4565-9406-01516667c780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413177091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.413177091
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1889937025
Short name T593
Test name
Test status
Simulation time 325605469252 ps
CPU time 372.51 seconds
Started May 30 03:21:28 PM PDT 24
Finished May 30 03:27:42 PM PDT 24
Peak memory 201868 kb
Host smart-b37750d9-80ae-4fb0-a6c4-19d4bb2906ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889937025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1889937025
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.161881676
Short name T85
Test name
Test status
Simulation time 342452625510 ps
CPU time 202.96 seconds
Started May 30 03:21:30 PM PDT 24
Finished May 30 03:24:55 PM PDT 24
Peak memory 201780 kb
Host smart-b2433fb5-8d89-4cfe-a633-7aedf613e6bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161881676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.161881676
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.206171828
Short name T431
Test name
Test status
Simulation time 414746647748 ps
CPU time 825.14 seconds
Started May 30 03:21:28 PM PDT 24
Finished May 30 03:35:14 PM PDT 24
Peak memory 201808 kb
Host smart-57217370-f169-471d-9356-c6d94b6cd50a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206171828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.206171828
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.4211219812
Short name T323
Test name
Test status
Simulation time 90764295241 ps
CPU time 459.63 seconds
Started May 30 03:21:30 PM PDT 24
Finished May 30 03:29:11 PM PDT 24
Peak memory 202124 kb
Host smart-1f405290-67b5-44a1-a1ae-77f4d1f4577b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211219812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.4211219812
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2824820979
Short name T328
Test name
Test status
Simulation time 26826722739 ps
CPU time 24.69 seconds
Started May 30 03:21:29 PM PDT 24
Finished May 30 03:21:55 PM PDT 24
Peak memory 201644 kb
Host smart-7ece69bf-463a-4b4d-a19d-a19e9a8776f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824820979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2824820979
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1651567022
Short name T687
Test name
Test status
Simulation time 3620361631 ps
CPU time 5.31 seconds
Started May 30 03:21:28 PM PDT 24
Finished May 30 03:21:35 PM PDT 24
Peak memory 201612 kb
Host smart-28fc24b3-cbac-4fcf-9cb9-11f3a5bfbbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651567022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1651567022
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.476456624
Short name T718
Test name
Test status
Simulation time 5907916178 ps
CPU time 3.11 seconds
Started May 30 03:21:30 PM PDT 24
Finished May 30 03:21:35 PM PDT 24
Peak memory 201624 kb
Host smart-ca0bb817-68ac-4a70-be60-54a2cb013b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476456624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.476456624
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1914972498
Short name T592
Test name
Test status
Simulation time 509072586 ps
CPU time 1.76 seconds
Started May 30 03:21:49 PM PDT 24
Finished May 30 03:21:52 PM PDT 24
Peak memory 201496 kb
Host smart-400e3a34-fb9e-48a5-8e12-c10e1354bdb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914972498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1914972498
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.1793129611
Short name T230
Test name
Test status
Simulation time 347956107801 ps
CPU time 135.78 seconds
Started May 30 03:21:38 PM PDT 24
Finished May 30 03:23:55 PM PDT 24
Peak memory 201892 kb
Host smart-32a4c19f-b91b-4400-9312-830b3df4645a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793129611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.1793129611
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2453410361
Short name T642
Test name
Test status
Simulation time 518253705384 ps
CPU time 331.66 seconds
Started May 30 03:21:39 PM PDT 24
Finished May 30 03:27:11 PM PDT 24
Peak memory 201812 kb
Host smart-7d7594b8-12df-4cdc-90a6-a61086758ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453410361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2453410361
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3779542849
Short name T312
Test name
Test status
Simulation time 335916250276 ps
CPU time 757.95 seconds
Started May 30 03:21:39 PM PDT 24
Finished May 30 03:34:18 PM PDT 24
Peak memory 201888 kb
Host smart-ef8b0c71-627e-4e22-a44f-8de051817041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779542849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3779542849
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1093684490
Short name T382
Test name
Test status
Simulation time 498526537944 ps
CPU time 605.85 seconds
Started May 30 03:21:40 PM PDT 24
Finished May 30 03:31:47 PM PDT 24
Peak memory 201784 kb
Host smart-9849b456-17d5-4b82-bf8b-37b1c6077e53
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093684490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1093684490
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1482015937
Short name T163
Test name
Test status
Simulation time 497534148208 ps
CPU time 84.14 seconds
Started May 30 03:21:28 PM PDT 24
Finished May 30 03:22:54 PM PDT 24
Peak memory 201736 kb
Host smart-77bd6a86-2c9b-4f7b-97ed-73d9d79986f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482015937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1482015937
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.918415966
Short name T428
Test name
Test status
Simulation time 164972850913 ps
CPU time 187.67 seconds
Started May 30 03:21:39 PM PDT 24
Finished May 30 03:24:48 PM PDT 24
Peak memory 201792 kb
Host smart-ebdf0644-5d28-45c7-8c1f-7a1971ff230a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=918415966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.918415966
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.321130249
Short name T744
Test name
Test status
Simulation time 349377136930 ps
CPU time 416.19 seconds
Started May 30 03:21:41 PM PDT 24
Finished May 30 03:28:38 PM PDT 24
Peak memory 201872 kb
Host smart-2c18ce83-af85-4ec5-9c9c-d9c6db57d956
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321130249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_
wakeup.321130249
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1506560423
Short name T153
Test name
Test status
Simulation time 587986497943 ps
CPU time 187.49 seconds
Started May 30 03:21:38 PM PDT 24
Finished May 30 03:24:46 PM PDT 24
Peak memory 201848 kb
Host smart-79e67760-d011-4419-8be3-0834c9bef57d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506560423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1506560423
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.4160892872
Short name T677
Test name
Test status
Simulation time 106568534025 ps
CPU time 595.67 seconds
Started May 30 03:21:38 PM PDT 24
Finished May 30 03:31:35 PM PDT 24
Peak memory 202128 kb
Host smart-06f91685-9ceb-458e-a0d1-e19192019ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160892872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.4160892872
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.1300239693
Short name T549
Test name
Test status
Simulation time 29852284544 ps
CPU time 5.69 seconds
Started May 30 03:21:39 PM PDT 24
Finished May 30 03:21:46 PM PDT 24
Peak memory 201640 kb
Host smart-5003ba6b-58e5-48be-88aa-bb8f8f8056ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300239693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1300239693
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2560545320
Short name T117
Test name
Test status
Simulation time 4879763626 ps
CPU time 11.4 seconds
Started May 30 03:21:37 PM PDT 24
Finished May 30 03:21:50 PM PDT 24
Peak memory 201652 kb
Host smart-cf6c49f2-7ae5-4486-aad8-418d9fe25c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560545320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2560545320
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.869768023
Short name T463
Test name
Test status
Simulation time 6045386728 ps
CPU time 2.03 seconds
Started May 30 03:21:29 PM PDT 24
Finished May 30 03:21:32 PM PDT 24
Peak memory 201640 kb
Host smart-bc85be27-96eb-40ae-8149-559f9820e93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869768023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.869768023
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.343711534
Short name T22
Test name
Test status
Simulation time 201704151419 ps
CPU time 182.39 seconds
Started May 30 03:21:38 PM PDT 24
Finished May 30 03:24:42 PM PDT 24
Peak memory 211464 kb
Host smart-991ec840-ca03-4d0d-8c98-3e13391ef828
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343711534 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.343711534
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1456144871
Short name T633
Test name
Test status
Simulation time 507291205 ps
CPU time 1.65 seconds
Started May 30 03:21:58 PM PDT 24
Finished May 30 03:22:01 PM PDT 24
Peak memory 201512 kb
Host smart-bf0d52b0-fad5-4eee-9f1b-4903a2e52e37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456144871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1456144871
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2858438599
Short name T667
Test name
Test status
Simulation time 177500988254 ps
CPU time 28.21 seconds
Started May 30 03:21:49 PM PDT 24
Finished May 30 03:22:19 PM PDT 24
Peak memory 201868 kb
Host smart-e7253dab-2975-4ffe-86e4-bb3c102fc04c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858438599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2858438599
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.181934425
Short name T733
Test name
Test status
Simulation time 487580840804 ps
CPU time 181.81 seconds
Started May 30 03:21:47 PM PDT 24
Finished May 30 03:24:50 PM PDT 24
Peak memory 201796 kb
Host smart-4874f392-180d-40f0-9ecc-44d7f2bc05c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=181934425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrup
t_fixed.181934425
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.4043161391
Short name T80
Test name
Test status
Simulation time 163438451003 ps
CPU time 390.43 seconds
Started May 30 03:21:50 PM PDT 24
Finished May 30 03:28:22 PM PDT 24
Peak memory 201948 kb
Host smart-9cdeffb0-bc35-466f-b64c-76345e353e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043161391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.4043161391
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3295796011
Short name T659
Test name
Test status
Simulation time 162468673763 ps
CPU time 110.15 seconds
Started May 30 03:21:48 PM PDT 24
Finished May 30 03:23:39 PM PDT 24
Peak memory 201800 kb
Host smart-defed67f-ad33-47ab-b0f5-1e513a9f151b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295796011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3295796011
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2644015328
Short name T241
Test name
Test status
Simulation time 406172796977 ps
CPU time 441.88 seconds
Started May 30 03:21:47 PM PDT 24
Finished May 30 03:29:10 PM PDT 24
Peak memory 201876 kb
Host smart-fce81856-b9a1-4416-a955-b81fea683022
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644015328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2644015328
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.50746034
Short name T86
Test name
Test status
Simulation time 199075184811 ps
CPU time 235.81 seconds
Started May 30 03:21:47 PM PDT 24
Finished May 30 03:25:43 PM PDT 24
Peak memory 201780 kb
Host smart-5b0e07ba-a375-4001-8a64-dd7d47509cfb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50746034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.a
dc_ctrl_filters_wakeup_fixed.50746034
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.390509454
Short name T474
Test name
Test status
Simulation time 123965690894 ps
CPU time 504.84 seconds
Started May 30 03:21:58 PM PDT 24
Finished May 30 03:30:24 PM PDT 24
Peak memory 202184 kb
Host smart-1c445042-039c-4f98-a4e5-9c786fb1843e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390509454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.390509454
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3151638552
Short name T362
Test name
Test status
Simulation time 26386042406 ps
CPU time 61.99 seconds
Started May 30 03:22:00 PM PDT 24
Finished May 30 03:23:03 PM PDT 24
Peak memory 201572 kb
Host smart-236e5e65-eb9f-403a-b513-fefc7af30eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151638552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3151638552
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.756800672
Short name T589
Test name
Test status
Simulation time 3364156801 ps
CPU time 2.65 seconds
Started May 30 03:21:58 PM PDT 24
Finished May 30 03:22:01 PM PDT 24
Peak memory 201580 kb
Host smart-d6d561b6-9785-46dc-ac95-f00ac90e86a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756800672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.756800672
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.77548182
Short name T791
Test name
Test status
Simulation time 5691005469 ps
CPU time 13.42 seconds
Started May 30 03:21:48 PM PDT 24
Finished May 30 03:22:03 PM PDT 24
Peak memory 201652 kb
Host smart-feb3d0ed-5fe7-4308-9359-6195da7712ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77548182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.77548182
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.677884017
Short name T551
Test name
Test status
Simulation time 361376343673 ps
CPU time 795.95 seconds
Started May 30 03:21:58 PM PDT 24
Finished May 30 03:35:15 PM PDT 24
Peak memory 201760 kb
Host smart-024c89e6-4020-49d0-be83-47baf03045f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677884017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
677884017
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.3248336150
Short name T510
Test name
Test status
Simulation time 513586091 ps
CPU time 1.32 seconds
Started May 30 03:22:22 PM PDT 24
Finished May 30 03:22:25 PM PDT 24
Peak memory 201460 kb
Host smart-0125e40f-649f-47c2-859d-ae4e3b5275b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248336150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.3248336150
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1635238406
Short name T539
Test name
Test status
Simulation time 160287831781 ps
CPU time 7.52 seconds
Started May 30 03:22:11 PM PDT 24
Finished May 30 03:22:20 PM PDT 24
Peak memory 201800 kb
Host smart-dc000dc8-f3e3-4fe3-9b12-2a85c8ecb417
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635238406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1635238406
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2233703644
Short name T316
Test name
Test status
Simulation time 344147230564 ps
CPU time 410.3 seconds
Started May 30 03:22:11 PM PDT 24
Finished May 30 03:29:03 PM PDT 24
Peak memory 201888 kb
Host smart-095e3cf1-fabc-4415-b5d7-4bfc0c3c87f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233703644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2233703644
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2227454659
Short name T327
Test name
Test status
Simulation time 326330021691 ps
CPU time 744.9 seconds
Started May 30 03:22:10 PM PDT 24
Finished May 30 03:34:36 PM PDT 24
Peak memory 201872 kb
Host smart-fc29f7bb-8477-4b3c-b009-fa3cca4e7124
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227454659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2227454659
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3345015501
Short name T479
Test name
Test status
Simulation time 316245285620 ps
CPU time 284.33 seconds
Started May 30 03:22:11 PM PDT 24
Finished May 30 03:26:57 PM PDT 24
Peak memory 201884 kb
Host smart-1b64a0e0-26bb-44c3-a74e-9dcd2773b2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345015501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3345015501
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1357654158
Short name T645
Test name
Test status
Simulation time 171072758788 ps
CPU time 392.55 seconds
Started May 30 03:22:12 PM PDT 24
Finished May 30 03:28:47 PM PDT 24
Peak memory 201852 kb
Host smart-0be55e94-5853-4d7c-bdbd-5aa6cf4fd09c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357654158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1357654158
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.125292850
Short name T249
Test name
Test status
Simulation time 218728896458 ps
CPU time 477.59 seconds
Started May 30 03:22:10 PM PDT 24
Finished May 30 03:30:08 PM PDT 24
Peak memory 201828 kb
Host smart-90fa9484-2b81-4d0e-ac63-27e838211194
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125292850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.125292850
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1125950989
Short name T453
Test name
Test status
Simulation time 409354776582 ps
CPU time 63.32 seconds
Started May 30 03:22:12 PM PDT 24
Finished May 30 03:23:17 PM PDT 24
Peak memory 201820 kb
Host smart-f63c7450-36b6-416f-bfd8-f2981208f7ad
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125950989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1125950989
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1330759715
Short name T192
Test name
Test status
Simulation time 97841024813 ps
CPU time 456.89 seconds
Started May 30 03:22:24 PM PDT 24
Finished May 30 03:30:02 PM PDT 24
Peak memory 202108 kb
Host smart-294ed45f-eb21-4d04-b0cf-85ba0261ce2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330759715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1330759715
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.4198138945
Short name T406
Test name
Test status
Simulation time 38066424759 ps
CPU time 19.71 seconds
Started May 30 03:22:10 PM PDT 24
Finished May 30 03:22:31 PM PDT 24
Peak memory 201620 kb
Host smart-dd0734ce-9cb2-4013-88bd-f9171de63b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198138945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.4198138945
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3023518558
Short name T578
Test name
Test status
Simulation time 5077430413 ps
CPU time 3.79 seconds
Started May 30 03:22:10 PM PDT 24
Finished May 30 03:22:15 PM PDT 24
Peak memory 201604 kb
Host smart-bd8d0457-3573-4529-928b-3f8c918042b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023518558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3023518558
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.124512410
Short name T614
Test name
Test status
Simulation time 5824715937 ps
CPU time 8.04 seconds
Started May 30 03:22:10 PM PDT 24
Finished May 30 03:22:20 PM PDT 24
Peak memory 201656 kb
Host smart-19dc5d04-3b30-47c4-9c73-a67630f7458d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124512410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.124512410
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3739272222
Short name T306
Test name
Test status
Simulation time 720892457992 ps
CPU time 330.23 seconds
Started May 30 03:22:27 PM PDT 24
Finished May 30 03:27:58 PM PDT 24
Peak memory 201804 kb
Host smart-733dceea-c57e-4401-ae38-6c9e37e5b817
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739272222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3739272222
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2907010904
Short name T653
Test name
Test status
Simulation time 162025137212 ps
CPU time 183.95 seconds
Started May 30 03:22:25 PM PDT 24
Finished May 30 03:25:30 PM PDT 24
Peak memory 210140 kb
Host smart-aedd4113-0f80-494d-bc3e-3099afeb3e4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907010904 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2907010904
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2365122307
Short name T370
Test name
Test status
Simulation time 478347781 ps
CPU time 0.78 seconds
Started May 30 03:22:34 PM PDT 24
Finished May 30 03:22:36 PM PDT 24
Peak memory 201524 kb
Host smart-99e80547-ee11-4578-baca-eea0766472ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365122307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2365122307
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3719248977
Short name T694
Test name
Test status
Simulation time 181175571311 ps
CPU time 394.09 seconds
Started May 30 03:22:25 PM PDT 24
Finished May 30 03:29:00 PM PDT 24
Peak memory 201752 kb
Host smart-a8cdc593-cf59-4726-965b-dc57c583eb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719248977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3719248977
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3784515238
Short name T736
Test name
Test status
Simulation time 332553290868 ps
CPU time 57.47 seconds
Started May 30 03:22:23 PM PDT 24
Finished May 30 03:23:22 PM PDT 24
Peak memory 201832 kb
Host smart-2db28c7b-452a-4bf0-abb2-5c231763f9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784515238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3784515238
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2099306332
Short name T608
Test name
Test status
Simulation time 332088442910 ps
CPU time 756.59 seconds
Started May 30 03:22:23 PM PDT 24
Finished May 30 03:35:01 PM PDT 24
Peak memory 201804 kb
Host smart-a6f502c9-528c-473d-939f-ec4f93ce3ece
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099306332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2099306332
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2876542663
Short name T496
Test name
Test status
Simulation time 166954123494 ps
CPU time 62.17 seconds
Started May 30 03:22:25 PM PDT 24
Finished May 30 03:23:28 PM PDT 24
Peak memory 201796 kb
Host smart-c60fa62a-3d4f-499b-9ca0-700808f73a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876542663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2876542663
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.563605121
Short name T355
Test name
Test status
Simulation time 488083385239 ps
CPU time 604.14 seconds
Started May 30 03:22:22 PM PDT 24
Finished May 30 03:32:27 PM PDT 24
Peak memory 201808 kb
Host smart-c5d43356-6e3d-47f5-8d82-d248380e7d9d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=563605121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.563605121
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1749562586
Short name T684
Test name
Test status
Simulation time 368356187862 ps
CPU time 81.52 seconds
Started May 30 03:22:24 PM PDT 24
Finished May 30 03:23:47 PM PDT 24
Peak memory 201912 kb
Host smart-1f8ce604-d3ce-4069-b883-32e4b083ed4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749562586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1749562586
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3592812626
Short name T512
Test name
Test status
Simulation time 601852106823 ps
CPU time 1344.68 seconds
Started May 30 03:22:23 PM PDT 24
Finished May 30 03:44:49 PM PDT 24
Peak memory 201824 kb
Host smart-390d7d77-7f17-4840-9ae6-bbe4ea5befc0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592812626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.3592812626
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2173643951
Short name T41
Test name
Test status
Simulation time 71143232235 ps
CPU time 342.71 seconds
Started May 30 03:22:25 PM PDT 24
Finished May 30 03:28:09 PM PDT 24
Peak memory 202148 kb
Host smart-01719205-89de-443a-9e78-4bfc0a2bfa86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173643951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2173643951
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3404467322
Short name T330
Test name
Test status
Simulation time 36803739142 ps
CPU time 42.26 seconds
Started May 30 03:22:22 PM PDT 24
Finished May 30 03:23:06 PM PDT 24
Peak memory 201644 kb
Host smart-89327916-b380-4a00-afd8-d9bcdffd534a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404467322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3404467322
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1473868946
Short name T459
Test name
Test status
Simulation time 3837887364 ps
CPU time 2.98 seconds
Started May 30 03:22:23 PM PDT 24
Finished May 30 03:22:27 PM PDT 24
Peak memory 201640 kb
Host smart-3a3d7d22-28f2-4ca4-8bef-3e103deaf65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473868946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1473868946
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.878605174
Short name T497
Test name
Test status
Simulation time 6015941456 ps
CPU time 8.05 seconds
Started May 30 03:22:23 PM PDT 24
Finished May 30 03:22:32 PM PDT 24
Peak memory 201624 kb
Host smart-7c9d3ddb-fcf1-4396-a496-b3792e4d774e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878605174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.878605174
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3949181068
Short name T781
Test name
Test status
Simulation time 647938376269 ps
CPU time 1453.43 seconds
Started May 30 03:22:34 PM PDT 24
Finished May 30 03:46:49 PM PDT 24
Peak memory 201796 kb
Host smart-ca1c4215-4639-4892-8f92-824e07bedf2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949181068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3949181068
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.1324830516
Short name T62
Test name
Test status
Simulation time 432965275 ps
CPU time 1.55 seconds
Started May 30 03:22:45 PM PDT 24
Finished May 30 03:22:47 PM PDT 24
Peak memory 201500 kb
Host smart-b537e76d-a91e-4426-bf37-fc58a48a475d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324830516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.1324830516
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2254480127
Short name T748
Test name
Test status
Simulation time 332574146712 ps
CPU time 392.25 seconds
Started May 30 03:22:38 PM PDT 24
Finished May 30 03:29:12 PM PDT 24
Peak memory 201776 kb
Host smart-81e2d6f6-e61a-408b-bb0d-bc282b989120
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254480127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2254480127
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3303735334
Short name T240
Test name
Test status
Simulation time 349536801288 ps
CPU time 204.02 seconds
Started May 30 03:22:39 PM PDT 24
Finished May 30 03:26:04 PM PDT 24
Peak memory 201884 kb
Host smart-20b691a0-3088-40fd-82f3-09f23c18fd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303735334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3303735334
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3388964413
Short name T611
Test name
Test status
Simulation time 326814246959 ps
CPU time 770.35 seconds
Started May 30 03:22:35 PM PDT 24
Finished May 30 03:35:26 PM PDT 24
Peak memory 201784 kb
Host smart-c026d2a2-b72b-41ec-9052-84bc1db15c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388964413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3388964413
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.4240010450
Short name T371
Test name
Test status
Simulation time 167903983669 ps
CPU time 328.21 seconds
Started May 30 03:22:33 PM PDT 24
Finished May 30 03:28:02 PM PDT 24
Peak memory 201740 kb
Host smart-4b5982b0-1162-4356-8502-990a024c5b34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240010450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.4240010450
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.24003126
Short name T137
Test name
Test status
Simulation time 336889270808 ps
CPU time 815.36 seconds
Started May 30 03:22:40 PM PDT 24
Finished May 30 03:36:16 PM PDT 24
Peak memory 201796 kb
Host smart-2bddde04-00a8-4ca0-a557-dae24e286a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24003126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.24003126
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2388018337
Short name T591
Test name
Test status
Simulation time 489477020520 ps
CPU time 124.36 seconds
Started May 30 03:22:33 PM PDT 24
Finished May 30 03:24:38 PM PDT 24
Peak memory 201800 kb
Host smart-3bf564a8-876d-4482-9400-397b72b277f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388018337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2388018337
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.866853325
Short name T239
Test name
Test status
Simulation time 182801455099 ps
CPU time 156.43 seconds
Started May 30 03:22:32 PM PDT 24
Finished May 30 03:25:10 PM PDT 24
Peak memory 201824 kb
Host smart-8c7a9c7c-58d2-4bc2-abb9-c7f2cd164fd9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866853325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_
wakeup.866853325
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1749926770
Short name T134
Test name
Test status
Simulation time 596121747162 ps
CPU time 181.65 seconds
Started May 30 03:22:33 PM PDT 24
Finished May 30 03:25:36 PM PDT 24
Peak memory 201820 kb
Host smart-7061a2fb-14e2-48e6-9d02-9f9bd26b1cf8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749926770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1749926770
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3712921205
Short name T483
Test name
Test status
Simulation time 109829143088 ps
CPU time 316.47 seconds
Started May 30 03:22:40 PM PDT 24
Finished May 30 03:27:57 PM PDT 24
Peak memory 202208 kb
Host smart-7f8cc269-90d9-4c05-a309-9e9ce9fc58ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712921205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3712921205
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1806463585
Short name T417
Test name
Test status
Simulation time 21180236906 ps
CPU time 26.01 seconds
Started May 30 03:22:33 PM PDT 24
Finished May 30 03:23:00 PM PDT 24
Peak memory 201644 kb
Host smart-f6157d99-2570-42ed-9541-c273c102ca60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806463585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1806463585
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1210434346
Short name T395
Test name
Test status
Simulation time 4061713786 ps
CPU time 3.03 seconds
Started May 30 03:22:40 PM PDT 24
Finished May 30 03:22:44 PM PDT 24
Peak memory 201624 kb
Host smart-ceee2807-6dfc-4a3b-b9e5-2a82ce730145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210434346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1210434346
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.385909925
Short name T624
Test name
Test status
Simulation time 6116138107 ps
CPU time 4.74 seconds
Started May 30 03:22:33 PM PDT 24
Finished May 30 03:22:39 PM PDT 24
Peak memory 201624 kb
Host smart-19d7c104-c454-4173-aecc-0d9100f72d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385909925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.385909925
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.56376077
Short name T142
Test name
Test status
Simulation time 343181154884 ps
CPU time 53.99 seconds
Started May 30 03:22:49 PM PDT 24
Finished May 30 03:23:44 PM PDT 24
Peak memory 201800 kb
Host smart-da007777-e2d3-4c91-9fbd-0f0377f3a567
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56376077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.56376077
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.471836461
Short name T579
Test name
Test status
Simulation time 104057371492 ps
CPU time 83.78 seconds
Started May 30 03:22:33 PM PDT 24
Finished May 30 03:23:58 PM PDT 24
Peak memory 210488 kb
Host smart-04b2b92c-e2a1-4db0-a63d-13d46ba853e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471836461 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.471836461
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2983536745
Short name T60
Test name
Test status
Simulation time 389151149 ps
CPU time 1.56 seconds
Started May 30 03:22:55 PM PDT 24
Finished May 30 03:22:58 PM PDT 24
Peak memory 201460 kb
Host smart-0265a1f6-9b32-4b49-90d9-4f7193608073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983536745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2983536745
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.462794707
Short name T617
Test name
Test status
Simulation time 508424799993 ps
CPU time 303.62 seconds
Started May 30 03:22:49 PM PDT 24
Finished May 30 03:27:54 PM PDT 24
Peak memory 201804 kb
Host smart-f1830e8f-5077-448b-a26c-464ce3cdc959
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462794707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.462794707
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.2604616188
Short name T514
Test name
Test status
Simulation time 168033381470 ps
CPU time 123.61 seconds
Started May 30 03:22:45 PM PDT 24
Finished May 30 03:24:50 PM PDT 24
Peak memory 201808 kb
Host smart-55d95121-0eb6-4628-abfd-9c38d42f35d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604616188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.2604616188
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.507888413
Short name T144
Test name
Test status
Simulation time 332874049066 ps
CPU time 392.46 seconds
Started May 30 03:22:49 PM PDT 24
Finished May 30 03:29:22 PM PDT 24
Peak memory 201804 kb
Host smart-0375d78b-68c8-4a17-961a-b6043f1ed10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507888413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.507888413
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.313214634
Short name T469
Test name
Test status
Simulation time 328112740339 ps
CPU time 191.51 seconds
Started May 30 03:22:44 PM PDT 24
Finished May 30 03:25:56 PM PDT 24
Peak memory 201808 kb
Host smart-0b7b8215-00b3-47f2-9bf5-88e5c94d998c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=313214634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.313214634
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.2588398371
Short name T166
Test name
Test status
Simulation time 490076727659 ps
CPU time 318.37 seconds
Started May 30 03:22:45 PM PDT 24
Finished May 30 03:28:04 PM PDT 24
Peak memory 201768 kb
Host smart-7b9c4075-5927-446f-9ea3-9f67fc343c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588398371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2588398371
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3269871950
Short name T372
Test name
Test status
Simulation time 483744699693 ps
CPU time 266.08 seconds
Started May 30 03:22:45 PM PDT 24
Finished May 30 03:27:12 PM PDT 24
Peak memory 201800 kb
Host smart-d21ff353-3982-442b-bf2c-aacb86f085a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269871950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3269871950
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1851025997
Short name T234
Test name
Test status
Simulation time 183359801118 ps
CPU time 96.33 seconds
Started May 30 03:22:45 PM PDT 24
Finished May 30 03:24:22 PM PDT 24
Peak memory 201852 kb
Host smart-1d9c7271-5927-4a16-a1f2-887066a61435
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851025997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1851025997
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3706212778
Short name T441
Test name
Test status
Simulation time 407182638441 ps
CPU time 63.4 seconds
Started May 30 03:22:49 PM PDT 24
Finished May 30 03:23:54 PM PDT 24
Peak memory 201808 kb
Host smart-51ab1a09-3d2d-4efb-a12c-1e69780f6dea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706212778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3706212778
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1220545131
Short name T405
Test name
Test status
Simulation time 82975964421 ps
CPU time 438.19 seconds
Started May 30 03:22:58 PM PDT 24
Finished May 30 03:30:18 PM PDT 24
Peak memory 202188 kb
Host smart-32c9f951-765f-4aa0-85b7-61a7f1dcb5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220545131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1220545131
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2309858458
Short name T778
Test name
Test status
Simulation time 40411350867 ps
CPU time 7.96 seconds
Started May 30 03:22:56 PM PDT 24
Finished May 30 03:23:05 PM PDT 24
Peak memory 201580 kb
Host smart-9e525630-11d7-4162-87b0-a64ec2e3ff7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309858458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2309858458
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.4022284271
Short name T434
Test name
Test status
Simulation time 4299406223 ps
CPU time 10.61 seconds
Started May 30 03:22:57 PM PDT 24
Finished May 30 03:23:09 PM PDT 24
Peak memory 201612 kb
Host smart-49973c51-d1d7-488e-b2aa-cf1bb0d914d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022284271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.4022284271
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.969460089
Short name T767
Test name
Test status
Simulation time 6079217141 ps
CPU time 2.25 seconds
Started May 30 03:22:47 PM PDT 24
Finished May 30 03:22:50 PM PDT 24
Peak memory 201644 kb
Host smart-cf1bcfc4-d92c-4b48-91f9-2fbd7dc4f60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969460089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.969460089
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3929606618
Short name T777
Test name
Test status
Simulation time 101880111365 ps
CPU time 387.34 seconds
Started May 30 03:22:56 PM PDT 24
Finished May 30 03:29:25 PM PDT 24
Peak memory 202164 kb
Host smart-dab7c68a-131d-45ae-a74e-aa5424bb920d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929606618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3929606618
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2089258818
Short name T28
Test name
Test status
Simulation time 85683164662 ps
CPU time 100.74 seconds
Started May 30 03:22:56 PM PDT 24
Finished May 30 03:24:38 PM PDT 24
Peak memory 210116 kb
Host smart-7ce56a52-f1da-40b0-a3b8-39a739ae49ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089258818 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2089258818
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2628018267
Short name T398
Test name
Test status
Simulation time 361244322 ps
CPU time 0.81 seconds
Started May 30 03:23:09 PM PDT 24
Finished May 30 03:23:10 PM PDT 24
Peak memory 201496 kb
Host smart-4c18d2a7-73dd-4cb9-a565-5be4fd1e66eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628018267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2628018267
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3625344785
Short name T582
Test name
Test status
Simulation time 168727389240 ps
CPU time 196.47 seconds
Started May 30 03:23:07 PM PDT 24
Finished May 30 03:26:25 PM PDT 24
Peak memory 201780 kb
Host smart-7c53dc69-9c34-478d-88da-58c9e9c16d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625344785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3625344785
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.867904672
Short name T90
Test name
Test status
Simulation time 162745973642 ps
CPU time 399.29 seconds
Started May 30 03:22:57 PM PDT 24
Finished May 30 03:29:38 PM PDT 24
Peak memory 201752 kb
Host smart-4c2cc8b1-c80f-41c6-9c76-a0939e44c46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867904672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.867904672
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.4142700892
Short name T443
Test name
Test status
Simulation time 326040999816 ps
CPU time 352.64 seconds
Started May 30 03:22:56 PM PDT 24
Finished May 30 03:28:49 PM PDT 24
Peak memory 201792 kb
Host smart-b067dd52-a156-4d66-8362-ea8cd6a36c82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142700892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.4142700892
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2466486407
Short name T174
Test name
Test status
Simulation time 498868438941 ps
CPU time 125.73 seconds
Started May 30 03:22:55 PM PDT 24
Finished May 30 03:25:02 PM PDT 24
Peak memory 201752 kb
Host smart-0e7dd38b-7713-438f-b048-37aacee37c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466486407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2466486407
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2069787280
Short name T147
Test name
Test status
Simulation time 490731235436 ps
CPU time 295 seconds
Started May 30 03:22:56 PM PDT 24
Finished May 30 03:27:52 PM PDT 24
Peak memory 201772 kb
Host smart-bd5b56f3-3697-451d-b553-9dbfd4219828
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069787280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2069787280
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1313983361
Short name T288
Test name
Test status
Simulation time 325389792813 ps
CPU time 760.32 seconds
Started May 30 03:23:07 PM PDT 24
Finished May 30 03:35:49 PM PDT 24
Peak memory 201860 kb
Host smart-9194a43d-858d-494a-93e8-34853193b80a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313983361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1313983361
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1949108803
Short name T171
Test name
Test status
Simulation time 599943913250 ps
CPU time 217.66 seconds
Started May 30 03:23:11 PM PDT 24
Finished May 30 03:26:50 PM PDT 24
Peak memory 201808 kb
Host smart-abc400de-baf0-4f7c-aec8-2d24f2494f75
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949108803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1949108803
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1798944564
Short name T462
Test name
Test status
Simulation time 146605819064 ps
CPU time 511.51 seconds
Started May 30 03:23:12 PM PDT 24
Finished May 30 03:31:44 PM PDT 24
Peak memory 202188 kb
Host smart-c2954dac-b440-4d0d-b719-4e3fef54a2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798944564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1798944564
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.642474603
Short name T714
Test name
Test status
Simulation time 41028136290 ps
CPU time 12.64 seconds
Started May 30 03:23:12 PM PDT 24
Finished May 30 03:23:26 PM PDT 24
Peak memory 201636 kb
Host smart-4bcf2972-940b-44de-a30b-8328fa3d1798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642474603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.642474603
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2502262679
Short name T541
Test name
Test status
Simulation time 4670385807 ps
CPU time 12.76 seconds
Started May 30 03:23:08 PM PDT 24
Finished May 30 03:23:22 PM PDT 24
Peak memory 201592 kb
Host smart-1ed55245-10dd-4585-bdf3-10a714ae0ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502262679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2502262679
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1322836468
Short name T661
Test name
Test status
Simulation time 5907488505 ps
CPU time 13.67 seconds
Started May 30 03:22:56 PM PDT 24
Finished May 30 03:23:11 PM PDT 24
Peak memory 201644 kb
Host smart-5237d0b0-eb4d-45d5-9aa8-c8a68af83c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322836468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1322836468
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3049910280
Short name T310
Test name
Test status
Simulation time 197290813367 ps
CPU time 124.06 seconds
Started May 30 03:23:07 PM PDT 24
Finished May 30 03:25:12 PM PDT 24
Peak memory 201880 kb
Host smart-e677e04f-ce01-4325-b165-0180144cbe0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049910280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3049910280
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.104841361
Short name T15
Test name
Test status
Simulation time 749656649749 ps
CPU time 438.78 seconds
Started May 30 03:23:09 PM PDT 24
Finished May 30 03:30:28 PM PDT 24
Peak memory 210404 kb
Host smart-e328e22e-4805-4881-8f5a-d9fbbe4bd4f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104841361 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.104841361
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.378102254
Short name T660
Test name
Test status
Simulation time 291027881 ps
CPU time 1.3 seconds
Started May 30 03:14:47 PM PDT 24
Finished May 30 03:14:51 PM PDT 24
Peak memory 201524 kb
Host smart-a3fd02b0-8214-4f54-bdc3-22980ba5482c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378102254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.378102254
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3211167295
Short name T304
Test name
Test status
Simulation time 357615326827 ps
CPU time 768.79 seconds
Started May 30 03:14:47 PM PDT 24
Finished May 30 03:27:37 PM PDT 24
Peak memory 201880 kb
Host smart-833c9dc4-0271-4167-b057-d80a77e34856
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211167295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3211167295
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1310717926
Short name T575
Test name
Test status
Simulation time 162343513580 ps
CPU time 58.13 seconds
Started May 30 03:14:50 PM PDT 24
Finished May 30 03:15:50 PM PDT 24
Peak memory 201820 kb
Host smart-bb9d62ed-1a0d-4a41-a270-874ec5a63a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310717926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1310717926
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.709786536
Short name T226
Test name
Test status
Simulation time 488516073576 ps
CPU time 1069.87 seconds
Started May 30 03:14:48 PM PDT 24
Finished May 30 03:32:40 PM PDT 24
Peak memory 201912 kb
Host smart-d04f0ee0-d85c-4f7a-8ebf-f31338d4aa96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709786536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.709786536
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3434368871
Short name T596
Test name
Test status
Simulation time 166625864379 ps
CPU time 184.29 seconds
Started May 30 03:14:45 PM PDT 24
Finished May 30 03:17:50 PM PDT 24
Peak memory 201796 kb
Host smart-1e442e0b-abe9-422f-80c1-ffc839c29c18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434368871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3434368871
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3068155527
Short name T280
Test name
Test status
Simulation time 161800979396 ps
CPU time 99.05 seconds
Started May 30 03:14:48 PM PDT 24
Finished May 30 03:16:29 PM PDT 24
Peak memory 201572 kb
Host smart-ae5fa041-5169-4d2a-8b1c-be42beff1ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068155527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3068155527
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3544685348
Short name T689
Test name
Test status
Simulation time 159151651377 ps
CPU time 357.44 seconds
Started May 30 03:14:47 PM PDT 24
Finished May 30 03:20:47 PM PDT 24
Peak memory 201824 kb
Host smart-2e5760da-8a64-4132-a4b7-811220e04deb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544685348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3544685348
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.250759982
Short name T798
Test name
Test status
Simulation time 168789504859 ps
CPU time 95.63 seconds
Started May 30 03:14:47 PM PDT 24
Finished May 30 03:16:24 PM PDT 24
Peak memory 201880 kb
Host smart-829ffe30-c078-492e-8e02-c3d8a4d72351
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250759982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.250759982
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.4039545803
Short name T353
Test name
Test status
Simulation time 409520130724 ps
CPU time 780.68 seconds
Started May 30 03:14:48 PM PDT 24
Finished May 30 03:27:51 PM PDT 24
Peak memory 201816 kb
Host smart-9b56ea81-6638-4df0-a79b-611a6c002fc8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039545803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.4039545803
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2521750792
Short name T520
Test name
Test status
Simulation time 115980629678 ps
CPU time 416.18 seconds
Started May 30 03:14:48 PM PDT 24
Finished May 30 03:21:47 PM PDT 24
Peak memory 202188 kb
Host smart-3f8686ab-fa24-4286-b883-8e496fc663d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521750792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2521750792
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.888064366
Short name T719
Test name
Test status
Simulation time 24929633005 ps
CPU time 59.67 seconds
Started May 30 03:14:49 PM PDT 24
Finished May 30 03:15:50 PM PDT 24
Peak memory 201244 kb
Host smart-9aafa599-4343-4a06-8e44-19e360d70ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888064366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.888064366
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.2772480248
Short name T711
Test name
Test status
Simulation time 4247556060 ps
CPU time 10.89 seconds
Started May 30 03:14:49 PM PDT 24
Finished May 30 03:15:02 PM PDT 24
Peak memory 201596 kb
Host smart-b9ca844e-3c56-493e-9e70-ef599677e57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772480248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2772480248
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3053793659
Short name T54
Test name
Test status
Simulation time 4305301543 ps
CPU time 2.12 seconds
Started May 30 03:14:50 PM PDT 24
Finished May 30 03:14:54 PM PDT 24
Peak memory 217268 kb
Host smart-ddc1f203-7cd9-4028-b36e-38a6bebfdb8d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053793659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3053793659
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3564848927
Short name T2
Test name
Test status
Simulation time 5729809746 ps
CPU time 13.49 seconds
Started May 30 03:14:46 PM PDT 24
Finished May 30 03:15:01 PM PDT 24
Peak memory 201672 kb
Host smart-437d556d-0ceb-4ccf-ae2a-8006c08b631f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564848927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3564848927
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3507397682
Short name T42
Test name
Test status
Simulation time 260610235355 ps
CPU time 426.99 seconds
Started May 30 03:14:46 PM PDT 24
Finished May 30 03:21:55 PM PDT 24
Peak memory 202112 kb
Host smart-62d8f90b-23ee-4e8c-8781-f929742122ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507397682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3507397682
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3090952884
Short name T229
Test name
Test status
Simulation time 233608622499 ps
CPU time 167.43 seconds
Started May 30 03:14:48 PM PDT 24
Finished May 30 03:17:38 PM PDT 24
Peak memory 210392 kb
Host smart-61de4042-e695-4817-92dc-319701d51e78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090952884 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3090952884
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2624424032
Short name T409
Test name
Test status
Simulation time 502334319 ps
CPU time 1.62 seconds
Started May 30 03:23:19 PM PDT 24
Finished May 30 03:23:22 PM PDT 24
Peak memory 201504 kb
Host smart-0bbd15b5-5a39-4bf4-a743-5eb6037a25aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624424032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2624424032
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.4099668104
Short name T750
Test name
Test status
Simulation time 583454070294 ps
CPU time 698.45 seconds
Started May 30 03:23:07 PM PDT 24
Finished May 30 03:34:47 PM PDT 24
Peak memory 201876 kb
Host smart-9eefddbb-f4bc-416e-89c2-dab5292e7017
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099668104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.4099668104
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.4115733437
Short name T722
Test name
Test status
Simulation time 340613582468 ps
CPU time 717.54 seconds
Started May 30 03:23:23 PM PDT 24
Finished May 30 03:35:22 PM PDT 24
Peak memory 201860 kb
Host smart-87313823-20ee-4700-8f4d-f18db952a232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115733437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.4115733437
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3890578874
Short name T332
Test name
Test status
Simulation time 506075938934 ps
CPU time 1212.16 seconds
Started May 30 03:23:08 PM PDT 24
Finished May 30 03:43:22 PM PDT 24
Peak memory 201800 kb
Host smart-d1f46c28-6321-4dcd-aa0f-201aadb8e2b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890578874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3890578874
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.5441478
Short name T784
Test name
Test status
Simulation time 495052951494 ps
CPU time 1089.79 seconds
Started May 30 03:23:07 PM PDT 24
Finished May 30 03:41:18 PM PDT 24
Peak memory 201812 kb
Host smart-64ef9405-92be-4386-940e-21c101922a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5441478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.5441478
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2854078876
Short name T721
Test name
Test status
Simulation time 328706585611 ps
CPU time 192.27 seconds
Started May 30 03:23:08 PM PDT 24
Finished May 30 03:26:21 PM PDT 24
Peak memory 201792 kb
Host smart-69a87806-6d19-40f5-a233-df37e0c897cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854078876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2854078876
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.51297979
Short name T664
Test name
Test status
Simulation time 346924224115 ps
CPU time 631.76 seconds
Started May 30 03:23:07 PM PDT 24
Finished May 30 03:33:40 PM PDT 24
Peak memory 201872 kb
Host smart-81e4893c-530f-49a8-bc8a-7ccae2708767
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51297979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_w
akeup.51297979
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.425607583
Short name T525
Test name
Test status
Simulation time 205364912398 ps
CPU time 486.02 seconds
Started May 30 03:23:08 PM PDT 24
Finished May 30 03:31:15 PM PDT 24
Peak memory 201872 kb
Host smart-7bf5c78c-f7db-4608-95a3-a44bf8dfc948
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425607583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.425607583
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.3904566789
Short name T478
Test name
Test status
Simulation time 76604902863 ps
CPU time 457.12 seconds
Started May 30 03:23:23 PM PDT 24
Finished May 30 03:31:02 PM PDT 24
Peak memory 202156 kb
Host smart-906b1f52-5284-4d4e-8d64-6b97d4d9571e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904566789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3904566789
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1313677957
Short name T452
Test name
Test status
Simulation time 47075161818 ps
CPU time 113.88 seconds
Started May 30 03:23:22 PM PDT 24
Finished May 30 03:25:17 PM PDT 24
Peak memory 201636 kb
Host smart-77a86475-0666-43f9-a8a7-e147023d9553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313677957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1313677957
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.887701402
Short name T368
Test name
Test status
Simulation time 3021998735 ps
CPU time 4.36 seconds
Started May 30 03:23:19 PM PDT 24
Finished May 30 03:23:25 PM PDT 24
Peak memory 201560 kb
Host smart-ad9e0615-c3ee-433e-87ab-03e27ac7e6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887701402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.887701402
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2771726410
Short name T504
Test name
Test status
Simulation time 5802827581 ps
CPU time 14.96 seconds
Started May 30 03:23:09 PM PDT 24
Finished May 30 03:23:25 PM PDT 24
Peak memory 201628 kb
Host smart-e6317f65-5e15-42b8-8644-87e311086a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771726410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2771726410
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2398369215
Short name T295
Test name
Test status
Simulation time 410267373526 ps
CPU time 511.64 seconds
Started May 30 03:23:23 PM PDT 24
Finished May 30 03:31:56 PM PDT 24
Peak memory 202180 kb
Host smart-934628ba-0615-4cb5-bf36-3fdb83409324
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398369215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2398369215
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.470040122
Short name T183
Test name
Test status
Simulation time 311632833238 ps
CPU time 378.46 seconds
Started May 30 03:23:19 PM PDT 24
Finished May 30 03:29:39 PM PDT 24
Peak memory 210352 kb
Host smart-1c552418-7bc8-4157-95bb-02949c5767e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470040122 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.470040122
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3509088021
Short name T786
Test name
Test status
Simulation time 521706898 ps
CPU time 1.88 seconds
Started May 30 03:23:35 PM PDT 24
Finished May 30 03:23:38 PM PDT 24
Peak memory 201512 kb
Host smart-fb1613bb-913c-4dd6-8b7e-b60397b49e77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509088021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3509088021
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.4235793044
Short name T701
Test name
Test status
Simulation time 331301524717 ps
CPU time 207.95 seconds
Started May 30 03:23:23 PM PDT 24
Finished May 30 03:26:53 PM PDT 24
Peak memory 201860 kb
Host smart-4ecde410-8b8b-49e7-9b51-af57d0de7248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235793044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.4235793044
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3360093609
Short name T367
Test name
Test status
Simulation time 335740489042 ps
CPU time 207.64 seconds
Started May 30 03:23:19 PM PDT 24
Finished May 30 03:26:49 PM PDT 24
Peak memory 201808 kb
Host smart-9687744c-e97c-4ae2-84be-91db1756a431
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360093609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3360093609
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1815633722
Short name T691
Test name
Test status
Simulation time 329862424561 ps
CPU time 222.17 seconds
Started May 30 03:23:21 PM PDT 24
Finished May 30 03:27:05 PM PDT 24
Peak memory 201828 kb
Host smart-207871fd-dec6-4da9-ba7a-9f60b3eaca0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815633722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1815633722
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1362329507
Short name T601
Test name
Test status
Simulation time 327395984976 ps
CPU time 359.68 seconds
Started May 30 03:23:19 PM PDT 24
Finished May 30 03:29:20 PM PDT 24
Peak memory 201780 kb
Host smart-10c12b19-a6cb-4d4e-a8f3-4e4a96718182
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362329507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1362329507
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.76552524
Short name T263
Test name
Test status
Simulation time 565130694698 ps
CPU time 1409.09 seconds
Started May 30 03:23:20 PM PDT 24
Finished May 30 03:46:51 PM PDT 24
Peak memory 201900 kb
Host smart-79185a8a-60a5-4262-a4a0-e2ee4afba54c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76552524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_w
akeup.76552524
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1115735866
Short name T461
Test name
Test status
Simulation time 608756135960 ps
CPU time 741.88 seconds
Started May 30 03:23:22 PM PDT 24
Finished May 30 03:35:46 PM PDT 24
Peak memory 201776 kb
Host smart-8eaa900d-63db-4cb8-8e4e-ee365e4f88ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115735866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1115735866
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3703116245
Short name T76
Test name
Test status
Simulation time 107933656581 ps
CPU time 344.33 seconds
Started May 30 03:23:35 PM PDT 24
Finished May 30 03:29:20 PM PDT 24
Peak memory 202064 kb
Host smart-8701b2b9-75aa-4897-81e6-e93f280bbbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703116245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3703116245
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1345758013
Short name T776
Test name
Test status
Simulation time 31926914081 ps
CPU time 12.06 seconds
Started May 30 03:23:35 PM PDT 24
Finished May 30 03:23:49 PM PDT 24
Peak memory 201628 kb
Host smart-852e5b74-711e-480a-b8db-291001f62961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345758013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1345758013
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.202415229
Short name T397
Test name
Test status
Simulation time 4759025335 ps
CPU time 3.4 seconds
Started May 30 03:23:35 PM PDT 24
Finished May 30 03:23:40 PM PDT 24
Peak memory 201624 kb
Host smart-7e2dc217-d548-471e-9185-d9e60128580d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202415229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.202415229
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3016227898
Short name T602
Test name
Test status
Simulation time 5891342003 ps
CPU time 7.74 seconds
Started May 30 03:23:18 PM PDT 24
Finished May 30 03:23:27 PM PDT 24
Peak memory 201648 kb
Host smart-31c0ab13-1a99-4ab5-b659-1afb7f230cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016227898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3016227898
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2568962488
Short name T679
Test name
Test status
Simulation time 20312029426 ps
CPU time 42.9 seconds
Started May 30 03:23:36 PM PDT 24
Finished May 30 03:24:20 PM PDT 24
Peak memory 201876 kb
Host smart-aa3362f9-5784-4807-a7e2-a45bd816f570
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568962488 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2568962488
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1384497430
Short name T410
Test name
Test status
Simulation time 427342618 ps
CPU time 0.71 seconds
Started May 30 03:23:46 PM PDT 24
Finished May 30 03:23:48 PM PDT 24
Peak memory 201500 kb
Host smart-13c2c2d9-e76f-4199-9dba-30cbd29ee907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384497430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1384497430
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2877135888
Short name T175
Test name
Test status
Simulation time 188777309023 ps
CPU time 304.58 seconds
Started May 30 03:23:46 PM PDT 24
Finished May 30 03:28:52 PM PDT 24
Peak memory 201820 kb
Host smart-7b7b2a38-d70a-40b7-a7cb-3dd6452d66c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877135888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2877135888
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1711995203
Short name T251
Test name
Test status
Simulation time 527965113148 ps
CPU time 305.88 seconds
Started May 30 03:23:47 PM PDT 24
Finished May 30 03:28:54 PM PDT 24
Peak memory 201816 kb
Host smart-d0be807b-ee52-4629-a020-6c50f7d1eb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711995203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1711995203
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3528520403
Short name T224
Test name
Test status
Simulation time 168995955316 ps
CPU time 203.86 seconds
Started May 30 03:23:46 PM PDT 24
Finished May 30 03:27:11 PM PDT 24
Peak memory 201808 kb
Host smart-1599ffe5-9a5f-420f-9e5b-d33a0abe5088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528520403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3528520403
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1976358848
Short name T622
Test name
Test status
Simulation time 330267616525 ps
CPU time 208.94 seconds
Started May 30 03:23:45 PM PDT 24
Finished May 30 03:27:15 PM PDT 24
Peak memory 201740 kb
Host smart-46643abe-872e-42a4-9b4e-93b64f6126f5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976358848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1976358848
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2465913421
Short name T255
Test name
Test status
Simulation time 480339307545 ps
CPU time 527.18 seconds
Started May 30 03:23:45 PM PDT 24
Finished May 30 03:32:34 PM PDT 24
Peak memory 201800 kb
Host smart-3fd82a70-28b6-4ef1-be8f-ad5ef3ff9315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465913421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2465913421
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.771882371
Short name T365
Test name
Test status
Simulation time 493313979531 ps
CPU time 1109.05 seconds
Started May 30 03:23:48 PM PDT 24
Finished May 30 03:42:18 PM PDT 24
Peak memory 201792 kb
Host smart-b1246667-0c49-4f4d-a2b9-74b5977e7845
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=771882371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.771882371
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3107430810
Short name T538
Test name
Test status
Simulation time 588355181173 ps
CPU time 1431.97 seconds
Started May 30 03:23:45 PM PDT 24
Finished May 30 03:47:38 PM PDT 24
Peak memory 201824 kb
Host smart-c01f04e0-e115-498a-ae43-ff79cc07f971
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107430810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3107430810
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3754055847
Short name T325
Test name
Test status
Simulation time 124236515941 ps
CPU time 422 seconds
Started May 30 03:23:49 PM PDT 24
Finished May 30 03:30:51 PM PDT 24
Peak memory 202052 kb
Host smart-7df4af1f-0dd1-4488-88e6-62b8272352d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754055847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3754055847
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1529549752
Short name T334
Test name
Test status
Simulation time 33601600656 ps
CPU time 22.13 seconds
Started May 30 03:23:46 PM PDT 24
Finished May 30 03:24:09 PM PDT 24
Peak memory 201596 kb
Host smart-18834641-3fc5-4a26-8a56-b50afd9dd33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529549752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1529549752
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.4275654618
Short name T625
Test name
Test status
Simulation time 3300940715 ps
CPU time 1.87 seconds
Started May 30 03:23:45 PM PDT 24
Finished May 30 03:23:48 PM PDT 24
Peak memory 201632 kb
Host smart-4d3b999c-bddc-4754-937c-183c1beaf252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275654618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.4275654618
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2161490794
Short name T700
Test name
Test status
Simulation time 6045938684 ps
CPU time 15.07 seconds
Started May 30 03:23:48 PM PDT 24
Finished May 30 03:24:04 PM PDT 24
Peak memory 201584 kb
Host smart-fc6789f8-ec0b-434c-ac18-5b15608f5b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161490794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2161490794
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.244592061
Short name T648
Test name
Test status
Simulation time 329819040331 ps
CPU time 459.37 seconds
Started May 30 03:23:46 PM PDT 24
Finished May 30 03:31:27 PM PDT 24
Peak memory 201800 kb
Host smart-203122d3-0ce5-4273-8143-110978d0c4cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244592061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
244592061
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2202258300
Short name T14
Test name
Test status
Simulation time 24262254365 ps
CPU time 54.66 seconds
Started May 30 03:23:46 PM PDT 24
Finished May 30 03:24:42 PM PDT 24
Peak memory 210472 kb
Host smart-89a464a9-0add-411e-a5ca-7127a43c2ca3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202258300 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2202258300
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.507070879
Short name T349
Test name
Test status
Simulation time 481932797 ps
CPU time 0.82 seconds
Started May 30 03:24:05 PM PDT 24
Finished May 30 03:24:06 PM PDT 24
Peak memory 201484 kb
Host smart-37c053af-4ab7-4614-917e-1c4a16b3f091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507070879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.507070879
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3589159314
Short name T555
Test name
Test status
Simulation time 516821581317 ps
CPU time 610.92 seconds
Started May 30 03:24:04 PM PDT 24
Finished May 30 03:34:16 PM PDT 24
Peak memory 201860 kb
Host smart-322b11e2-f6b1-4480-8295-033fc831a3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589159314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3589159314
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2656960721
Short name T346
Test name
Test status
Simulation time 493752466736 ps
CPU time 1213.61 seconds
Started May 30 03:23:58 PM PDT 24
Finished May 30 03:44:13 PM PDT 24
Peak memory 201804 kb
Host smart-5460b5d5-3829-426a-8d21-59477fde2615
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656960721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2656960721
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.255848897
Short name T172
Test name
Test status
Simulation time 327376869004 ps
CPU time 181.68 seconds
Started May 30 03:23:46 PM PDT 24
Finished May 30 03:26:49 PM PDT 24
Peak memory 201852 kb
Host smart-aca52d85-f7a3-4a7b-88a4-14ef45a0a93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255848897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.255848897
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.343331211
Short name T710
Test name
Test status
Simulation time 327549526220 ps
CPU time 47.96 seconds
Started May 30 03:23:45 PM PDT 24
Finished May 30 03:24:35 PM PDT 24
Peak memory 201796 kb
Host smart-95d3ecdb-0d92-4fb0-9cba-6b5572e2b5a1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=343331211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.343331211
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2768052253
Short name T149
Test name
Test status
Simulation time 564562228569 ps
CPU time 126.62 seconds
Started May 30 03:23:57 PM PDT 24
Finished May 30 03:26:05 PM PDT 24
Peak memory 201760 kb
Host smart-56b22647-5bd9-4c48-ab2e-6b37e6b5b054
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768052253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2768052253
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.24495177
Short name T448
Test name
Test status
Simulation time 610234108705 ps
CPU time 728.16 seconds
Started May 30 03:23:57 PM PDT 24
Finished May 30 03:36:06 PM PDT 24
Peak memory 201876 kb
Host smart-e764703b-26f3-42aa-9aea-57d25a005d3c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24495177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.a
dc_ctrl_filters_wakeup_fixed.24495177
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.4254742845
Short name T534
Test name
Test status
Simulation time 138864612971 ps
CPU time 777.73 seconds
Started May 30 03:23:57 PM PDT 24
Finished May 30 03:36:56 PM PDT 24
Peak memory 202104 kb
Host smart-12ab223f-ae82-4f40-b113-53ba9e9455f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254742845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.4254742845
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.2061380329
Short name T609
Test name
Test status
Simulation time 32867319097 ps
CPU time 40.81 seconds
Started May 30 03:23:56 PM PDT 24
Finished May 30 03:24:38 PM PDT 24
Peak memory 201632 kb
Host smart-96927c93-1cc4-41a8-8d3e-efedf5cdb87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061380329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2061380329
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3433225963
Short name T537
Test name
Test status
Simulation time 4537762581 ps
CPU time 5.59 seconds
Started May 30 03:23:57 PM PDT 24
Finished May 30 03:24:04 PM PDT 24
Peak memory 201624 kb
Host smart-05693b24-8251-4a2f-bbc2-33512b6a645f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433225963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3433225963
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.656923052
Short name T773
Test name
Test status
Simulation time 5977704586 ps
CPU time 4.53 seconds
Started May 30 03:23:47 PM PDT 24
Finished May 30 03:23:52 PM PDT 24
Peak memory 201636 kb
Host smart-d69760a6-034e-4053-b7d5-804617c35f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656923052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.656923052
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3232401734
Short name T600
Test name
Test status
Simulation time 11815741608 ps
CPU time 9.42 seconds
Started May 30 03:23:59 PM PDT 24
Finished May 30 03:24:09 PM PDT 24
Peak memory 201800 kb
Host smart-14ac5b0a-c3f0-42e2-b7fb-4c0021bf89bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232401734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3232401734
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3549508806
Short name T799
Test name
Test status
Simulation time 68752792804 ps
CPU time 73.7 seconds
Started May 30 03:23:57 PM PDT 24
Finished May 30 03:25:12 PM PDT 24
Peak memory 210124 kb
Host smart-19e2de0e-1cc8-4d08-a6cf-af51eec945aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549508806 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3549508806
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1609988904
Short name T369
Test name
Test status
Simulation time 436929457 ps
CPU time 1.13 seconds
Started May 30 03:24:12 PM PDT 24
Finished May 30 03:24:14 PM PDT 24
Peak memory 201516 kb
Host smart-b052353d-b471-46d2-ba7b-019a113c2a66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609988904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1609988904
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2665627232
Short name T657
Test name
Test status
Simulation time 194238951241 ps
CPU time 462.86 seconds
Started May 30 03:24:11 PM PDT 24
Finished May 30 03:31:54 PM PDT 24
Peak memory 201764 kb
Host smart-cae6f6db-0bf0-40d6-b873-06741f069d48
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665627232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2665627232
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1765793983
Short name T294
Test name
Test status
Simulation time 175316717418 ps
CPU time 380.39 seconds
Started May 30 03:24:10 PM PDT 24
Finished May 30 03:30:31 PM PDT 24
Peak memory 201804 kb
Host smart-8804082d-68c0-4ef1-8974-44615b5dd9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765793983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1765793983
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3425424783
Short name T121
Test name
Test status
Simulation time 159468070268 ps
CPU time 108.66 seconds
Started May 30 03:24:09 PM PDT 24
Finished May 30 03:25:58 PM PDT 24
Peak memory 201812 kb
Host smart-61c6c5c6-3639-4a8d-8e92-c7a88d693d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425424783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3425424783
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2903838749
Short name T407
Test name
Test status
Simulation time 159232695276 ps
CPU time 192.49 seconds
Started May 30 03:24:11 PM PDT 24
Finished May 30 03:27:24 PM PDT 24
Peak memory 201788 kb
Host smart-c60664dc-06b5-4de9-9a50-975b9cd17c9c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903838749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2903838749
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2852925384
Short name T725
Test name
Test status
Simulation time 160619924693 ps
CPU time 102.57 seconds
Started May 30 03:23:57 PM PDT 24
Finished May 30 03:25:41 PM PDT 24
Peak memory 201884 kb
Host smart-d9203ae1-8817-49df-82ca-6562d690e414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852925384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2852925384
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.1854275948
Short name T581
Test name
Test status
Simulation time 492017788931 ps
CPU time 1185.83 seconds
Started May 30 03:24:04 PM PDT 24
Finished May 30 03:43:51 PM PDT 24
Peak memory 201756 kb
Host smart-4d148b91-c99c-44df-9670-a5812576e721
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854275948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.1854275948
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3794057302
Short name T285
Test name
Test status
Simulation time 345631805738 ps
CPU time 204.12 seconds
Started May 30 03:24:09 PM PDT 24
Finished May 30 03:27:34 PM PDT 24
Peak memory 201904 kb
Host smart-025214c5-fc55-495b-9bce-5db991ac8dc1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794057302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3794057302
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1248719185
Short name T634
Test name
Test status
Simulation time 608999903006 ps
CPU time 449.88 seconds
Started May 30 03:24:10 PM PDT 24
Finished May 30 03:31:41 PM PDT 24
Peak memory 201832 kb
Host smart-2447172a-9860-42e0-a808-f99af0c0b824
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248719185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1248719185
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.57514156
Short name T187
Test name
Test status
Simulation time 87554986359 ps
CPU time 473.55 seconds
Started May 30 03:24:10 PM PDT 24
Finished May 30 03:32:05 PM PDT 24
Peak memory 202192 kb
Host smart-d840b5b2-6aa2-42c1-85d7-d8cb41b5caea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57514156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.57514156
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.2918288861
Short name T145
Test name
Test status
Simulation time 31140070882 ps
CPU time 39.19 seconds
Started May 30 03:24:09 PM PDT 24
Finished May 30 03:24:49 PM PDT 24
Peak memory 201624 kb
Host smart-20d8da8c-6019-4d9f-965d-1d781bfaa00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918288861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2918288861
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.180262614
Short name T567
Test name
Test status
Simulation time 3944798675 ps
CPU time 3.01 seconds
Started May 30 03:24:09 PM PDT 24
Finished May 30 03:24:13 PM PDT 24
Peak memory 201624 kb
Host smart-bf95624d-67bf-4afd-b8c1-0b0223c204ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180262614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.180262614
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.351846601
Short name T413
Test name
Test status
Simulation time 5956038197 ps
CPU time 3.91 seconds
Started May 30 03:24:04 PM PDT 24
Finished May 30 03:24:09 PM PDT 24
Peak memory 201624 kb
Host smart-51bdee15-938b-448b-9ece-16529896267d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351846601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.351846601
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2968469292
Short name T546
Test name
Test status
Simulation time 350216753602 ps
CPU time 140.09 seconds
Started May 30 03:24:13 PM PDT 24
Finished May 30 03:26:34 PM PDT 24
Peak memory 201880 kb
Host smart-01c63604-8b28-4df1-9185-be96e235ef39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968469292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2968469292
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1891235125
Short name T27
Test name
Test status
Simulation time 102689879234 ps
CPU time 254.09 seconds
Started May 30 03:24:09 PM PDT 24
Finished May 30 03:28:24 PM PDT 24
Peak memory 217812 kb
Host smart-da2f6ed9-9c78-4c85-a811-5ddc4bf88772
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891235125 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1891235125
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2040593866
Short name T438
Test name
Test status
Simulation time 309650923 ps
CPU time 0.78 seconds
Started May 30 03:24:22 PM PDT 24
Finished May 30 03:24:24 PM PDT 24
Peak memory 201504 kb
Host smart-fde99b4c-e72a-4236-bbf0-bdb126d57495
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040593866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2040593866
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3177867309
Short name T583
Test name
Test status
Simulation time 540874386752 ps
CPU time 336.85 seconds
Started May 30 03:24:21 PM PDT 24
Finished May 30 03:29:59 PM PDT 24
Peak memory 201784 kb
Host smart-a99e44b0-ab2c-419b-ae80-9f8fa88a0c75
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177867309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3177867309
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.4232814520
Short name T470
Test name
Test status
Simulation time 162878357835 ps
CPU time 382.98 seconds
Started May 30 03:24:22 PM PDT 24
Finished May 30 03:30:47 PM PDT 24
Peak memory 201808 kb
Host smart-ec40b4f1-76c3-4ed1-8001-db36f3d65af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232814520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.4232814520
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1232217590
Short name T482
Test name
Test status
Simulation time 331482417619 ps
CPU time 182.38 seconds
Started May 30 03:24:20 PM PDT 24
Finished May 30 03:27:23 PM PDT 24
Peak memory 201828 kb
Host smart-6a77f954-e118-4cfa-918a-ab85964a5f92
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232217590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1232217590
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3687989577
Short name T456
Test name
Test status
Simulation time 165206296042 ps
CPU time 379.44 seconds
Started May 30 03:24:11 PM PDT 24
Finished May 30 03:30:32 PM PDT 24
Peak memory 201868 kb
Host smart-18590086-cf9e-40de-b1eb-c841061d7826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687989577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3687989577
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.4076432919
Short name T480
Test name
Test status
Simulation time 166337174741 ps
CPU time 103.03 seconds
Started May 30 03:24:11 PM PDT 24
Finished May 30 03:25:55 PM PDT 24
Peak memory 201784 kb
Host smart-c800bb04-9de0-4d90-b48a-5eff7e687a27
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076432919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.4076432919
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3110713514
Short name T154
Test name
Test status
Simulation time 536532545520 ps
CPU time 506.69 seconds
Started May 30 03:24:21 PM PDT 24
Finished May 30 03:32:49 PM PDT 24
Peak memory 201892 kb
Host smart-e492a0fb-4044-40f3-b8ed-8b5a16dbe4f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110713514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3110713514
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.947960025
Short name T585
Test name
Test status
Simulation time 200142237715 ps
CPU time 64.73 seconds
Started May 30 03:24:22 PM PDT 24
Finished May 30 03:25:28 PM PDT 24
Peak memory 201824 kb
Host smart-302b36b2-e57f-489e-91f6-f788a7be4d72
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947960025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.947960025
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.307693212
Short name T552
Test name
Test status
Simulation time 131536292859 ps
CPU time 436.24 seconds
Started May 30 03:24:21 PM PDT 24
Finished May 30 03:31:38 PM PDT 24
Peak memory 202088 kb
Host smart-9f9a2358-369b-45c8-93b1-d47f922068dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307693212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.307693212
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.4175700556
Short name T734
Test name
Test status
Simulation time 32349658548 ps
CPU time 40.03 seconds
Started May 30 03:24:21 PM PDT 24
Finished May 30 03:25:02 PM PDT 24
Peak memory 201608 kb
Host smart-33c1dc82-b10c-47d9-8c7f-00a5cd3c62f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175700556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.4175700556
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.614747431
Short name T460
Test name
Test status
Simulation time 4471755733 ps
CPU time 12.57 seconds
Started May 30 03:24:21 PM PDT 24
Finished May 30 03:24:35 PM PDT 24
Peak memory 201636 kb
Host smart-50213c0f-4b2e-4cfe-95e3-7d19e2703b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614747431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.614747431
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2960139285
Short name T759
Test name
Test status
Simulation time 5926150808 ps
CPU time 14.39 seconds
Started May 30 03:24:11 PM PDT 24
Finished May 30 03:24:26 PM PDT 24
Peak memory 201656 kb
Host smart-82ef0548-a110-45f2-a87c-545a41ce1de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960139285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2960139285
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1359279387
Short name T654
Test name
Test status
Simulation time 132019565382 ps
CPU time 425.44 seconds
Started May 30 03:24:21 PM PDT 24
Finished May 30 03:31:27 PM PDT 24
Peak memory 202104 kb
Host smart-a2f0c501-73af-4a98-8de0-047111f21bcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359279387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1359279387
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.491260403
Short name T704
Test name
Test status
Simulation time 46018966014 ps
CPU time 47.28 seconds
Started May 30 03:24:22 PM PDT 24
Finished May 30 03:25:10 PM PDT 24
Peak memory 202012 kb
Host smart-35caa23b-bfb3-4708-839a-0fa874164e87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491260403 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.491260403
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.679715576
Short name T386
Test name
Test status
Simulation time 437195160 ps
CPU time 0.92 seconds
Started May 30 03:24:33 PM PDT 24
Finished May 30 03:24:35 PM PDT 24
Peak memory 201504 kb
Host smart-af209a4d-c7a4-4ce1-a1ea-24fd64345fdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679715576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.679715576
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.357130658
Short name T208
Test name
Test status
Simulation time 656089857230 ps
CPU time 710.3 seconds
Started May 30 03:24:31 PM PDT 24
Finished May 30 03:36:23 PM PDT 24
Peak memory 201824 kb
Host smart-2c798768-ba8c-4a7a-a301-bc6527cc7375
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357130658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.357130658
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2608403320
Short name T515
Test name
Test status
Simulation time 167756295455 ps
CPU time 416.33 seconds
Started May 30 03:24:32 PM PDT 24
Finished May 30 03:31:30 PM PDT 24
Peak memory 201776 kb
Host smart-87fcd037-38a4-4ce8-85e4-acd5a57354df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608403320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2608403320
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3582598491
Short name T529
Test name
Test status
Simulation time 158060750436 ps
CPU time 68.44 seconds
Started May 30 03:24:35 PM PDT 24
Finished May 30 03:25:44 PM PDT 24
Peak memory 201804 kb
Host smart-3d96a2a4-cc48-4bd4-968f-0e3735008382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582598491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3582598491
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.474001685
Short name T569
Test name
Test status
Simulation time 487509871679 ps
CPU time 278.39 seconds
Started May 30 03:24:31 PM PDT 24
Finished May 30 03:29:11 PM PDT 24
Peak memory 201872 kb
Host smart-b51fbc7e-fccc-4e30-a1e7-f8ad56851814
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=474001685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.474001685
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.1900774716
Short name T198
Test name
Test status
Simulation time 162265220928 ps
CPU time 172.69 seconds
Started May 30 03:24:32 PM PDT 24
Finished May 30 03:27:26 PM PDT 24
Peak memory 201832 kb
Host smart-69c8aa51-03cc-4ec8-a099-6017007bb904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900774716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1900774716
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2674340622
Short name T590
Test name
Test status
Simulation time 163357921764 ps
CPU time 361.65 seconds
Started May 30 03:24:32 PM PDT 24
Finished May 30 03:30:35 PM PDT 24
Peak memory 201752 kb
Host smart-513c28fd-4839-454d-9745-fe9dbd090f67
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674340622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2674340622
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3821084424
Short name T317
Test name
Test status
Simulation time 346191401861 ps
CPU time 162.98 seconds
Started May 30 03:24:32 PM PDT 24
Finished May 30 03:27:16 PM PDT 24
Peak memory 201812 kb
Host smart-f710a691-96b9-4143-9a6a-b14010d958ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821084424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3821084424
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.219549316
Short name T341
Test name
Test status
Simulation time 201541842497 ps
CPU time 446.83 seconds
Started May 30 03:24:32 PM PDT 24
Finished May 30 03:32:00 PM PDT 24
Peak memory 201772 kb
Host smart-10ccd20f-2007-4c8e-91dc-8da3ba369243
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219549316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.219549316
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.751204224
Short name T771
Test name
Test status
Simulation time 67399025897 ps
CPU time 408.79 seconds
Started May 30 03:24:31 PM PDT 24
Finished May 30 03:31:21 PM PDT 24
Peak memory 202132 kb
Host smart-01e92548-ecd8-433a-89b9-696b2c3cc63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751204224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.751204224
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3674659497
Short name T764
Test name
Test status
Simulation time 27246645974 ps
CPU time 67.85 seconds
Started May 30 03:24:32 PM PDT 24
Finished May 30 03:25:41 PM PDT 24
Peak memory 201600 kb
Host smart-d731edb4-f795-4d07-8da6-dda6ea7e267f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674659497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3674659497
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.889502281
Short name T120
Test name
Test status
Simulation time 4004490913 ps
CPU time 10.2 seconds
Started May 30 03:24:32 PM PDT 24
Finished May 30 03:24:43 PM PDT 24
Peak memory 201628 kb
Host smart-e2d3e3ec-d9f1-4018-a737-293f487dd226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889502281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.889502281
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3049344930
Short name T425
Test name
Test status
Simulation time 5892185067 ps
CPU time 2.78 seconds
Started May 30 03:24:32 PM PDT 24
Finished May 30 03:24:36 PM PDT 24
Peak memory 201656 kb
Host smart-81742188-a45a-4392-8d83-83608cdfc4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049344930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3049344930
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1255895472
Short name T730
Test name
Test status
Simulation time 329167005046 ps
CPU time 209.11 seconds
Started May 30 03:24:31 PM PDT 24
Finished May 30 03:28:01 PM PDT 24
Peak memory 201808 kb
Host smart-c4f57769-919f-4bc7-9c45-c2474963a9c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255895472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1255895472
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1075190127
Short name T223
Test name
Test status
Simulation time 505188400186 ps
CPU time 236.29 seconds
Started May 30 03:24:31 PM PDT 24
Finished May 30 03:28:28 PM PDT 24
Peak memory 217888 kb
Host smart-ef8edc28-2d9d-4311-b9e3-90ac1136eef6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075190127 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1075190127
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2605132353
Short name T402
Test name
Test status
Simulation time 531528909 ps
CPU time 1.77 seconds
Started May 30 03:24:42 PM PDT 24
Finished May 30 03:24:44 PM PDT 24
Peak memory 201512 kb
Host smart-1e3fc580-8e20-42d0-8ece-751babc072ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605132353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2605132353
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2792267682
Short name T264
Test name
Test status
Simulation time 172265456021 ps
CPU time 106.57 seconds
Started May 30 03:24:42 PM PDT 24
Finished May 30 03:26:29 PM PDT 24
Peak memory 201808 kb
Host smart-0b508ba1-43b8-4279-9eea-a2b336661151
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792267682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2792267682
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1066327494
Short name T278
Test name
Test status
Simulation time 323761759026 ps
CPU time 214.09 seconds
Started May 30 03:24:44 PM PDT 24
Finished May 30 03:28:19 PM PDT 24
Peak memory 201816 kb
Host smart-1204ea4c-f0e8-49ab-b29c-387c52d07743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066327494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1066327494
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1761275050
Short name T233
Test name
Test status
Simulation time 487887992211 ps
CPU time 467.33 seconds
Started May 30 03:24:42 PM PDT 24
Finished May 30 03:32:31 PM PDT 24
Peak memory 201788 kb
Host smart-42d64a26-6274-43bb-affb-33b2e5ecd732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761275050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1761275050
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2306674859
Short name T668
Test name
Test status
Simulation time 487043601624 ps
CPU time 306.98 seconds
Started May 30 03:24:42 PM PDT 24
Finished May 30 03:29:50 PM PDT 24
Peak memory 201812 kb
Host smart-fff9c4f5-1ddf-44fd-8f35-4b4343480ac8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306674859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2306674859
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3738659523
Short name T207
Test name
Test status
Simulation time 164435019091 ps
CPU time 102.33 seconds
Started May 30 03:24:32 PM PDT 24
Finished May 30 03:26:16 PM PDT 24
Peak memory 201772 kb
Host smart-71850c16-9798-459c-9854-f2b24fb5cf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738659523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3738659523
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.4231941934
Short name T756
Test name
Test status
Simulation time 163898498475 ps
CPU time 374.27 seconds
Started May 30 03:24:33 PM PDT 24
Finished May 30 03:30:48 PM PDT 24
Peak memory 201732 kb
Host smart-9a359d16-d761-4023-a1ec-8b65e191832c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231941934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.4231941934
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3767887796
Short name T13
Test name
Test status
Simulation time 186872138733 ps
CPU time 30.69 seconds
Started May 30 03:24:42 PM PDT 24
Finished May 30 03:25:14 PM PDT 24
Peak memory 201888 kb
Host smart-ee08d07d-939a-4918-87ce-1f122b11e7c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767887796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3767887796
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.388898263
Short name T666
Test name
Test status
Simulation time 198735119216 ps
CPU time 509.87 seconds
Started May 30 03:24:45 PM PDT 24
Finished May 30 03:33:16 PM PDT 24
Peak memory 201824 kb
Host smart-2f383bc8-7b24-4a6f-812a-6a0aa760ecd8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388898263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.388898263
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.566428031
Short name T728
Test name
Test status
Simulation time 122998519868 ps
CPU time 674.82 seconds
Started May 30 03:24:44 PM PDT 24
Finished May 30 03:36:00 PM PDT 24
Peak memory 202196 kb
Host smart-822ef362-5e2e-4473-8515-980502932e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566428031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.566428031
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2638036542
Short name T422
Test name
Test status
Simulation time 33882938042 ps
CPU time 10.13 seconds
Started May 30 03:24:45 PM PDT 24
Finished May 30 03:24:56 PM PDT 24
Peak memory 201616 kb
Host smart-0e4e2a1e-082b-4349-b455-615cc944ef05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638036542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2638036542
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1634884265
Short name T399
Test name
Test status
Simulation time 4888932924 ps
CPU time 5.37 seconds
Started May 30 03:24:43 PM PDT 24
Finished May 30 03:24:49 PM PDT 24
Peak memory 201612 kb
Host smart-9e4925ae-0720-41b1-bec7-f07dcece6aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634884265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1634884265
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.4227168155
Short name T442
Test name
Test status
Simulation time 5656247085 ps
CPU time 2.96 seconds
Started May 30 03:24:31 PM PDT 24
Finished May 30 03:24:35 PM PDT 24
Peak memory 201636 kb
Host smart-34ed72c2-539b-4b3b-b24d-5206fe37c76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227168155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.4227168155
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3235384122
Short name T644
Test name
Test status
Simulation time 531542084404 ps
CPU time 551.23 seconds
Started May 30 03:24:45 PM PDT 24
Finished May 30 03:33:57 PM PDT 24
Peak memory 201888 kb
Host smart-d9045a50-7125-4fdc-8341-12f88f14f202
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235384122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3235384122
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3662991431
Short name T447
Test name
Test status
Simulation time 392688423 ps
CPU time 1.03 seconds
Started May 30 03:24:54 PM PDT 24
Finished May 30 03:24:56 PM PDT 24
Peak memory 201524 kb
Host smart-d11ef8f8-f1f2-482b-8c1f-cf75616a17b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662991431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3662991431
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2075596453
Short name T127
Test name
Test status
Simulation time 377667066061 ps
CPU time 249.43 seconds
Started May 30 03:24:53 PM PDT 24
Finished May 30 03:29:04 PM PDT 24
Peak memory 201816 kb
Host smart-14792ef7-4fcb-4d9d-9395-a714ed835eff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075596453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2075596453
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.99949413
Short name T303
Test name
Test status
Simulation time 493387498798 ps
CPU time 581.39 seconds
Started May 30 03:24:42 PM PDT 24
Finished May 30 03:34:25 PM PDT 24
Peak memory 201832 kb
Host smart-8ad76254-ffb9-4c26-b484-e3c25e3c90dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99949413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.99949413
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1073113161
Short name T785
Test name
Test status
Simulation time 324523285909 ps
CPU time 206.85 seconds
Started May 30 03:24:52 PM PDT 24
Finished May 30 03:28:20 PM PDT 24
Peak memory 201764 kb
Host smart-d3f770a2-644f-4dbd-8f51-c0f9b5a0bea0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073113161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1073113161
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3414222254
Short name T640
Test name
Test status
Simulation time 164325783833 ps
CPU time 166.19 seconds
Started May 30 03:24:42 PM PDT 24
Finished May 30 03:27:29 PM PDT 24
Peak memory 201784 kb
Host smart-38414e11-42fd-45a0-8bac-3c327d584045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414222254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3414222254
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.838172239
Short name T727
Test name
Test status
Simulation time 331347481861 ps
CPU time 319.81 seconds
Started May 30 03:24:45 PM PDT 24
Finished May 30 03:30:06 PM PDT 24
Peak memory 201816 kb
Host smart-beb69b40-b4cd-4b02-8eba-d43f3f6727eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=838172239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.838172239
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.226492999
Short name T135
Test name
Test status
Simulation time 542272937647 ps
CPU time 627.87 seconds
Started May 30 03:24:54 PM PDT 24
Finished May 30 03:35:23 PM PDT 24
Peak memory 201968 kb
Host smart-6235ae80-2c36-4ae8-b6b7-9fda3c531775
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226492999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.226492999
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2017556957
Short name T747
Test name
Test status
Simulation time 197809852881 ps
CPU time 242.52 seconds
Started May 30 03:24:54 PM PDT 24
Finished May 30 03:28:58 PM PDT 24
Peak memory 201760 kb
Host smart-0945b1ab-ce6c-456e-af92-64ffc8764d48
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017556957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2017556957
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1317024546
Short name T473
Test name
Test status
Simulation time 118927842162 ps
CPU time 631.34 seconds
Started May 30 03:24:53 PM PDT 24
Finished May 30 03:35:26 PM PDT 24
Peak memory 202108 kb
Host smart-4f2923f7-9793-4c5d-b12e-92283b8b053d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317024546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1317024546
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3035551013
Short name T490
Test name
Test status
Simulation time 32149726287 ps
CPU time 33.33 seconds
Started May 30 03:24:54 PM PDT 24
Finished May 30 03:25:28 PM PDT 24
Peak memory 201648 kb
Host smart-a7edd52c-6dfa-4a5c-81a1-8baa9daae2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035551013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3035551013
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2846191531
Short name T658
Test name
Test status
Simulation time 5396516823 ps
CPU time 3.77 seconds
Started May 30 03:24:54 PM PDT 24
Finished May 30 03:24:58 PM PDT 24
Peak memory 201600 kb
Host smart-ff1fa0cd-136c-40fa-8523-a1138d4d0b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846191531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2846191531
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2649975780
Short name T618
Test name
Test status
Simulation time 6028906921 ps
CPU time 13.63 seconds
Started May 30 03:24:41 PM PDT 24
Finished May 30 03:24:56 PM PDT 24
Peak memory 201604 kb
Host smart-83ef2535-210a-4837-9f29-0b420166b7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649975780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2649975780
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3972781054
Short name T83
Test name
Test status
Simulation time 67421552731 ps
CPU time 154.24 seconds
Started May 30 03:24:52 PM PDT 24
Finished May 30 03:27:27 PM PDT 24
Peak memory 210120 kb
Host smart-1e602c14-14f4-4b45-be5d-3a829328beae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972781054 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3972781054
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1451440095
Short name T79
Test name
Test status
Simulation time 564563911 ps
CPU time 0.7 seconds
Started May 30 03:25:14 PM PDT 24
Finished May 30 03:25:15 PM PDT 24
Peak memory 201520 kb
Host smart-21e8eca7-10ed-43a6-8fdf-761791738f11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451440095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1451440095
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1918375213
Short name T165
Test name
Test status
Simulation time 355258235927 ps
CPU time 158.87 seconds
Started May 30 03:25:04 PM PDT 24
Finished May 30 03:27:44 PM PDT 24
Peak memory 201908 kb
Host smart-4af81218-f56c-46f4-a293-cb0c409f1812
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918375213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1918375213
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3122079572
Short name T210
Test name
Test status
Simulation time 364056973303 ps
CPU time 842.45 seconds
Started May 30 03:25:03 PM PDT 24
Finished May 30 03:39:06 PM PDT 24
Peak memory 201936 kb
Host smart-f55909c0-6eef-4056-bdf6-38954041f40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122079572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3122079572
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3471830232
Short name T215
Test name
Test status
Simulation time 490205481067 ps
CPU time 323.24 seconds
Started May 30 03:25:03 PM PDT 24
Finished May 30 03:30:27 PM PDT 24
Peak memory 201800 kb
Host smart-cf32a7fd-a7b3-41b5-8653-5713998a8c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471830232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3471830232
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.4195022491
Short name T755
Test name
Test status
Simulation time 328313669011 ps
CPU time 379.61 seconds
Started May 30 03:25:07 PM PDT 24
Finished May 30 03:31:27 PM PDT 24
Peak memory 201792 kb
Host smart-f21c34db-c094-4cf4-a207-39851546f2e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195022491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.4195022491
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2077439526
Short name T576
Test name
Test status
Simulation time 331119534942 ps
CPU time 404.37 seconds
Started May 30 03:25:08 PM PDT 24
Finished May 30 03:31:53 PM PDT 24
Peak memory 201736 kb
Host smart-ca9f2009-0bf2-47c6-ad17-e1fd96492d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077439526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2077439526
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1715764567
Short name T352
Test name
Test status
Simulation time 487858929341 ps
CPU time 1187.85 seconds
Started May 30 03:25:07 PM PDT 24
Finished May 30 03:44:56 PM PDT 24
Peak memory 201764 kb
Host smart-38499850-8c22-4394-b377-92ca23db1de7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715764567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1715764567
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1048372176
Short name T743
Test name
Test status
Simulation time 351912654636 ps
CPU time 850.81 seconds
Started May 30 03:25:06 PM PDT 24
Finished May 30 03:39:18 PM PDT 24
Peak memory 201884 kb
Host smart-e1aad9a5-4a40-4843-8c40-b913587466df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048372176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1048372176
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.467886977
Short name T753
Test name
Test status
Simulation time 199903115339 ps
CPU time 429.45 seconds
Started May 30 03:25:05 PM PDT 24
Finished May 30 03:32:15 PM PDT 24
Peak memory 201820 kb
Host smart-1f3ec5a7-54dd-45ee-98e1-94fce7186b3c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467886977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.467886977
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.433111384
Short name T189
Test name
Test status
Simulation time 88826517608 ps
CPU time 341.4 seconds
Started May 30 03:25:03 PM PDT 24
Finished May 30 03:30:46 PM PDT 24
Peak memory 202052 kb
Host smart-d009911c-e330-408a-ba54-2cc355b95f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433111384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.433111384
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3122604195
Short name T356
Test name
Test status
Simulation time 24666285340 ps
CPU time 27.68 seconds
Started May 30 03:25:03 PM PDT 24
Finished May 30 03:25:32 PM PDT 24
Peak memory 201648 kb
Host smart-8ec648ea-5a5b-4150-8942-990b867b77c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122604195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3122604195
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1121516891
Short name T485
Test name
Test status
Simulation time 3589719495 ps
CPU time 5.13 seconds
Started May 30 03:25:05 PM PDT 24
Finished May 30 03:25:11 PM PDT 24
Peak memory 201640 kb
Host smart-824567eb-c355-4ea6-bb60-58da38897a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121516891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1121516891
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3099910396
Short name T338
Test name
Test status
Simulation time 5930473694 ps
CPU time 4.33 seconds
Started May 30 03:24:54 PM PDT 24
Finished May 30 03:24:59 PM PDT 24
Peak memory 201600 kb
Host smart-a9b4fb90-b196-40a2-821a-952e770e9520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099910396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3099910396
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.395769028
Short name T597
Test name
Test status
Simulation time 130831163108 ps
CPU time 534.3 seconds
Started May 30 03:25:07 PM PDT 24
Finished May 30 03:34:03 PM PDT 24
Peak memory 210328 kb
Host smart-8bbdb18b-a8d7-4260-994a-2d7fa175acbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395769028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
395769028
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.743903958
Short name T257
Test name
Test status
Simulation time 444361587565 ps
CPU time 248.69 seconds
Started May 30 03:25:07 PM PDT 24
Finished May 30 03:29:17 PM PDT 24
Peak memory 211148 kb
Host smart-ab894173-f260-4262-8804-21bbc88756b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743903958 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.743903958
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3983903224
Short name T401
Test name
Test status
Simulation time 473859517 ps
CPU time 1.76 seconds
Started May 30 03:14:49 PM PDT 24
Finished May 30 03:14:52 PM PDT 24
Peak memory 201468 kb
Host smart-61459799-ef21-481c-95dc-752468c9cd22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983903224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3983903224
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1208864119
Short name T284
Test name
Test status
Simulation time 166087191625 ps
CPU time 404.19 seconds
Started May 30 03:14:49 PM PDT 24
Finished May 30 03:21:35 PM PDT 24
Peak memory 201376 kb
Host smart-49b4a6c2-dae0-491c-819d-97773b3dcd5c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208864119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1208864119
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2822195314
Short name T276
Test name
Test status
Simulation time 494559503818 ps
CPU time 1115.91 seconds
Started May 30 03:14:50 PM PDT 24
Finished May 30 03:33:28 PM PDT 24
Peak memory 201768 kb
Host smart-e4c6b6bc-e831-4e6c-a451-07053088e55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822195314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2822195314
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.4142227687
Short name T703
Test name
Test status
Simulation time 325431129862 ps
CPU time 788.32 seconds
Started May 30 03:14:47 PM PDT 24
Finished May 30 03:27:57 PM PDT 24
Peak memory 201812 kb
Host smart-4748ccfe-6bfc-4079-9338-9b3f85fddc01
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142227687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.4142227687
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.804759276
Short name T444
Test name
Test status
Simulation time 161745245930 ps
CPU time 373.57 seconds
Started May 30 03:14:47 PM PDT 24
Finished May 30 03:21:02 PM PDT 24
Peak memory 201796 kb
Host smart-28dd4d84-aca1-46ba-9646-106cdf09ebe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804759276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.804759276
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3811216696
Short name T373
Test name
Test status
Simulation time 334849312351 ps
CPU time 726.21 seconds
Started May 30 03:14:48 PM PDT 24
Finished May 30 03:26:56 PM PDT 24
Peak memory 201876 kb
Host smart-ff21991c-37c4-435b-b988-96e09cd971b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811216696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3811216696
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3378397400
Short name T139
Test name
Test status
Simulation time 358176901983 ps
CPU time 817.63 seconds
Started May 30 03:14:46 PM PDT 24
Finished May 30 03:28:25 PM PDT 24
Peak memory 201836 kb
Host smart-f577c982-4c06-402f-a84d-254a3b9827d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378397400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3378397400
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3043570087
Short name T568
Test name
Test status
Simulation time 193437794751 ps
CPU time 143.62 seconds
Started May 30 03:14:46 PM PDT 24
Finished May 30 03:17:11 PM PDT 24
Peak memory 201788 kb
Host smart-271afe96-1ac0-4fa3-9e7a-2221d32feb46
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043570087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.3043570087
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2085465852
Short name T396
Test name
Test status
Simulation time 133623563526 ps
CPU time 493.65 seconds
Started May 30 03:14:47 PM PDT 24
Finished May 30 03:23:03 PM PDT 24
Peak memory 202144 kb
Host smart-ea0057b9-c00e-41d9-9051-d16bca79c9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085465852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2085465852
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1434181603
Short name T559
Test name
Test status
Simulation time 40677348657 ps
CPU time 94.65 seconds
Started May 30 03:14:49 PM PDT 24
Finished May 30 03:16:26 PM PDT 24
Peak memory 201588 kb
Host smart-c2efa5d0-8692-46c7-914d-dbab709f6106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434181603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1434181603
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2909876636
Short name T364
Test name
Test status
Simulation time 3143568103 ps
CPU time 1.29 seconds
Started May 30 03:14:47 PM PDT 24
Finished May 30 03:14:50 PM PDT 24
Peak memory 201636 kb
Host smart-ed150f05-0856-4751-a307-3af2e2b52570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909876636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2909876636
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1502201701
Short name T4
Test name
Test status
Simulation time 5990903516 ps
CPU time 4.24 seconds
Started May 30 03:14:49 PM PDT 24
Finished May 30 03:14:55 PM PDT 24
Peak memory 201660 kb
Host smart-334a65df-a49c-41c9-b88e-df079f786d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502201701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1502201701
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2414617034
Short name T124
Test name
Test status
Simulation time 530643114060 ps
CPU time 285.57 seconds
Started May 30 03:14:50 PM PDT 24
Finished May 30 03:19:38 PM PDT 24
Peak memory 201888 kb
Host smart-5b4c4ef3-4245-44af-8e11-1c6fb639ec11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414617034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2414617034
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1758943302
Short name T33
Test name
Test status
Simulation time 33397431514 ps
CPU time 88.71 seconds
Started May 30 03:14:50 PM PDT 24
Finished May 30 03:16:21 PM PDT 24
Peak memory 210428 kb
Host smart-8e582421-cea7-41cf-bdea-b2f6965b0a4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758943302 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1758943302
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1485370366
Short name T545
Test name
Test status
Simulation time 499734469 ps
CPU time 1.68 seconds
Started May 30 03:14:48 PM PDT 24
Finished May 30 03:14:52 PM PDT 24
Peak memory 201496 kb
Host smart-243fc460-f292-4308-a1f0-b09a40a93989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485370366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1485370366
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2185232168
Short name T282
Test name
Test status
Simulation time 609960770111 ps
CPU time 1183.47 seconds
Started May 30 03:14:49 PM PDT 24
Finished May 30 03:34:35 PM PDT 24
Peak memory 201736 kb
Host smart-4ec1947a-bae2-4411-924c-afb0ab2fc64a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185232168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2185232168
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1303230650
Short name T202
Test name
Test status
Simulation time 180632340581 ps
CPU time 124.83 seconds
Started May 30 03:14:48 PM PDT 24
Finished May 30 03:16:55 PM PDT 24
Peak memory 201648 kb
Host smart-709bb4a4-7e80-404d-847f-5bc37a82db75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303230650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1303230650
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.4082205945
Short name T141
Test name
Test status
Simulation time 327837473272 ps
CPU time 349.01 seconds
Started May 30 03:14:50 PM PDT 24
Finished May 30 03:20:41 PM PDT 24
Peak memory 201824 kb
Host smart-1669cd37-82b7-4147-b095-343ab2ca6110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082205945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.4082205945
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3415493621
Short name T449
Test name
Test status
Simulation time 325484073412 ps
CPU time 756.36 seconds
Started May 30 03:14:46 PM PDT 24
Finished May 30 03:27:24 PM PDT 24
Peak memory 201756 kb
Host smart-0957c482-e7d1-4d48-9d9c-d1a3731d9c67
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415493621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3415493621
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1005974877
Short name T299
Test name
Test status
Simulation time 167919152860 ps
CPU time 109.62 seconds
Started May 30 03:14:49 PM PDT 24
Finished May 30 03:16:41 PM PDT 24
Peak memory 201776 kb
Host smart-2af8a627-6d93-4f2a-bc34-8dac3b4f8a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005974877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1005974877
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1981731940
Short name T421
Test name
Test status
Simulation time 164996886737 ps
CPU time 422.07 seconds
Started May 30 03:14:49 PM PDT 24
Finished May 30 03:21:53 PM PDT 24
Peak memory 201768 kb
Host smart-1f57fe3d-d769-4bb7-b02d-c6e321d5a035
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981731940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1981731940
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.922491873
Short name T155
Test name
Test status
Simulation time 599504547949 ps
CPU time 193.64 seconds
Started May 30 03:14:50 PM PDT 24
Finished May 30 03:18:05 PM PDT 24
Peak memory 201832 kb
Host smart-68ca3659-93e9-4417-8682-fce19cd81159
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922491873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.922491873
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1700962946
Short name T521
Test name
Test status
Simulation time 602511060462 ps
CPU time 140.17 seconds
Started May 30 03:14:47 PM PDT 24
Finished May 30 03:17:10 PM PDT 24
Peak memory 201824 kb
Host smart-dc689b63-fdb6-45c7-9798-5c4abdfaa249
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700962946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1700962946
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3696674369
Short name T629
Test name
Test status
Simulation time 103776854493 ps
CPU time 382.18 seconds
Started May 30 03:14:49 PM PDT 24
Finished May 30 03:21:13 PM PDT 24
Peak memory 202124 kb
Host smart-cf0ac487-c78f-4b87-8258-ba449bf38ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696674369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3696674369
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.907484581
Short name T524
Test name
Test status
Simulation time 38816853000 ps
CPU time 48.09 seconds
Started May 30 03:14:48 PM PDT 24
Finished May 30 03:15:38 PM PDT 24
Peak memory 201612 kb
Host smart-cb78d874-f1a3-4d76-8b2c-7abdb6e090d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907484581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.907484581
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.887049615
Short name T726
Test name
Test status
Simulation time 3098682954 ps
CPU time 2.52 seconds
Started May 30 03:14:48 PM PDT 24
Finished May 30 03:14:53 PM PDT 24
Peak memory 201624 kb
Host smart-76f4d277-5f49-48bd-9801-f654820ba239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887049615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.887049615
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3579271510
Short name T557
Test name
Test status
Simulation time 5942421810 ps
CPU time 7.28 seconds
Started May 30 03:14:45 PM PDT 24
Finished May 30 03:14:54 PM PDT 24
Peak memory 201652 kb
Host smart-839e489f-1c5f-4e5c-8073-a826d0fba1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579271510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3579271510
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.104861109
Short name T681
Test name
Test status
Simulation time 527907652989 ps
CPU time 230.8 seconds
Started May 30 03:14:46 PM PDT 24
Finished May 30 03:18:39 PM PDT 24
Peak memory 210436 kb
Host smart-90e0b816-e735-44af-8ebf-64b3ffea8495
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104861109 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.104861109
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2891727683
Short name T344
Test name
Test status
Simulation time 320455658 ps
CPU time 1.4 seconds
Started May 30 03:15:01 PM PDT 24
Finished May 30 03:15:04 PM PDT 24
Peak memory 201452 kb
Host smart-d6aaf3bc-9dd9-4c1a-96c1-7019264cdeb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891727683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2891727683
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.445321625
Short name T270
Test name
Test status
Simulation time 500970419838 ps
CPU time 100.01 seconds
Started May 30 03:15:05 PM PDT 24
Finished May 30 03:16:46 PM PDT 24
Peak memory 201828 kb
Host smart-c0681fab-012c-420e-b2e7-aac85a864b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445321625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.445321625
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2833992985
Short name T696
Test name
Test status
Simulation time 317607780032 ps
CPU time 356.22 seconds
Started May 30 03:15:06 PM PDT 24
Finished May 30 03:21:04 PM PDT 24
Peak memory 201792 kb
Host smart-058805e1-923d-4c61-b3ae-c64667242079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833992985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2833992985
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3536928906
Short name T706
Test name
Test status
Simulation time 488192688478 ps
CPU time 91.44 seconds
Started May 30 03:15:06 PM PDT 24
Finished May 30 03:16:38 PM PDT 24
Peak memory 201776 kb
Host smart-ce0f6d6e-5e0d-4957-9c22-40fcb37e087c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536928906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3536928906
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.648180263
Short name T130
Test name
Test status
Simulation time 164263254622 ps
CPU time 74.4 seconds
Started May 30 03:15:01 PM PDT 24
Finished May 30 03:16:17 PM PDT 24
Peak memory 201876 kb
Host smart-7a2616cb-1d40-4881-b9db-ebcfe6394d74
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=648180263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.648180263
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1700396011
Short name T680
Test name
Test status
Simulation time 354115738287 ps
CPU time 169.25 seconds
Started May 30 03:15:00 PM PDT 24
Finished May 30 03:17:50 PM PDT 24
Peak memory 201896 kb
Host smart-07be6874-16f5-475f-b499-e325743bb423
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700396011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1700396011
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3409682096
Short name T662
Test name
Test status
Simulation time 197044804108 ps
CPU time 291.84 seconds
Started May 30 03:15:00 PM PDT 24
Finished May 30 03:19:53 PM PDT 24
Peak memory 201804 kb
Host smart-07712314-dbc4-4ef5-8485-0001da4c6bda
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409682096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3409682096
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.2112933282
Short name T468
Test name
Test status
Simulation time 125034012245 ps
CPU time 553.57 seconds
Started May 30 03:15:02 PM PDT 24
Finished May 30 03:24:17 PM PDT 24
Peak memory 202072 kb
Host smart-3dc017fa-125b-4303-ae6e-5997d86b2797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112933282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2112933282
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.286402372
Short name T553
Test name
Test status
Simulation time 37630707635 ps
CPU time 46.28 seconds
Started May 30 03:15:05 PM PDT 24
Finished May 30 03:15:53 PM PDT 24
Peak memory 201640 kb
Host smart-ec07894a-ddc8-4290-9ce3-0436e3544ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286402372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.286402372
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3888460014
Short name T500
Test name
Test status
Simulation time 3371546986 ps
CPU time 9.15 seconds
Started May 30 03:15:00 PM PDT 24
Finished May 30 03:15:10 PM PDT 24
Peak memory 201636 kb
Host smart-c33f348c-f949-4616-9d0d-2a2d147d6b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888460014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3888460014
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.4013644061
Short name T717
Test name
Test status
Simulation time 5915246737 ps
CPU time 7.37 seconds
Started May 30 03:14:48 PM PDT 24
Finished May 30 03:14:57 PM PDT 24
Peak memory 201632 kb
Host smart-c4006280-670a-49ea-becb-5df38801fdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013644061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.4013644061
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.24793945
Short name T533
Test name
Test status
Simulation time 170634200383 ps
CPU time 279.46 seconds
Started May 30 03:15:06 PM PDT 24
Finished May 30 03:19:46 PM PDT 24
Peak memory 201816 kb
Host smart-f15f65a6-8621-4bd9-a6b0-d87aef5092fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24793945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.24793945
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1880004985
Short name T185
Test name
Test status
Simulation time 87084725929 ps
CPU time 256.42 seconds
Started May 30 03:15:01 PM PDT 24
Finished May 30 03:19:19 PM PDT 24
Peak memory 218628 kb
Host smart-12f2fe2f-c9cd-40d9-8500-8e8ce1ee1f06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880004985 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1880004985
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2208934952
Short name T350
Test name
Test status
Simulation time 466619895 ps
CPU time 1.73 seconds
Started May 30 03:14:59 PM PDT 24
Finished May 30 03:15:02 PM PDT 24
Peak memory 201488 kb
Host smart-a8900f08-b9cf-4fdf-b459-e23de56dae58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208934952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2208934952
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.157615437
Short name T762
Test name
Test status
Simulation time 330270350149 ps
CPU time 313.45 seconds
Started May 30 03:15:01 PM PDT 24
Finished May 30 03:20:16 PM PDT 24
Peak memory 201892 kb
Host smart-474b8158-f5d2-4321-9d35-56d400a98a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157615437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.157615437
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2169491581
Short name T720
Test name
Test status
Simulation time 330347616465 ps
CPU time 382.27 seconds
Started May 30 03:15:00 PM PDT 24
Finished May 30 03:21:24 PM PDT 24
Peak memory 201752 kb
Host smart-7d6bdcc6-28e9-4108-b077-318603356d40
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169491581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2169491581
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.740873425
Short name T161
Test name
Test status
Simulation time 491639332058 ps
CPU time 149.01 seconds
Started May 30 03:15:06 PM PDT 24
Finished May 30 03:17:36 PM PDT 24
Peak memory 201848 kb
Host smart-4c1f5226-2da4-4e23-a367-de910dfff47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740873425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.740873425
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.186962319
Short name T663
Test name
Test status
Simulation time 493753360060 ps
CPU time 246.32 seconds
Started May 30 03:15:01 PM PDT 24
Finished May 30 03:19:09 PM PDT 24
Peak memory 201884 kb
Host smart-4561171b-342f-4fad-85ec-32bb20ffd7c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=186962319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.186962319
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2254146180
Short name T78
Test name
Test status
Simulation time 388308714173 ps
CPU time 214.5 seconds
Started May 30 03:15:00 PM PDT 24
Finished May 30 03:18:36 PM PDT 24
Peak memory 201848 kb
Host smart-793f0394-1685-4efb-bd9f-556e06691229
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254146180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2254146180
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.645231184
Short name T390
Test name
Test status
Simulation time 607341126846 ps
CPU time 436.98 seconds
Started May 30 03:15:02 PM PDT 24
Finished May 30 03:22:21 PM PDT 24
Peak memory 201776 kb
Host smart-3e12536f-22b3-494f-907e-b5bf7a1fae40
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645231184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.645231184
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.636286529
Short name T429
Test name
Test status
Simulation time 72771273004 ps
CPU time 381.19 seconds
Started May 30 03:15:02 PM PDT 24
Finished May 30 03:21:25 PM PDT 24
Peak memory 202108 kb
Host smart-0b7564f7-652c-4dcf-ac49-c9d5e403f75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636286529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.636286529
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1873069271
Short name T616
Test name
Test status
Simulation time 27873734941 ps
CPU time 32.91 seconds
Started May 30 03:15:01 PM PDT 24
Finished May 30 03:15:35 PM PDT 24
Peak memory 201640 kb
Host smart-1b2ece0d-9a81-446e-afda-6cd7f1f48c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873069271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1873069271
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.467807
Short name T584
Test name
Test status
Simulation time 3070441380 ps
CPU time 2.38 seconds
Started May 30 03:14:59 PM PDT 24
Finished May 30 03:15:03 PM PDT 24
Peak memory 201660 kb
Host smart-223306cf-eef9-4e81-bacc-d56d73873afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.467807
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3695204542
Short name T693
Test name
Test status
Simulation time 6082423182 ps
CPU time 4.46 seconds
Started May 30 03:15:06 PM PDT 24
Finished May 30 03:15:12 PM PDT 24
Peak memory 201620 kb
Host smart-e470f95b-9536-47d1-8883-ecfb2bf19adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695204542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3695204542
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3104926473
Short name T715
Test name
Test status
Simulation time 305002669472 ps
CPU time 1015.84 seconds
Started May 30 03:15:03 PM PDT 24
Finished May 30 03:32:00 PM PDT 24
Peak memory 202132 kb
Host smart-e6a1beed-fb27-4dc9-9718-2905f33035fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104926473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3104926473
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.312763394
Short name T32
Test name
Test status
Simulation time 88087862978 ps
CPU time 139.39 seconds
Started May 30 03:15:05 PM PDT 24
Finished May 30 03:17:26 PM PDT 24
Peak memory 210464 kb
Host smart-ac2f3636-8a5a-44ca-b335-bd97d7a7320a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312763394 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.312763394
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3764089052
Short name T518
Test name
Test status
Simulation time 517023850 ps
CPU time 1.77 seconds
Started May 30 03:15:12 PM PDT 24
Finished May 30 03:15:15 PM PDT 24
Peak memory 201452 kb
Host smart-126813aa-6385-495c-b788-f4b68b5ca47f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764089052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3764089052
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1621404389
Short name T261
Test name
Test status
Simulation time 178968857567 ps
CPU time 433.44 seconds
Started May 30 03:15:11 PM PDT 24
Finished May 30 03:22:26 PM PDT 24
Peak memory 201860 kb
Host smart-5a19ba0e-e502-40f2-be2d-cb8a9b6d799c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621404389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1621404389
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3579847599
Short name T311
Test name
Test status
Simulation time 347082974007 ps
CPU time 199.62 seconds
Started May 30 03:15:11 PM PDT 24
Finished May 30 03:18:32 PM PDT 24
Peak memory 201820 kb
Host smart-59d55933-edf6-4eaa-80c4-61c4634db8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579847599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3579847599
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.651244956
Short name T206
Test name
Test status
Simulation time 161874518298 ps
CPU time 398.63 seconds
Started May 30 03:15:02 PM PDT 24
Finished May 30 03:21:43 PM PDT 24
Peak memory 201804 kb
Host smart-a584d23f-c1d5-492e-84d8-65a42a8b0cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651244956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.651244956
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.4178429214
Short name T686
Test name
Test status
Simulation time 162019722556 ps
CPU time 107.52 seconds
Started May 30 03:15:03 PM PDT 24
Finished May 30 03:16:52 PM PDT 24
Peak memory 201788 kb
Host smart-58c714ff-d91d-475c-a9fd-03e0e2a53294
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178429214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.4178429214
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1491033706
Short name T200
Test name
Test status
Simulation time 502599942820 ps
CPU time 288.39 seconds
Started May 30 03:15:07 PM PDT 24
Finished May 30 03:19:57 PM PDT 24
Peak memory 201832 kb
Host smart-c6647270-72b6-4963-9a44-ec67279d5367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491033706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1491033706
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.937641696
Short name T495
Test name
Test status
Simulation time 495305707934 ps
CPU time 298.11 seconds
Started May 30 03:15:00 PM PDT 24
Finished May 30 03:19:59 PM PDT 24
Peak memory 201756 kb
Host smart-0beb5a4a-8e99-4cc1-a229-f08e98259639
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=937641696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.937641696
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3456754233
Short name T612
Test name
Test status
Simulation time 526341998315 ps
CPU time 1280.46 seconds
Started May 30 03:15:01 PM PDT 24
Finished May 30 03:36:23 PM PDT 24
Peak memory 201820 kb
Host smart-d7caeb63-1352-4444-83c4-d7c24815a379
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456754233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3456754233
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.4086371405
Short name T347
Test name
Test status
Simulation time 400420629484 ps
CPU time 889.35 seconds
Started May 30 03:15:05 PM PDT 24
Finished May 30 03:29:56 PM PDT 24
Peak memory 201824 kb
Host smart-a9879767-1c1e-4dec-b8c9-59edaaab0ab9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086371405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.4086371405
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2055316582
Short name T678
Test name
Test status
Simulation time 113710625373 ps
CPU time 396.02 seconds
Started May 30 03:15:11 PM PDT 24
Finished May 30 03:21:49 PM PDT 24
Peak memory 202100 kb
Host smart-6b2abf60-35c7-4f92-98b6-856b61823fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055316582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2055316582
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1268184947
Short name T530
Test name
Test status
Simulation time 28408093104 ps
CPU time 33.73 seconds
Started May 30 03:15:12 PM PDT 24
Finished May 30 03:15:47 PM PDT 24
Peak memory 201636 kb
Host smart-98053c53-0318-43b4-9b1d-50756436b8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268184947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1268184947
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.166589229
Short name T740
Test name
Test status
Simulation time 3955146095 ps
CPU time 9.31 seconds
Started May 30 03:15:15 PM PDT 24
Finished May 30 03:15:26 PM PDT 24
Peak memory 200604 kb
Host smart-d976abc8-dd89-4430-a62d-c2123ccc2483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166589229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.166589229
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3167857366
Short name T465
Test name
Test status
Simulation time 5961524087 ps
CPU time 14.97 seconds
Started May 30 03:15:01 PM PDT 24
Finished May 30 03:15:17 PM PDT 24
Peak memory 201648 kb
Host smart-a1a05d00-a5ab-4b12-a89e-944e750a339e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167857366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3167857366
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.487563004
Short name T307
Test name
Test status
Simulation time 175098933833 ps
CPU time 121.68 seconds
Started May 30 03:15:11 PM PDT 24
Finished May 30 03:17:14 PM PDT 24
Peak memory 201784 kb
Host smart-01b1b3ff-47cd-4ce8-8346-03851aaf9bec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487563004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.487563004
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3556895640
Short name T180
Test name
Test status
Simulation time 37118874865 ps
CPU time 114.92 seconds
Started May 30 03:15:15 PM PDT 24
Finished May 30 03:17:11 PM PDT 24
Peak memory 209136 kb
Host smart-43869e89-7105-4218-8ad3-d9b3aa749400
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556895640 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3556895640
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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