Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7251	1			T1	47		T4	20		T5	13
testmodes[AdcCtrlTestmodeNormal]	5676	1			T1	39		T2	1		T3	1
testmodes[AdcCtrlTestmodeLowpower]	5808	1			T1	34		T2	2		T5	11
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3960	1			T1	17		T4	19		T5	10
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1775	1			T1	14		T5	2		T10	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1413	1			T1	16		T5	1		T28	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1812	1			T1	18		T5	2		T10	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2100	1			T1	14		T5	5		T10	6
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1419	1			T1	7		T2	1		T5	5
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1370	1			T1	11		T5	1		T38	18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1457	1			T1	11		T5	5		T27	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2729	1			T1	11		T2	1		T5	4