Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27054

1

T1

120

T2

50

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23479

1

T1

120

T2

25

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3575

1

T2

25

T3

1

T5

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20980

1

T1

120

T2

25

T3

1

auto[1]

6074

1

T2

25

T6

20

T8

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22998

1

T1

120

T2

27

T3

1

auto[1]

4056

1

T2

23

T5

2

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	46	1			T149	10		T210	1		T211	1
values[1]	778	1			T13	6		T212	7		T213	16
values[2]	828	1			T27	11		T100	2		T36	14
values[3]	855	1			T2	24		T7	14		T11	13
values[4]	707	1			T11	10		T29	4		T163	6
values[5]	2839	1			T2	25		T6	20		T14	1
values[6]	655	1			T130	19		T48	15		T42	16
values[7]	691	1			T2	1		T37	10		T132	8
values[8]	710	1			T3	1		T5	7		T11	9
values[9]	1187	1			T8	15		T12	26		T13	6
minimum	17758	1			T1	120		T4	20		T5	32

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1047	1			T13	6		T100	1		T212	7
values[1]	819	1			T11	13		T27	11		T100	1
values[2]	664	1			T2	24		T7	14		T11	10
values[3]	3088	1			T6	20		T14	1		T83	9
values[4]	574	1			T2	25		T29	14		T130	4
values[5]	728	1			T48	15		T42	31		T214	12
values[6]	580	1			T2	1		T37	10		T130	15
values[7]	760	1			T5	7		T11	9		T13	6
values[8]	754	1			T3	1		T8	15		T12	29
values[9]	275	1			T37	13		T215	21		T214	5
minimum	17765	1			T1	120		T4	20		T5	32

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

4263

1

T2

24

T5

1

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T212	7		T131	1		T31	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T13	1		T100	1		T33	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T11	1		T27	8		T100	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T36	24		T37	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	1		T216	11		T217	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	12		T11	1		T141	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1606	1			T6	20		T14	1		T83	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T28	2		T48	14		T80	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	14		T29	12		T148	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T130	1		T125	1		T142	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T48	9		T42	19		T218	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T214	1		T163	13		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T130	1		T132	1		T133	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	1		T37	10		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	1		T13	1		T36	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	5		T59	1		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T12	3		T134	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	1		T8	15		T12	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T37	13		T215	10		T214	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T148	8		T179	1		T219	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17646	1			T1	120		T4	20		T5	32
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T31	2		T126	12		T149	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	5		T33	12		T220	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T11	12		T27	3		T48	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T141	1		T126	16		T140	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	13		T15	1		T221	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	12		T11	9		T141	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	976	1			T83	8		T98	21		T99	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T48	11		T80	1		T16	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T2	11		T29	2		T148	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T130	3		T125	7		T142	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T48	6		T42	12		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T214	11		T163	11		T135	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T130	14		T132	7		T178	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T175	9		T222	2		T223	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T11	8		T13	5		T29	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	2		T32	4		T163	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T140	11		T136	8		T224	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	13		T132	9		T80	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T215	11		T214	4		T142	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T148	3		T179	11		T219	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T28	1		T29	2		T59	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T149	1		T211	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T210	1		T225	19		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T212	7		T31	5		T127	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T13	1		T213	16		T33	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T27	8		T100	1		T48	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T100	1		T36	14		T217	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T7	1		T11	1		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T2	12		T36	10		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T29	2		T163	6		T137	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T11	1		T16	1		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1559	1			T2	14		T6	20		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T28	2		T80	8		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T130	1		T48	9		T42	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T130	1		T16	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T132	1		T42	11		T227	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	1		T37	10		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T11	1		T12	3		T36	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	1		T5	5		T80	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	393	1			T13	1		T37	13		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T8	15		T12	13		T59	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17645	1			T1	120		T4	20		T5	32
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T149	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T225	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T31	2		T226	2		T228	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T13	5		T33	12		T220	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T27	3		T48	12		T31	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T226	12		T229	13		T182	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	13		T11	12		T215	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	12		T48	11		T141	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T29	2		T221	12		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	9		T16	1		T226	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	941	1			T2	11		T83	8		T98	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T80	1		T125	7		T142	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T130	14		T48	6		T42	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T130	3		T135	15		T230	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T132	7		T42	4		T178	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T214	11		T163	11		T175	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	8		T29	9		T148	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T5	2		T80	1		T32	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T13	5		T130	12		T215	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	13		T132	9		T138	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T29	2		T59	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T212	1		T131	1		T31	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T13	6		T100	1		T33	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T11	13		T27	7		T100	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T36	2		T37	1		T141	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	14		T216	1		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	13		T11	10		T141	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T6	2		T14	1		T83	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T28	2		T48	12		T80	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T2	12		T29	3		T148	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T130	4		T125	8		T142	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T48	7		T42	14		T218	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T214	12		T163	12		T135	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T130	15		T132	8		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	1		T37	1		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T11	9		T13	6		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	6		T59	1		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	1		T134	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	1		T8	1		T12	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T37	1		T215	12		T214	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T148	4		T179	12		T219	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17765	1			T1	120		T4	20		T5	32
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T212	6		T31	1		T127	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T33	7		T188	15		T231	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T27	4		T48	15		T215	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T36	22		T213	15		T217	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T216	10		T217	3		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	11		T141	12		T232	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T6	18		T34	25		T35	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T48	13		T80	7		T233	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T2	13		T29	11		T148	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T142	13		T234	16		T235	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T48	8		T42	17		T218	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T163	12		T236	6		T237	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T133	9		T227	10		T238	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T37	9		T217	5		T175	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T36	12		T29	7		T148	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T5	1		T163	6		T140	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	2		T140	11		T237	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T8	14		T12	12		T138	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T37	12		T215	9		T142	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T148	7		T219	1		T239	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T149	10		T211	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T210	1		T225	16		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T212	1		T31	6		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	6		T213	1		T33	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T27	7		T100	1		T48	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T100	1		T36	1		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T7	14		T11	13		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T2	13		T36	1		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T29	3		T163	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T11	10		T16	2		T226	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T2	12		T6	2		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T28	2		T80	2		T125	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T130	15		T48	7		T42	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T130	4		T16	1		T135	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T132	8		T42	5		T227	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T2	1		T37	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T11	9		T12	1		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T3	1		T5	6		T80	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T13	6		T37	1		T130	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T8	1		T12	14		T59	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17758	1			T1	120		T4	20		T5	32
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T225	18		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T212	6		T31	1		T127	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T213	15		T33	7		T188	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T27	4		T48	15		T218	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T36	13		T217	7		T127	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T215	17		T30	11		T216	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T2	11		T36	9		T48	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T29	1		T163	5		T137	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T233	12		T240	7		T234	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T2	13		T6	18		T34	25
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T80	7		T142	13		T234	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T48	8		T42	7		T218	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T236	6		T241	10		T242	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T42	10		T227	10		T165	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T37	9		T217	5		T163	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	2		T36	12		T29	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	1		T163	6		T140	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T37	12		T215	9		T140	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T8	14		T12	12		T138	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

auto[0]

4263

1

T2

24

T5

1

T6

18

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27054

1

T1

120

T2

50

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23416

1

T1

120

T2

24

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3638

1

T2

26

T3

1

T5

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20722

1

T1

120

T2

1

T3

1

auto[1]

6332

1

T2

49

T6

20

T8

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22998

1

T1

120

T2

27

T3

1

auto[1]

4056

1

T2

23

T5

2

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	20	1			T243	20		-	-		-	-
values[0]	31	1			T244	1		T245	8		T246	1
values[1]	753	1			T100	1		T29	14		T130	19
values[2]	724	1			T11	9		T12	3		T13	6
values[3]	783	1			T37	13		T48	25		T133	10
values[4]	712	1			T27	11		T100	1		T130	13
values[5]	814	1			T2	25		T11	13		T13	6
values[6]	739	1			T5	7		T7	14		T36	10
values[7]	592	1			T28	2		T37	10		T59	1
values[8]	571	1			T3	1		T8	15		T12	26
values[9]	3557	1			T2	25		T6	20		T11	10
minimum	17758	1			T1	120		T4	20		T5	32

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	922	1			T13	6		T100	1		T130	19
values[1]	847	1			T11	9		T12	3		T29	14
values[2]	592	1			T37	13		T48	25		T133	10
values[3]	904	1			T11	13		T13	6		T27	11
values[4]	758	1			T2	25		T5	7		T215	35
values[5]	638	1			T7	14		T36	10		T29	23
values[6]	2946	1			T6	20		T14	1		T83	9
values[7]	679	1			T3	1		T8	15		T12	26
values[8]	741	1			T2	25		T36	13		T48	28
values[9]	268	1			T11	10		T37	1		T138	22
minimum	17759	1			T1	120		T4	20		T5	32

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

4263

1

T2

24

T5

1

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	1		T130	1		T31	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T100	1		T130	1		T30	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T215	10		T131	1		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	1		T12	3		T29	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T37	13		T48	14		T133	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T214	1		T163	13		T140	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T11	1		T13	1		T27	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T100	1		T130	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T215	18		T212	7		T214	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	14		T5	5		T15	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	1		T36	10		T29	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T125	1		T217	8		T163	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1650	1			T6	20		T14	1		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T28	2		T37	10		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T8	15		T36	14		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	1		T12	13		T48	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	12		T216	11		T214	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T2	1		T36	13		T48	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T11	1		T37	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T138	9		T143	1		T247	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17645	1			T1	120		T4	20		T5	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T244	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	5		T130	3		T31	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T130	14		T30	13		T126	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T215	11		T128	3		T129	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	8		T29	2		T80	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T48	11		T125	10		T148	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T214	4		T163	11		T140	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	12		T13	5		T27	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T130	12		T136	9		T179	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T215	17		T214	6		T140	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T2	11		T5	2		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	13		T29	11		T132	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T125	7		T163	7		T142	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T83	8		T98	21		T99	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T132	7		T126	12		T142	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T141	1		T248	2		T222	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	13		T48	6		T141	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	12		T214	11		T129	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T48	12		T148	10		T142	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T11	9		T226	12		T249	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T138	13		T247	10		T250	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T29	2		T59	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T243	20		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T245	5		T251	5		T252	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T244	1		T246	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T130	1		T31	2		T217	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T100	1		T29	12		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T13	1		T215	10		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	1		T12	3		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T37	13		T48	14		T133	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T163	13		T140	12		T218	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T27	8		T80	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T100	1		T130	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T11	1		T13	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	14		T15	8		T129	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	1		T36	10		T29	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T5	5		T125	1		T217	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T59	1		T31	5		T217	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T28	2		T37	10		T42	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T8	15		T36	14		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T3	1		T12	13		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1767	1			T2	12		T6	20		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T2	1		T36	13		T48	25
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17645	1			T1	120		T4	20		T5	32
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T245	3		T251	1		T252	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T130	3		T31	1		T149	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T29	2		T130	14		T80	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T13	5		T215	11		T32	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T11	8		T42	4		T214	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T48	11		T148	3		T19	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T163	11		T140	11		T149	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T27	3		T80	1		T125	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T130	12		T179	9		T253	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T11	12		T13	5		T132	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	11		T15	2		T129	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	13		T29	11		T214	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	2		T125	7		T163	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T31	2		T33	12		T128	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T42	8		T182	12		T230	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T141	1		T254	3		T228	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	13		T132	7		T126	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1115	1			T2	12		T11	9		T83	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T48	18		T141	14		T138	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T29	2		T59	1