Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27054

1

T1

120

T2

50

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23467

1

T1

120

T3

1

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3587

1

T2

50

T7

14

T8

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21041

1

T1

120

T2

1

T4

20

auto[1]

6013

1

T2

49

T3

1

T5

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22998

1

T1

120

T2

27

T3

1

auto[1]

4056

1

T2

23

T5

2

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	267	1			T3	1		T140	23		T244	1
values[0]	40	1			T22	13		T311	26		T286	1
values[1]	693	1			T13	6		T29	4		T48	15
values[2]	3008	1			T2	24		T5	7		T6	20
values[3]	601	1			T8	15		T11	10		T100	1
values[4]	961	1			T215	21		T138	22		T134	1
values[5]	831	1			T7	14		T12	26		T27	11
values[6]	704	1			T2	1		T13	6		T36	14
values[7]	661	1			T11	22		T37	10		T42	16
values[8]	626	1			T2	25		T132	11		T42	15
values[9]	904	1			T12	3		T28	2		T37	14
minimum	17758	1			T1	120		T4	20		T5	32

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	521	1			T5	7		T36	13		T29	14
values[1]	2991	1			T2	24		T6	20		T14	1
values[2]	803	1			T8	15		T11	10		T100	1
values[3]	909	1			T215	21		T138	22		T134	1
values[4]	791	1			T7	14		T12	26		T13	6
values[5]	733	1			T2	1		T36	14		T130	28
values[6]	531	1			T11	22		T37	10		T42	15
values[7]	654	1			T2	25		T28	2		T132	11
values[8]	898	1			T3	1		T12	3		T37	14
values[9]	151	1			T140	23		T187	3		T248	6
minimum	18072	1			T1	120		T4	20		T5	32

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

4263

1

T2

24

T5

1

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T5	5		T36	13		T29	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T48	9		T141	1		T216	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1671	1			T6	20		T14	1		T83	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	12		T130	1		T31	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	1		T100	1		T36	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T8	15		T148	11		T140	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T134	1		T214	1		T217	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T215	10		T138	9		T212	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T13	1		T27	8		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	1		T12	13		T125	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T36	14		T130	1		T42	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	1		T130	1		T48	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	1		T42	11		T133	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T11	1		T37	10		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T232	15		T214	1		T163	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T2	14		T28	2		T132	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T3	1		T12	3		T37	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T132	1		T48	14		T218	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T312	4		T170	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T140	12		T187	3		T248	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17767	1			T1	120		T4	20		T5	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T13	1		T80	1		T141	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T5	2		T29	2		T16	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T48	6		T141	1		T148	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	985	1			T83	8		T98	21		T99	27
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T2	12		T130	3		T31	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	9		T140	12		T254	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T148	10		T140	8		T128	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T214	6		T149	10		T135	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T215	11		T138	13		T30	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	5		T27	3		T80	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	13		T12	13		T125	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T130	12		T42	8		T32	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T130	14		T48	12		T215	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T11	8		T42	4		T181	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T11	12		T142	11		T16	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T232	5		T214	4		T163	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T2	11		T132	9		T163	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T15	1		T228	1		T272	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T132	7		T48	11		T128	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T312	7		T170	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T140	11		T248	5		T255	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T28	1		T29	4		T59	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T13	5		T80	1		T141	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T3	1		T244	1		T272	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T140	12		T253	12		T313	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T22	7		T311	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T286	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T29	2		T217	8		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	1		T48	9		T80	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1685	1			T5	5		T6	20		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	12		T130	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T11	1		T100	1		T36	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T8	15		T148	11		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T134	1		T214	1		T217	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T215	10		T138	9		T212	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T27	8		T100	1		T59	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T7	1		T12	13		T125	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	1		T36	14		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	1		T130	1		T48	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	1		T42	8		T133	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	1		T37	10		T215	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T42	11		T232	15		T163	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T2	14		T132	2		T163	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T12	3		T37	14		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T28	2		T132	1		T48	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17645	1			T1	120		T4	20		T5	32
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T272	2		T222	12		T312	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T140	11		T253	14		T313	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T22	6		T311	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T29	2		T126	12		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	5		T48	6		T80	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T5	2		T83	8		T98	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T2	12		T130	3		T141	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	9		T29	9		T140	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T148	10		T128	3		T226	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T214	6		T149	10		T135	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T215	11		T138	13		T30	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T27	3		T80	1		T214	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	13		T12	13		T125	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	5		T130	12		T148	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T130	14		T48	12		T126	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T11	8		T42	8		T33	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	12		T215	17		T16	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T42	4		T232	5		T163	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T2	11		T132	9		T163	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T214	4		T15	1		T228	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T132	7		T48	11		T128	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T29	2		T59	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T5	6		T36	1		T29	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T48	7		T141	2		T216	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T6	2		T14	1		T83	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	13		T130	4		T31	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T11	10		T100	1		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T8	1		T148	11		T140	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T134	1		T214	7		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T215	12		T138	14		T212	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T13	6		T27	7		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T7	14		T12	14		T125	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T36	1		T130	13		T42	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T2	1		T130	15		T48	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T11	9		T42	5		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	13		T37	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T232	6		T214	5		T163	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T2	12		T28	2		T132	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T3	1		T12	1		T37	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T132	8		T48	12		T218	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T312	8		T170	4		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T140	12		T187	1		T248	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17891	1			T1	120		T4	20		T5	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T13	6		T80	2		T141	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T5	1		T36	12		T29	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T48	8		T216	10		T148	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T6	18		T34	25		T35	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T2	11		T31	1		T163	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T36	9		T217	3		T140	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T8	14		T148	10		T140	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T217	5		T218	5		T240	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T215	9		T138	8		T212	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T27	4		T80	7		T148	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	12		T238	5		T223	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T36	13		T42	7		T33	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T48	15		T215	17		T213	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	10		T133	9		T181	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T37	9		T127	12		T142	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T232	14		T163	6		T142	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T2	13		T163	12		T240	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	2		T37	12		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T48	13		T218	6		T127	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T312	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T140	11		T187	2		T255	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T29	1		T217	7		T15	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T141	12		T17	1		T301	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T3	1		T244	1		T272	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T140	12		T253	15		T313	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T22	7		T311	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T286	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T29	3		T217	1		T126	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T13	6		T48	7		T80	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T5	6		T6	2		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	13		T130	4		T141	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T11	10		T100	1		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T8	1		T148	11		T128	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T134	1		T214	7		T217	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T215	12		T138	14		T212	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T27	7		T100	1		T59	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T7	14		T12	14		T125	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	6		T36	1		T130	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T2	1		T130	15		T48	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T11	9		T42	9		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	13		T37	1		T215	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T42	5		T232	6		T163	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T2	12		T132	11		T163	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	1		T37	2		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T28	2		T132	8		T48	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17758	1			T1	120		T4	20		T5	32
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T272	4		T222	13		T312	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T140	11		T253	11		T313	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T22	6		T311	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T29	1		T217	7		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T48	8		T141	12		T148	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1335	1			T5	1		T6	18		T34	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	11		T216	10		T31	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T36	9		T29	7		T140	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T8	14		T148	10		T175	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T217	8		T229	13		T240	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T215	9		T138	8		T212	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T27	4		T80	7		T218	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	12		T228	3		T267	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T36	13		T148	7		T181	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T48	15		T213	15		T238	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T42	7		T133	9		T33	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T37	9		T215	17		T127	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T42	10		T232	14		T163	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T2	13		T163	12		T142	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	2		T37	12		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T48	13		T218	6		T127	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

auto[0]

4263

1

T2

24

T5

1

T6

18