Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27054

1

T1

120

T2

50

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23496

1

T1

120

T2

49

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3558

1

T2

1

T3

1

T5

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20838

1

T1

120

T2

1

T3

1

auto[1]

6216

1

T2

49

T6

20

T8

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22998

1

T1

120

T2

27

T3

1

auto[1]

4056

1

T2

23

T5

2

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	338	1			T37	1		T138	22		T131	1
values[0]	21	1			T136	12		T245	8		T314	1
values[1]	750	1			T100	1		T130	19		T30	28
values[2]	739	1			T11	9		T12	3		T13	6
values[3]	757	1			T37	13		T48	25		T133	10
values[4]	797	1			T27	11		T100	1		T130	13
values[5]	748	1			T2	25		T5	7		T11	13
values[6]	746	1			T7	14		T36	10		T29	4
values[7]	596	1			T28	2		T37	10		T29	19
values[8]	575	1			T3	1		T8	15		T36	14
values[9]	3229	1			T2	25		T6	20		T11	10
minimum	17758	1			T1	120		T4	20		T5	32

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	612	1			T13	6		T130	4		T215	21
values[1]	888	1			T11	9		T12	3		T29	14
values[2]	604	1			T37	13		T48	25		T133	10
values[3]	847	1			T11	13		T27	11		T100	1
values[4]	782	1			T2	25		T5	7		T13	6
values[5]	685	1			T7	14		T36	10		T29	23
values[6]	2930	1			T6	20		T8	15		T14	1
values[7]	629	1			T3	1		T36	14		T48	15
values[8]	827	1			T2	25		T12	26		T36	13
values[9]	222	1			T11	10		T37	1		T138	22
minimum	18028	1			T1	120		T4	20		T5	32

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

4263

1

T2

24

T5

1

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T13	1		T130	1		T215	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T30	15		T126	1		T181	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T217	4		T218	6		T129	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T11	1		T12	3		T29	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T37	13		T48	14		T133	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T214	1		T163	13		T140	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T27	8		T80	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	1		T100	1		T213	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T2	14		T13	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	5		T15	8		T129	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	1		T36	10		T29	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T125	1		T217	8		T163	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1651	1			T6	20		T8	15		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T28	2		T37	10		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T36	14		T271	1		T137	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	1		T48	9		T141	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T2	12		T131	1		T216	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T2	1		T12	13		T36	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T11	1		T131	1		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T37	1		T138	9		T218	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17729	1			T1	120		T4	20		T5	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T100	1		T130	1		T136	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T13	5		T130	3		T215	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T30	13		T126	16		T181	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T129	11		T233	10		T181	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T11	8		T29	2		T80	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T48	11		T125	10		T148	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T214	4		T163	11		T140	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T27	3		T80	1		T232	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	12		T136	9		T179	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	11		T13	5		T130	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T5	2		T15	2		T129	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	13		T29	11		T132	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T125	7		T163	7		T142	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1030	1			T83	8		T98	21		T99	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T132	7		T42	8		T126	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T248	2		T222	8		T307	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T48	6		T141	15		T226	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T2	12		T214	11		T129	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	13		T48	12		T148	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T11	9		T226	12		T249	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T138	13		T247	10		T250	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T28	1		T29	2		T59	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T130	14		T136	11		T94	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T131	1		T216	11		T214	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T37	1		T138	9		T218	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T245	5		T314	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T136	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T130	1		T31	2		T32	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T100	1		T130	1		T30	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	1		T215	10		T217	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	1		T12	3		T29	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T37	13		T48	14		T133	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T214	1		T163	13		T140	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T27	8		T130	1		T80	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T100	1		T213	16		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T2	14		T13	1		T215	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	5		T11	1		T15	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	1		T36	10		T29	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T125	1		T217	8		T163	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T29	10		T59	1		T217	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T28	2		T37	10		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T8	15		T36	14		T271	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	1		T132	1		T48	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1703	1			T2	12		T6	20		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T2	1		T12	13		T36	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17645	1			T1	120		T4	20		T5	32
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T214	11		T226	12		T256	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T138	13		T276	7		T152	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T245	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T136	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T130	3		T31	1		T32	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T130	14		T30	13		T126	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T13	5		T215	11		T129	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T11	8		T29	2		T80	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T48	11		T148	3		T19	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T214	4		T163	11		T140	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T27	3		T130	12		T80	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T179	9		T255	13		T253	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T2	11		T13	5		T215	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T5	2		T11	12		T15	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	13		T29	2		T132	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T125	7		T163	7		T142	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T29	9		T33	12		T128	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T182	12		T223	10		T315	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T254	3		T248	2		T151	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T132	7		T48	6		T141	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T2	12		T11	9		T83	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T12	13		T48	12		T141	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T29	2		T59	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	6		T130	4		T215	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T30	17		T126	17		T181	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T217	1		T218	1		T129	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T11	9		T12	1		T29	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T37	1		T48	12		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T214	5		T163	12		T140	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T27	7		T80	2		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	13		T100	1		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T2	12		T13	6		T130	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	6		T15	8		T129	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T7	14		T36	1		T29	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T125	8		T217	1		T163	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T6	2		T8	1		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T28	2		T37	1		T132	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T36	1		T271	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	1		T48	7		T141	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T2	13		T131	1		T216	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T2	1		T12	14		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T11	10		T131	1		T226	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T37	1		T138	14		T218	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17854	1			T1	120		T4	20		T5	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T100	1		T130	15		T136	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T215	9		T127	5		T236	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T30	11		T181	2		T231	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T217	3		T218	5		T129	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	2		T29	11		T80	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T37	12		T48	13		T133	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T163	12		T140	11		T127	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T27	4		T232	14		T187	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T213	15		T165	16		T255	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T2	13		T215	17		T212	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	1		T15	2		T129	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T36	9		T29	8		T31	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T217	7		T163	6		T142	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T6	18		T8	14		T34	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T37	9		T42	7		T142	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T36	13		T137	5		T231	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T48	8		T141	12		T227	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T2	11		T216	10		T163	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	12		T36	12		T48	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T249	11		T256	11		T316	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T138	8		T218	6		T250	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T288	11		T291	10		T281	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T188	15		T317	14		T318	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T131	1		T216	1		T214	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T37	1		T138	14		T218	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T245	4		T314	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T136	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T130	4		T31	3		T32	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T100	1		T130	15		T30	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	6		T215	12		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T11	9		T12	1		T29	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T37	1		T48	12		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T214	5		T163	12		T140	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T27	7		T130	13		T80	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T100	1		T213	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T2	12		T13	6		T215	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T5	6		T11	13		T15	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T7	14		T36	1		T29	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T125	8		T217	1		T163	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T29	12		T59	1		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T28	2		T37	1		T182	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T8	1		T36	1		T271	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	1		T132	8		T48	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1412	1			T2	13		T6	2		T11	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T2	1		T12	14		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17758	1			T1	120		T4	20		T5	32
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T216	10		T256	11		T316	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T138	8		T218	6		T237	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T245	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T127	5		T236	6		T228	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T30	11		T188	15		T231	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T215	9		T217	3		T129	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	2		T29	11		T80	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T37	12		T48	13		T133	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T163	12		T140	11		T127	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T27	4		T187	2		T221	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T213	15		T165	16		T255	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T2	13		T215	17		T232	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	1		T15	2		T129	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T36	9		T29	1		T212	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T217	7		T163	6		T142	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T29	7		T217	5		T33	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T37	9		T223	21		T315	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	14		T36	13		T254	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T48	8		T42	7		T142	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T2	11		T6	18		T34	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T12	12		T36	12		T48	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

auto[0]

4263

1

T2

24

T5

1

T6

18