Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27054

1

T1

120

T2

50

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23485

1

T1

120

T3

1

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3569

1

T2

50

T7

14

T8

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21086

1

T1

120

T2

1

T4

20

auto[1]

5968

1

T2

49

T3

1

T5

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22998

1

T1

120

T2

27

T3

1

auto[1]

4056

1

T2

23

T5

2

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	35	1			T272	7		T243	13		T317	15
values[0]	82	1			T141	27		T263	12		T319	4
values[1]	624	1			T13	6		T29	4		T48	15
values[2]	3013	1			T2	24		T5	7		T6	20
values[3]	655	1			T8	15		T11	10		T100	1
values[4]	923	1			T215	21		T138	22		T134	1
values[5]	824	1			T12	26		T27	11		T100	1
values[6]	784	1			T7	14		T11	9		T13	6
values[7]	589	1			T2	1		T11	13		T37	10
values[8]	643	1			T2	25		T132	19		T42	15
values[9]	1124	1			T3	1		T12	3		T28	2
minimum	17758	1			T1	120		T4	20		T5	32

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	889	1			T5	7		T36	13		T29	18
values[1]	2902	1			T2	24		T6	20		T14	1
values[2]	773	1			T8	15		T11	10		T100	1
values[3]	934	1			T215	21		T138	22		T134	1
values[4]	780	1			T7	14		T12	26		T13	6
values[5]	738	1			T11	13		T36	14		T130	28
values[6]	555	1			T2	1		T11	9		T37	10
values[7]	573	1			T2	25		T28	2		T132	10
values[8]	847	1			T3	1		T12	3		T37	1
values[9]	245	1			T37	13		T140	23		T127	6
minimum	17818	1			T1	120		T4	20		T5	32

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

4263

1

T2

24

T5

1

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	5		T36	13		T29	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T48	9		T80	1		T141	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1642	1			T6	20		T14	1		T83	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	12		T130	1		T31	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T11	1		T100	1		T36	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T8	15		T148	11		T140	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T214	1		T149	1		T268	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T215	10		T138	9		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T13	1		T27	8		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	1		T12	13		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T36	14		T130	1		T32	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T11	1		T130	1		T48	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	1		T42	19		T133	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T2	1		T37	10		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T134	1		T232	15		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	14		T28	2		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T3	1		T12	3		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T132	1		T48	14		T218	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T37	13		T312	17		T320	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T140	12		T127	6		T255	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17675	1			T1	120		T4	20		T5	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T13	1		T321	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T5	2		T29	4		T126	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T48	6		T80	1		T141	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	976	1			T83	8		T98	21		T99	27
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T2	12		T130	3		T31	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T11	9		T31	2		T140	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T148	10		T140	8		T128	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T214	6		T149	10		T135	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T215	11		T138	13		T125	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	5		T27	3		T80	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T7	13		T12	13		T125	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T130	12		T32	4		T33	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	12		T130	14		T48	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	8		T42	12		T233	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T142	11		T16	9		T188	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T232	5		T214	4		T163	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T2	11		T132	9		T163	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T15	1		T228	1		T272	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T132	7		T48	11		T128	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T312	17		T320	7		T170	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T140	11		T255	13		T322	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T28	1		T29	2		T59	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T13	5		T321	7		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T272	5		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T243	13		T317	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T319	1		T323	10		T22	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T141	13		T263	10		T324	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T29	2		T217	8		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	1		T48	9		T80	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1667	1			T5	5		T6	20		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T2	12		T130	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T11	1		T100	1		T36	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T8	15		T148	11		T163	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T217	10		T149	1		T268	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T215	10		T138	9		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T27	8		T100	1		T59	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	13		T125	1		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	1		T13	1		T36	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T7	1		T48	16		T215	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T42	8		T33	14		T237	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	1		T11	1		T37	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T42	11		T232	15		T163	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	14		T132	3		T163	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T3	1		T12	3		T37	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T28	2		T48	14		T140	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17645	1			T1	120		T4	20		T5	32
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T272	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T319	3		T22	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T141	14		T263	2		T324	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T29	2		T126	12		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T13	5		T48	6		T80	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T5	2		T83	8		T98	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	12		T130	3		T141	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	9		T29	9		T31	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T148	10		T128	3		T226	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T149	10		T135	15		T229	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T215	11		T138	13		T125	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T27	3		T80	1		T214	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	13		T125	10		T136	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	8		T13	5		T130	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T7	13		T48	12		T215	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T42	8		T33	12		T181	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	12		T130	14		T16	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T42	4		T232	5		T163	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T2	11		T132	16		T163	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T214	4		T15	1		T228	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T48	11		T140	11		T128	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T29	2		T59	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T5	6		T36	1		T29	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T48	7		T80	2		T141	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T6	2		T14	1		T83	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T2	13		T130	4		T31	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	10		T100	1		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T8	1		T148	11		T140	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T214	7		T149	11		T268	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T215	12		T138	14		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T13	6		T27	7		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T7	14		T12	14		T125	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T36	1		T130	13		T32	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T11	13		T130	15		T48	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	9		T42	14		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T2	1		T37	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T134	1		T232	6		T214	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	12		T28	2		T132	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	1		T12	1		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T132	8		T48	12		T218	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T37	1		T312	19		T320	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T140	12		T127	1		T255	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17775	1			T1	120		T4	20		T5	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T13	6		T321	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	1		T36	12		T29	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T48	8		T141	12		T216	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T6	18		T34	25		T35	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T2	11		T163	5		T137	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T36	9		T31	1		T217	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T8	14		T148	10		T140	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T240	1		T234	2		T152	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T215	9		T138	8		T212	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T27	4		T80	7		T148	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	12		T238	5		T305	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T36	13		T33	7		T237	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T48	15		T215	17		T213	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T42	17		T133	9		T233	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T37	9		T142	13		T16	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T232	14		T163	6		T142	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T2	13		T163	12		T240	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	2		T15	1		T228	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T48	13		T218	6		T187	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T37	12		T312	15		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T140	11		T127	5		T255	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T264	4		T323	9		T311	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T321	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T272	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T243	1		T317	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T319	4		T323	1		T22	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T141	15		T263	3		T324	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T29	3		T217	1		T126	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	6		T48	7		T80	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T5	6		T6	2		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	13		T130	4		T141	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T11	10		T100	1		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T8	1		T148	11		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T217	2		T149	11		T268	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T215	12		T138	14		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T27	7		T100	1		T59	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T12	14		T125	11		T136	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	9		T13	6		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T7	14		T48	13		T215	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T42	9		T33	19		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	1		T11	13		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T42	5		T232	6		T163	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T2	12		T132	19		T163	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T3	1		T12	1		T37	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T28	2		T48	12		T140	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17758	1			T1	120		T4	20		T5	32
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T272	4		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T243	12		T317	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T323	9		T22	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T141	12		T263	9		T324	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T29	1		T217	7		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T48	8		T148	15		T142	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T5	1		T6	18		T34	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	11		T216	10		T137	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T36	9		T29	7		T31	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T8	14		T148	10		T163	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T217	8		T229	13		T240	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T215	9		T138	8		T212	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T27	4		T80	7		T218	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	12		T228	3		T267	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T36	13		T133	9		T148	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T48	15		T215	17		T213	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T42	7		T33	7		T237	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T37	9		T127	12		T16	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T42	10		T232	14		T163	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T2	13		T163	12		T142	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	2		T37	12		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T48	13		T140	11		T218	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

auto[0]

4263

1

T2

24

T5

1

T6

18