Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27054

1

T1

120

T2

50

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23833

1

T1

120

T2

24

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3221

1

T2

26

T7

14

T11

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20734

1

T1

116

T2

1

T3

1

auto[1]

6320

1

T1

4

T2

49

T5

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22998

1

T1

120

T2

27

T3

1

auto[1]

4056

1

T2

23

T5

2

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	690	1			T1	4		T3	1		T5	8
values[0]	44	1			T48	28		T21	8		T167	8
values[1]	624	1			T5	7		T13	6		T37	1
values[2]	3210	1			T6	20		T11	9		T14	1
values[3]	673	1			T132	10		T42	15		T148	21
values[4]	729	1			T2	24		T100	1		T42	1
values[5]	460	1			T8	15		T29	4		T59	1
values[6]	727	1			T13	6		T27	11		T100	1
values[7]	837	1			T2	25		T12	26		T36	23
values[8]	686	1			T2	1		T28	2		T37	10
values[9]	1060	1			T11	23		T12	3		T80	9
minimum	17314	1			T1	116		T4	20		T5	24

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	767	1			T13	6		T37	1		T29	19
values[1]	3071	1			T6	20		T11	9		T14	1
values[2]	625	1			T148	21		T142	25		T237	11
values[3]	674	1			T2	24		T100	1		T130	4
values[4]	620	1			T8	15		T27	11		T100	1
values[5]	749	1			T13	6		T36	23		T37	13
values[6]	802	1			T2	26		T12	26		T29	14
values[7]	698	1			T11	10		T28	2		T37	10
values[8]	850	1			T3	1		T80	9		T141	2
values[9]	238	1			T7	14		T11	13		T12	3
minimum	17960	1			T1	120		T4	20		T5	39

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

4263

1

T2

24

T5

1

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	1		T130	1		T141	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T37	1		T29	10		T215	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1704	1			T6	20		T14	1		T83	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T11	1		T132	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T136	1		T175	9		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T148	11		T142	14		T237	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T2	12		T126	1		T163	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T100	1		T130	1		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	15		T27	8		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T29	2		T59	1		T138	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T13	1		T36	10		T213	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T36	13		T37	13		T48	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T48	14		T133	10		T134	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	15		T12	13		T29	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	1		T28	2		T37	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T132	1		T30	15		T31	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	1		T141	1		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T80	8		T126	1		T140	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T12	3		T163	13		T218	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T7	1		T11	1		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17699	1			T1	120		T4	20		T5	37
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T80	1		T215	10		T125	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T13	5		T130	14		T141	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T29	9		T215	17		T135	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1031	1			T83	8		T98	21		T99	27
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	8		T132	9		T140	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T136	9		T175	9		T235	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T148	10		T142	11		T254	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	12		T163	7		T140	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T130	3		T126	12		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T27	3		T148	3		T178	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T29	2		T138	13		T148	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	5		T129	12		T226	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T48	6		T226	2		T280	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T48	11		T214	11		T229	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T2	11		T12	13		T29	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	9		T33	12		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T132	7		T30	13		T31	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T141	1		T125	7		T214	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T80	1		T126	16		T140	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T163	11		T235	8		T282	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T7	13		T11	12		T136	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T28	1		T29	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T80	1		T215	11		T125	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	552	1			T1	4		T3	1		T5	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T7	1		T140	10		T165	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T48	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T21	5		T167	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	5		T13	1		T232	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T37	1		T29	10		T80	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1735	1			T6	20		T14	1		T83	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	1		T134	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T42	11		T136	1		T270	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T132	1		T148	11		T142	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T2	12		T126	1		T140	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T100	1		T42	1		T217	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	15		T212	7		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T29	2		T59	1		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	1		T27	8		T100	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T48	9		T148	16		T271	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T36	10		T48	14		T133	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T2	14		T12	13		T36	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T28	2		T37	10		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	1		T29	12		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T11	1		T12	3		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T11	1		T80	8		T31	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17201	1			T1	116		T4	20		T5	24
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T125	7		T163	11		T235	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T7	13		T140	8		T325	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T48	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T21	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T5	2		T13	5		T232	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T29	9		T80	1		T215	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1116	1			T83	8		T98	21		T99	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T11	8		T140	12		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T42	4		T136	9		T175	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T132	9		T148	10		T142	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	12		T140	11		T149	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T126	12		T15	1		T142	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T148	3		T163	7		T178	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T29	2		T130	3		T138	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T13	5		T27	3		T129	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T48	6		T148	14		T226	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T48	11		T214	11		T188	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T2	11		T12	13		T42	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T33	12		T15	1		T229	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T29	2		T132	7		T30	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T11	9		T141	1		T214	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T11	12		T80	1		T31	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T29	2		T59	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T13	6		T130	15		T141	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T37	1		T29	12		T215	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T6	2		T14	1		T83	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	9		T132	10		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T136	10		T175	10		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T148	11		T142	12		T237	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T2	13		T126	1		T163	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T100	1		T130	4		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T8	1		T27	7		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T29	3		T59	1		T138	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T13	6		T36	1		T213	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T36	1		T37	1		T48	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T48	12		T133	1		T134	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	13		T12	14		T29	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T11	10		T28	2		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T132	8		T30	17		T31	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	1		T141	2		T125	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T80	2		T126	17		T140	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T12	1		T163	12		T218	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T7	14		T11	13		T136	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17804	1			T1	120		T4	20		T5	38
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T80	2		T215	12		T125	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T141	12		T232	14		T129	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T29	7		T215	17		T276	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T6	18		T34	25		T35	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T140	7		T127	5		T137	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T175	8		T235	9		T263	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T148	10		T142	13		T237	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T2	11		T163	6		T140	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T217	5		T15	1		T142	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T8	14		T27	4		T212	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T29	1		T138	8		T148	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T36	9		T213	15		T129	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T36	12		T37	12		T48	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T48	13		T133	9		T218	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	13		T12	12		T29	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T37	9		T33	7		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T30	11		T31	1		T128	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T217	10		T142	2		T237	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T80	7		T140	9		T127	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T12	2		T163	12		T218	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T233	11		T165	7		T326	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T5	1		T48	15		T216	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T215	9		T327	10		T21	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	528	1			T1	4		T3	1		T5	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T7	14		T140	9		T165	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T48	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T21	5		T167	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	6		T13	6		T232	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T37	1		T29	12		T80	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1464	1			T6	2		T14	1		T83	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	9		T134	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T42	5		T136	10		T270	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T132	10		T148	11		T142	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T2	13		T126	1		T140	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T100	1		T42	1		T217	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T8	1		T212	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T29	3		T59	1		T130	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	6		T27	7		T100	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T48	7		T148	15		T271	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T36	1		T48	12		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	12		T12	14		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T28	2		T37	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T2	1		T29	3		T132	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T11	10		T12	1		T141	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T11	13		T80	2		T31	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17314	1			T1	116		T4	20		T5	24
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T217	3		T163	12		T218	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T140	9		T165	7		T328	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T48	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T21	3		T167	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	1		T232	14		T216	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T29	7		T215	26		T288	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T6	18		T34	25		T35	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T140	7		T127	5		T137	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T42	10		T175	8		T263	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T148	10		T142	13		T237	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T2	11		T140	11		T129	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T217	5		T15	1		T142	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T8	14		T212	6		T148	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T29	1		T138	8		T240	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T27	4		T129	14		T227	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T48	8		T148	15		T137	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T36	9		T48	13		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	13		T12	12		T36	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T37	9		T33	7		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T29	11		T30	11		T128	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	2		T217	7		T142	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T80	7		T31	1		T127	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

auto[0]

4263

1

T2

24

T5

1

T6

18