Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27054

1

T1

120

T2

50

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23237

1

T1

120

T4

20

T5

32

auto[ADC_CTRL_FILTER_COND_OUT]

3817

1

T2

50

T3

1

T5

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21013

1

T1

120

T2

24

T3

1

auto[1]

6041

1

T2

26

T5

7

T6

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22998

1

T1

120

T2

27

T3

1

auto[1]

4056

1

T2

23

T5

2

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	290	1			T2	26		T27	11		T80	9
values[0]	80	1			T28	2		T215	21		T127	13
values[1]	631	1			T11	13		T36	13		T29	4
values[2]	553	1			T7	14		T100	1		T36	10
values[3]	646	1			T11	9		T12	3		T13	6
values[4]	920	1			T36	14		T29	14		T130	15
values[5]	3147	1			T6	20		T8	15		T14	1
values[6]	630	1			T2	24		T130	4		T48	15
values[7]	797	1			T3	1		T11	10		T12	26
values[8]	721	1			T48	25		T141	27		T133	10
values[9]	881	1			T5	7		T13	6		T100	1
minimum	17758	1			T1	120		T4	20		T5	32

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	503	1			T100	1		T36	13		T29	4
values[1]	563	1			T7	14		T36	10		T215	35
values[2]	882	1			T12	3		T13	6		T36	14
values[3]	2999	1			T6	20		T11	9		T14	1
values[4]	868	1			T2	24		T8	15		T37	10
values[5]	594	1			T130	4		T132	1		T48	15
values[6]	1051	1			T3	1		T11	10		T12	26
values[7]	485	1			T48	25		T133	10		T31	3
values[8]	878	1			T2	26		T5	7		T13	6
values[9]	129	1			T163	24		T228	13		T284	33
minimum	18102	1			T1	120		T4	20		T5	32

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

4263

1

T2

24

T5

1

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T59	1		T132	1		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T100	1		T36	13		T29	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	1		T36	10		T30	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T215	18		T217	8		T32	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T13	1		T48	16		T148	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	3		T36	14		T29	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1633	1			T6	20		T14	1		T83	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T11	1		T130	1		T212	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T29	10		T138	9		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T2	12		T8	15		T37	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T42	11		T126	1		T15	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T130	1		T132	1		T48	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T11	1		T140	8		T218	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T3	1		T12	13		T141	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T48	14		T31	2		T148	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T133	10		T217	6		T221	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T27	8		T130	1		T80	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T2	15		T5	5		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T228	4		T284	15		T329	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T163	13		T293	1		T294	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17703	1			T1	120		T4	20		T5	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T28	2		T141	1		T220	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T132	9		T214	4		T181	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T29	2		T31	2		T149	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T7	13		T30	13		T263	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T215	17		T32	4		T230	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	5		T48	12		T148	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T29	2		T125	10		T33	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	939	1			T83	8		T98	21		T99	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	8		T130	14		T140	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T29	9		T138	13		T178	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	12		T125	7		T233	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T42	4		T126	12		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T130	3		T48	6		T42	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T11	9		T140	12		T16	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	13		T141	14		T232	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T48	11		T31	1		T148	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T221	12		T179	9		T234	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T27	3		T130	12		T80	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	11		T5	2		T13	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T228	9		T284	18		T329	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T163	11		T293	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	12		T28	1		T29	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T141	1		T220	11		T280	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T27	8		T163	7		T228	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T2	15		T80	8		T16	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T215	10		T127	13		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T28	2		T285	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	1		T59	1		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T36	13		T29	2		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	1		T36	10		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T100	1		T217	8		T32	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	1		T30	15		T218	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	1		T12	3		T215	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T48	16		T148	11		T15	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T36	14		T29	12		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1662	1			T6	20		T14	1		T83	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T8	15		T37	10		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T42	11		T126	1		T268	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	12		T130	1		T48	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	1		T218	7		T15	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T3	1		T12	13		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T48	14		T31	2		T148	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T141	13		T133	10		T232	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T130	1		T80	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	5		T13	1		T100	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17645	1			T1	120		T4	20		T5	32
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T27	3		T163	7		T228	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T2	11		T80	1		T228	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T215	11		T135	9		T248	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T285	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T11	12		T132	7		T148	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T29	2		T141	1		T31	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T7	13		T132	9		T214	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T32	4		T16	1		T136	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	5		T30	13		T254	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	8		T215	17		T125	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T48	12		T148	10		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T29	2		T130	14		T140	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1014	1			T83	8		T98	21		T99	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T125	7		T226	2		T233	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T42	4		T126	12		T268	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	12		T130	3		T48	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	9		T15	1		T16	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	13		T214	6		T126	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T48	11		T31	1		T148	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T141	14		T232	5		T226	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T130	12		T80	1		T214	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	2		T13	5		T163	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T29	2		T59	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T59	1		T132	10		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T100	1		T36	1		T29	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	14		T36	1		T30	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T215	18		T217	1		T32	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T13	6		T48	13		T148	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T12	1		T36	1		T29	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T6	2		T14	1		T83	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T11	9		T130	15		T212	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T29	12		T138	14		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T2	13		T8	1		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T42	5		T126	13		T15	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T130	4		T132	1		T48	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T11	10		T140	13		T218	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T3	1		T12	14		T141	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T48	12		T31	3		T148	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T133	1		T217	1		T221	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T27	7		T130	13		T80	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T2	13		T5	6		T13	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T228	10		T284	19		T329	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T163	12		T293	9		T294	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17825	1			T1	120		T4	20		T5	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T28	2		T141	2		T220	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T181	6		T282	13		T298	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T36	12		T29	1		T31	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T36	9		T30	11		T213	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T215	17		T217	7		T221	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T48	15		T148	10		T218	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	2		T36	13		T29	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T6	18		T34	25		T35	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T212	6		T140	11		T129	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T29	7		T138	8		T229	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T2	11		T8	14		T37	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T42	10		T15	1		T165	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T48	8		T42	7		T129	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T140	7		T218	6		T16	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T12	12		T141	12		T232	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T48	13		T148	15		T142	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T133	9		T217	5		T221	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T27	4		T163	6		T140	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	13		T5	1		T37	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T228	3		T284	14		T329	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T163	12		T294	3		T297	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T215	9		T148	7		T127	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T220	8		T280	13		T253	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T27	7		T163	8		T228	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T2	13		T80	2		T16	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T215	12		T127	1		T135	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T28	2		T285	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T11	13		T59	1		T132	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T36	1		T29	3		T141	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T7	14		T36	1		T132	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T100	1		T217	1		T32	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	6		T30	17		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	9		T12	1		T215	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T48	13		T148	11		T15	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T36	1		T29	3		T130	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T6	2		T14	1		T83	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T8	1		T37	1		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T42	5		T126	13		T268	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	13		T130	4		T48	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T11	10		T218	1		T15	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	1		T12	14		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T48	12		T31	3		T148	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T141	15		T133	1		T232	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T130	13		T80	2		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	6		T13	6		T100	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17758	1			T1	120		T4	20		T5	32
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T27	4		T163	6		T228	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T2	13		T80	7		T188	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T215	9		T127	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T285	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T148	7		T181	6		T298	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T36	12		T29	1		T31	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T36	9		T213	15		T163	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T217	7		T221	2		T240	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T30	11		T218	5		T254	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	2		T215	17		T165	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T48	15		T148	10		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T36	13		T29	11		T212	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T6	18		T34	25		T35	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T8	14		T37	9		T233	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T42	10		T165	7		T238	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	11		T48	8		T42	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T218	6		T15	1		T16	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	12		T217	3		T129	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T48	13		T148	15		T140	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T141	12		T133	9		T232	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T140	9		T237	10		T188	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T5	1		T37	12		T216	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

auto[0]

4263

1

T2

24

T5

1

T6

18