Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27054

1

T1

120

T2

50

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23472

1

T1

120

T2

25

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3582

1

T2

25

T3

1

T5

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20946

1

T1

120

T2

25

T3

1

auto[1]

6108

1

T2

25

T6

20

T8

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22998

1

T1

120

T2

27

T3

1

auto[1]

4056

1

T2

23

T5

2

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	297	1			T132	10		T215	21		T138	22
values[0]	86	1			T149	10		T330	7		T210	1
values[1]	769	1			T13	6		T212	7		T31	7
values[2]	833	1			T27	11		T100	2		T36	14
values[3]	755	1			T2	24		T7	14		T11	13
values[4]	756	1			T11	10		T29	4		T48	25
values[5]	2861	1			T2	25		T6	20		T14	1
values[6]	608	1			T130	19		T48	15		T42	16
values[7]	723	1			T2	1		T37	10		T132	8
values[8]	716	1			T5	7		T11	9		T36	13
values[9]	892	1			T3	1		T8	15		T12	29
minimum	17758	1			T1	120		T4	20		T5	32

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	914	1			T100	1		T212	7		T131	1
values[1]	790	1			T11	13		T27	11		T100	1
values[2]	672	1			T2	24		T7	14		T11	10
values[3]	3108	1			T6	20		T14	1		T83	9
values[4]	502	1			T2	25		T29	14		T130	4
values[5]	710	1			T130	15		T48	15		T42	16
values[6]	647	1			T2	1		T37	10		T132	8
values[7]	712	1			T5	7		T11	9		T36	13
values[8]	824	1			T3	1		T8	15		T12	29
values[9]	217	1			T215	21		T214	5		T176	1
minimum	17958	1			T1	120		T4	20		T5	32

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

4263

1

T2

24

T5

1

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T212	7		T131	1		T31	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T100	1		T213	16		T188	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T11	1		T27	8		T100	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T36	24		T37	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	1		T216	11		T217	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	12		T11	1		T141	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1605	1			T6	20		T14	1		T83	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T28	2		T48	14		T80	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T2	14		T29	12		T148	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T130	1		T125	1		T142	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T130	1		T48	9		T42	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T214	1		T163	13		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T132	1		T42	11		T133	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	1		T37	10		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T11	1		T36	13		T29	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T5	5		T59	1		T80	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T12	3		T13	1		T37	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T3	1		T8	15		T12	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T215	10		T214	1		T176	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T179	1		T331	11		T239	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17673	1			T1	120		T4	20		T5	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T13	1		T33	14		T220	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T31	2		T126	12		T228	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T299	9		T151	6		T332	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T11	12		T27	3		T48	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T141	1		T126	16		T140	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	13		T15	1		T129	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	12		T11	9		T141	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	961	1			T83	8		T98	21		T99	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T48	11		T80	1		T135	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T2	11		T29	2		T148	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T130	3		T125	7		T142	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T130	14		T48	6		T42	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T214	11		T163	11		T135	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T132	7		T42	4		T178	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T222	2		T282	14		T223	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T11	8		T29	9		T130	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T5	2		T80	1		T32	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	5		T140	11		T142	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	13		T132	9		T138	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T215	11		T214	4		T287	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T179	11		T331	14		T239	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T28	1		T29	2		T59	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T13	5		T33	12		T220	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T215	10		T131	1		T224	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T132	1		T138	9		T142	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T149	1		T330	1		T333	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T210	1		T225	19		T265	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T212	7		T31	5		T127	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T13	1		T33	14		T188	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T27	8		T100	1		T48	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T100	1		T36	14		T213	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	1		T11	1		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	12		T36	10		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T29	2		T163	6		T129	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T11	1		T48	14		T16	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1547	1			T2	14		T6	20		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T28	2		T80	8		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T130	1		T48	9		T42	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T130	1		T16	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T132	1		T42	11		T133	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T2	1		T37	10		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T11	1		T36	13		T29	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	5		T80	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T12	3		T13	1		T37	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	1		T8	15		T12	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17645	1			T1	120		T4	20		T5	32
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T215	11		T224	4		T334	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T132	9		T138	13		T142	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T149	9		T330	6		T333	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T225	15		T265	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T31	2		T226	2		T228	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	5		T33	12		T220	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T27	3		T48	12		T31	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T226	12		T229	13		T181	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	13		T11	12		T215	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	12		T141	15		T232	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T29	2		T129	10		T221	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	9		T48	11		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	910	1			T2	11		T83	8		T98	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T80	1		T125	7		T142	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T130	14		T48	6		T42	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T130	3		T135	15		T230	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T132	7		T42	4		T178	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T214	11		T163	11		T175	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T11	8		T29	9		T148	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T5	2		T80	1		T32	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T13	5		T130	12		T214	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	13		T148	3		T282	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T29	2		T59	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T212	1		T131	1		T31	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T100	1		T213	1		T188	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T11	13		T27	7		T100	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T36	2		T37	1		T141	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	14		T216	1		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	13		T11	10		T141	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T6	2		T14	1		T83	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T28	2		T48	12		T80	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T2	12		T29	3		T148	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T130	4		T125	8		T142	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T130	15		T48	7		T42	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T214	12		T163	12		T135	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T132	8		T42	5		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	1		T37	1		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T11	9		T36	1		T29	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T5	6		T59	1		T80	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	1		T13	6		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	1		T8	1		T12	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T215	12		T214	5		T176	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T179	12		T331	15		T239	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17799	1			T1	120		T4	20		T5	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T13	6		T33	19		T220	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T212	6		T31	1		T127	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T213	15		T188	15		T231	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T27	4		T48	15		T215	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T36	22		T217	7		T140	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T216	10		T217	3		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	11		T141	12		T232	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T6	18		T34	25		T35	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T48	13		T80	7		T233	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T2	13		T29	11		T148	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T142	13		T234	16		T235	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T48	8		T42	7		T218	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T163	12		T236	6		T137	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T42	10		T133	9		T227	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T37	9		T217	5		T237	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T36	12		T29	7		T148	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T5	1		T163	6		T140	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	2		T37	12		T140	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T8	14		T12	12		T138	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T215	9		T287	14		T335	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T331	10		T239	1		T297	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T310	12		T333	6		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T33	7		T220	8		T292	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T215	12		T131	1		T224	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T132	10		T138	14		T142	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T149	10		T330	7		T333	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T210	1		T225	16		T265	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T212	1		T31	6		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	6		T33	19		T188	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T27	7		T100	1		T48	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T100	1		T36	1		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T7	14		T11	13		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	13		T36	1		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T29	3		T163	1		T129	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T11	10		T48	12		T16	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T2	12		T6	2		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T28	2		T80	2		T125	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T130	15		T48	7		T42	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T130	4		T16	1		T135	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T132	8		T42	5		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T2	1		T37	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T11	9		T36	1		T29	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T5	6		T80	2		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T12	1		T13	6		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	1		T8	1		T12	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17758	1			T1	120		T4	20		T5	32
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T215	9		T224	9		T165	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T138	8		T142	2		T240	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T333	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T225	18		T265	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T212	6		T31	1		T127	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T33	7		T188	15		T231	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T27	4		T48	15		T218	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T36	13		T213	15		T217	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T215	17		T30	11		T216	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	11		T36	9		T141	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T29	1		T163	5		T129	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T48	13		T233	12		T240	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T2	13		T6	18		T34	25
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T80	7		T142	13		T234	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T48	8		T42	7		T218	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T236	6		T241	10		T242	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T42	10		T133	9		T227	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T37	9		T217	5		T163	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T36	12		T29	7		T148	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	1		T163	6		T140	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T12	2		T37	12		T140	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T8	14		T12	12		T148	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

auto[0]

4263

1

T2

24

T5

1

T6

18