Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T13	6		T130	4		T31	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T100	1		T130	15		T30	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T215	12		T131	1		T128	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T11	9		T12	1		T29	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T37	1		T48	12		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T214	5		T163	12		T140	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T11	13		T13	6		T27	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T100	1		T130	13		T136	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T215	18		T212	1		T214	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	12		T5	6		T15	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	14		T36	1		T29	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T125	8		T217	1		T163	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1390	1			T6	2		T14	1		T83	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T28	2		T37	1		T132	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T8	1		T36	1		T141	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	1		T12	14		T48	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	13		T216	1		T214	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	1		T36	1		T48	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T11	10		T37	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T138	14		T143	1		T247	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17758	1			T1	120		T4	20		T5	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T244	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T217	3		T127	5		T236	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T30	11		T148	15		T188	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T215	9		T129	14		T233	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	2		T29	11		T80	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T37	12		T48	13		T133	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T163	12		T140	11		T127	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T27	4		T232	14		T213	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T165	16		T255	15		T253	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T215	17		T212	6		T140	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T2	13		T5	1		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T36	9		T29	8		T31	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T217	7		T163	6		T142	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T6	18		T34	25		T35	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T37	9		T142	2		T165	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	14		T36	13		T137	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	12		T48	8		T141	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T2	11		T216	10		T163	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T36	12		T48	15		T148	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T218	6		T249	11		T256	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T138	8		T250	18		T168	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T243	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T245	4		T251	6		T252	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T244	1		T246	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T130	4		T31	3		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T100	1		T29	3		T130	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	6		T215	12		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T11	9		T12	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T37	1		T48	12		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T163	12		T140	12		T218	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T27	7		T80	2		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T100	1		T130	13		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T11	13		T13	6		T132	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	12		T15	8		T129	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	14		T36	1		T29	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	6		T125	8		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T59	1		T31	6		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T28	2		T37	1		T42	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T8	1		T36	1		T141	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	1		T12	14		T132	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1507	1			T2	13		T6	2		T11	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	367	1			T2	1		T36	1		T48	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17758	1			T1	120		T4	20		T5	32
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T243	19		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T245	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T217	3		T127	5		T236	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T29	11		T80	7		T30	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T215	9		T129	14		T181	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	2		T42	10		T148	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T37	12		T48	13		T133	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T163	12		T140	11		T218	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T27	4		T213	15		T187	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T165	16		T257	9		T253	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T215	17		T232	14		T140	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	13		T15	2		T129	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T36	9		T29	8		T212	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	1		T217	7		T163	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T31	1		T217	5		T33	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T37	9		T42	7		T223	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T8	14		T36	13		T254	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T12	12		T142	2		T165	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T2	11		T6	18		T34	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T36	12		T48	23		T141	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

auto[0]

4263

1

T2

24

T5

1

T6

18