Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27054

1

T1

120

T2

50

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23557

1

T1

120

T2

26

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3497

1

T2

24

T7

14

T13

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21046

1

T1

120

T2

1

T4

20

auto[1]

6008

1

T2

49

T3

1

T5

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22998

1

T1

120

T2

27

T3

1

auto[1]

4056

1

T2

23

T5

2

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	11	1			T258	11		-	-		-	-
values[0]	36	1			T182	12		T248	6		T21	3
values[1]	580	1			T5	7		T130	13		T48	15
values[2]	830	1			T2	49		T37	1		T29	4
values[3]	487	1			T36	14		T48	25		T141	2
values[4]	2918	1			T6	20		T14	1		T83	9
values[5]	594	1			T100	1		T36	10		T29	14
values[6]	842	1			T3	1		T11	19		T12	3
values[7]	821	1			T8	15		T13	6		T29	19
values[8]	749	1			T7	14		T13	6		T27	11
values[9]	1428	1			T2	1		T11	13		T12	26
minimum	17758	1			T1	120		T4	20		T5	32

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	778	1			T5	7		T37	1		T130	13
values[1]	767	1			T2	49		T29	4		T130	4
values[2]	610	1			T36	14		T48	25		T141	2
values[3]	2937	1			T6	20		T14	1		T83	9
values[4]	670	1			T12	3		T36	10		T29	14
values[5]	793	1			T3	1		T8	15		T11	19
values[6]	762	1			T7	14		T13	6		T132	9
values[7]	684	1			T13	6		T27	11		T37	23
values[8]	998	1			T2	1		T12	26		T100	1
values[9]	284	1			T11	13		T42	15		T32	6
minimum	17771	1			T1	120		T4	20		T5	32

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

4263

1

T2

24

T5

1

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T5	5		T132	1		T48	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T37	1		T130	1		T215	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T2	14		T29	2		T232	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	12		T130	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T36	14		T48	14		T30	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T141	1		T129	15		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1626	1			T6	20		T14	1		T83	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T48	16		T163	13		T127	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	3		T42	8		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T36	10		T29	12		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	1		T8	15		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T138	9		T214	1		T217	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T132	1		T30	1		T148	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	1		T13	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	1		T80	1		T163	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T27	8		T37	23		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T2	1		T12	13		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T100	1		T213	16		T31	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T11	1		T32	2		T142	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T42	11		T15	3		T129	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17658	1			T1	120		T4	20		T5	32
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	2		T132	9		T48	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T130	12		T215	17		T126	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T2	11		T29	2		T232	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	12		T130	3		T136	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T48	11		T30	13		T126	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T141	1		T129	11		T136	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	983	1			T83	8		T98	21		T99	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T48	12		T163	11		T233	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T42	8		T135	15		T238	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T29	2		T259	6		T260	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	17		T29	9		T80	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T138	13		T214	11		T140	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T132	7		T148	10		T181	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T7	13		T13	5		T141	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	5		T80	1		T163	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T27	3		T125	10		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T12	13		T142	11		T228	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T31	2		T140	19		T128	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T11	12		T32	4		T142	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T42	4		T15	1		T129	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T29	2		T59	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T258	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T21	3		T261	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T182	1		T248	1		T262	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	5		T48	9		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T130	1		T215	18		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T2	14		T29	2		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	12		T37	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T36	14		T48	14		T30	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T141	1		T136	1		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1591	1			T6	20		T14	1		T83	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T163	13		T129	15		T227	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T100	1		T130	1		T216	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T36	10		T29	12		T48	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	1		T11	2		T12	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T138	9		T144	1		T165	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T8	15		T29	10		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	1		T141	13		T215	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	1		T33	14		T187	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	1		T27	8		T37	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T2	1		T11	1		T12	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	491	1			T100	1		T37	13		T42	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17645	1			T1	120		T4	20		T5	32
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T182	11		T248	5		T262	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T48	6		T214	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T130	12		T215	17		T126	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	11		T29	2		T132	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	12		T130	3		T136	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T48	11		T30	13		T126	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T141	1		T136	8		T226	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	926	1			T83	8		T98	21		T99	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T163	11		T129	11		T224	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T130	14		T31	1		T148	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T29	2		T48	12		T259	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	17		T42	8		T135	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T138	13		T238	10		T222	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T29	9		T132	7		T80	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T13	5		T141	14		T215	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T13	5		T33	12		T129	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T7	13		T27	3		T125	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T11	12		T12	13		T80	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T42	4		T31	2		T140	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T29	2		T59	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T5	6		T132	10		T48	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T37	1		T130	13		T215	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T2	12		T29	3		T232	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	13		T130	4		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T36	1		T48	12		T30	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T141	2		T129	12		T136	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T6	2		T14	1		T83	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T48	13		T163	12		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T12	1		T42	9		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T36	1		T29	3		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	1		T8	1		T11	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T138	14		T214	12		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T132	8		T30	1		T148	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	14		T13	6		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T13	6		T80	2		T163	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T27	7		T37	2		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T2	1		T12	14		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T100	1		T213	1		T31	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T11	13		T32	6		T142	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T42	5		T15	3		T129	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17759	1			T1	120		T4	20		T5	32
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	1		T48	8		T148	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T215	17		T217	5		T181	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T2	13		T29	1		T232	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T2	11		T237	8		T221	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T36	13		T48	13		T30	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T129	14		T227	10		T224	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T6	18		T34	25		T35	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T48	15		T163	12		T127	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	2		T42	7		T216	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T36	9		T29	11		T263	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T8	14		T36	12		T29	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T138	8		T217	7		T140	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T148	10		T236	6		T221	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T141	12		T215	9		T163	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T163	6		T33	7		T187	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T27	4		T37	21		T133	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T12	12		T212	6		T142	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T213	15		T31	1		T140	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T142	12		T257	7		T264	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T42	10		T15	1		T129	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T265	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T258	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T21	1		T261	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T182	12		T248	6		T262	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	6		T48	7		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T130	13		T215	18		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	12		T29	3		T132	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	13		T37	1		T130	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T36	1		T48	12		T30	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T141	2		T136	9		T226	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T6	2		T14	1		T83	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T163	12		T129	12		T227	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T100	1		T130	15		T216	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T36	1		T29	3		T48	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T3	1		T11	19		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T138	14		T144	1		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T8	1		T29	12		T132	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T13	6		T141	15		T215	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T13	6		T33	19		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	14		T27	7		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T2	1		T11	13		T12	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	423	1			T100	1		T37	1		T42	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17758	1			T1	120		T4	20		T5	32
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T258	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T21	2		T261	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T262	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	1		T48	8		T240	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T215	17		T217	5		T181	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T2	13		T29	1		T232	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T2	11		T237	8		T221	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T36	13		T48	13		T30	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T137	13		T175	8		T266	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T6	18		T34	25		T35	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T163	12		T129	14		T227	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T216	10		T148	15		T127	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T36	9		T29	11		T48	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	2		T36	12		T42	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T138	8		T165	16		T238	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	14		T29	7		T80	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T141	12		T215	9		T217	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T33	7		T187	2		T129	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T27	4		T37	9		T218	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T12	12		T212	6		T163	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	396	1			T37	12		T42	10		T133	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

auto[0]

4263

1

T2

24

T5

1

T6

18