Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27054

1

T1

120

T2

50

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23558

1

T1

120

T2

24

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3496

1

T2

26

T3

1

T11

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20631

1

T1

116

T2

25

T3

1

auto[1]

6423

1

T1

4

T2

25

T5

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22998

1

T1

120

T2

27

T3

1

auto[1]

4056

1

T2

23

T5

2

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	452	1			T1	4		T5	8		T38	2
values[0]	60	1			T48	28		T267	1		T21	8
values[1]	663	1			T5	7		T13	6		T37	1
values[2]	3086	1			T6	20		T11	9		T14	1
values[3]	749	1			T132	10		T42	15		T148	21
values[4]	682	1			T2	24		T100	1		T42	1
values[5]	480	1			T8	15		T29	4		T59	1
values[6]	722	1			T13	6		T27	11		T100	1
values[7]	821	1			T2	25		T12	26		T36	13
values[8]	701	1			T2	1		T37	10		T29	14
values[9]	1324	1			T3	1		T7	14		T11	23
minimum	17314	1			T1	116		T4	20		T5	24

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	938	1			T5	7		T13	6		T37	1
values[1]	3091	1			T6	20		T11	9		T14	1
values[2]	666	1			T217	6		T148	21		T142	47
values[3]	626	1			T2	24		T100	1		T130	4
values[4]	590	1			T8	15		T27	11		T100	1
values[5]	794	1			T13	6		T36	23		T37	13
values[6]	761	1			T2	1		T12	26		T29	14
values[7]	726	1			T2	25		T11	10		T28	2
values[8]	862	1			T3	1		T80	9		T141	2
values[9]	231	1			T7	14		T11	13		T12	3
minimum	17769	1			T1	120		T4	20		T5	32

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

4263

1

T2

24

T5

1

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	5		T13	1		T48	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T37	1		T29	10		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1739	1			T6	20		T14	1		T83	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	1		T132	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T136	1		T235	10		T263	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T217	6		T148	11		T142	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T2	12		T42	1		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T100	1		T130	1		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T8	15		T27	8		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T29	2		T138	9		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T13	1		T36	23		T213	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T37	13		T48	9		T148	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T48	14		T133	10		T134	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	1		T12	13		T29	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	1		T37	10		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T2	14		T28	2		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T141	1		T125	1		T217	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T3	1		T80	8		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T7	1		T12	3		T163	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T11	1		T236	7		T233	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17656	1			T1	120		T4	20		T5	32
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	2		T13	5		T48	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T29	9		T130	14		T80	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1072	1			T83	8		T98	21		T99	27
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T11	8		T132	9		T140	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T136	9		T235	9		T223	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T148	10		T142	20		T254	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	12		T126	12		T163	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T130	3		T15	1		T268	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T27	3		T148	3		T257	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T29	2		T138	13		T178	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	5		T129	12		T226	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T48	6		T148	14		T226	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T48	11		T31	1		T214	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	13		T29	2		T42	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	9		T214	10		T33	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	11		T132	7		T30	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T141	1		T125	7		T140	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T80	1		T126	16		T136	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T7	13		T163	11		T136	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T11	12		T233	10		T154	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T29	2		T59	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	452	1			T1	4		T5	8		T38	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T48	16		T269	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T267	1		T21	5		T166	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	5		T13	1		T232	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T37	1		T29	10		T80	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1632	1			T6	20		T14	1		T83	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	1		T130	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T42	11		T136	1		T270	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T132	1		T148	11		T142	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T2	12		T42	1		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T100	1		T217	6		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	15		T59	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T29	2		T130	1		T138	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	1		T27	8		T100	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T48	9		T148	16		T271	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T36	13		T48	14		T133	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T2	14		T12	13		T37	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T37	10		T131	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T2	1		T29	12		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T7	1		T11	1		T12	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	388	1			T3	1		T11	1		T28	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17201	1			T1	116		T4	20		T5	24
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T48	12		T269	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T21	3		T166	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	2		T13	5		T232	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T29	9		T80	1		T215	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1068	1			T83	8		T98	21		T99	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	8		T130	14		T140	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T42	4		T136	9		T221	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T132	9		T148	10		T142	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	12		T126	12		T140	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T15	1		T142	9		T228	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T163	7		T149	10		T257	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T29	2		T130	3		T138	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	5		T27	3		T148	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T48	6		T148	14		T226	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T48	11		T214	11		T188	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	11		T12	13		T42	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T31	1		T214	6		T33	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T29	2		T132	7		T30	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T7	13		T11	9		T141	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T11	12		T80	1		T31	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T29	2		T59	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T5	6		T13	6		T48	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T37	1		T29	12		T130	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1420	1			T6	2		T14	1		T83	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	9		T132	10		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T136	10		T235	10		T263	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T217	1		T148	11		T142	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T2	13		T42	1		T126	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T100	1		T130	4		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T8	1		T27	7		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T29	3		T138	14		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	6		T36	2		T213	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T37	1		T48	7		T148	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T48	12		T133	1		T134	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	1		T12	14		T29	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	10		T37	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	12		T28	2		T132	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T141	2		T125	8		T217	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T3	1		T80	2		T126	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T7	14		T12	1		T163	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T11	13		T236	1		T233	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17759	1			T1	120		T4	20		T5	32
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	1		T48	15		T141	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T29	7		T215	26		T163	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T6	18		T34	25		T35	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T140	7		T137	13		T272	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T235	9		T263	7		T223	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T217	5		T148	10		T142	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T2	11		T163	6		T140	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T15	1		T273	11		T274	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T8	14		T27	4		T212	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T29	1		T138	8		T137	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T36	21		T213	15		T187	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T37	12		T48	8		T148	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T48	13		T133	9		T218	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	12		T29	11		T42	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T37	9		T33	7		T152	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	13		T30	11		T31	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T217	10		T140	9		T127	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T80	7		T237	8		T181	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T12	2		T163	12		T218	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T236	6		T233	11		T275	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T216	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	445	1			T1	4		T5	8		T38	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T48	13		T269	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T267	1		T21	5		T166	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	6		T13	6		T232	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T37	1		T29	12		T80	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1406	1			T6	2		T14	1		T83	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	9		T130	15		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T42	5		T136	10		T270	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T132	10		T148	11		T142	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T2	13		T42	1		T126	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T100	1		T217	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T8	1		T59	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T29	3		T130	4		T138	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T13	6		T27	7		T100	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T48	7		T148	15		T271	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T36	1		T48	12		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	12		T12	14		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T37	1		T131	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	1		T29	3		T132	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T7	14		T11	10		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	403	1			T3	1		T11	13		T28	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17314	1			T1	116		T4	20		T5	24
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T165	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T48	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T21	3		T166	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	1		T232	14		T216	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T29	7		T215	26		T163	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T6	18		T34	25		T35	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T140	7		T137	13		T276	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T42	10		T221	12		T175	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T148	10		T142	13		T237	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T2	11		T140	11		T129	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T217	5		T15	1		T142	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T8	14		T163	6		T257	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T29	1		T138	8		T240	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T27	4		T36	9		T212	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T48	8		T148	15		T227	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T36	12		T48	13		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	13		T12	12		T37	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T37	9		T33	7		T229	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T29	11		T30	11		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T12	2		T217	10		T163	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T80	7		T31	1		T236	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

auto[0]

4263

1

T2

24

T5

1

T6

18