Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27054

1

T1

120

T2

50

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21005

1

T1

120

T2

26

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

6049

1

T2

24

T5

7

T6

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20845

1

T1

120

T2

50

T4

20

auto[1]

6209

1

T3

1

T5

7

T6

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22998

1

T1

120

T2

27

T3

1

auto[1]

4056

1

T2

23

T5

2

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	59	1			T132	1		T30	28		T277	2
values[0]	14	1			T278	13		T279	1		-	-
values[1]	722	1			T3	1		T13	6		T37	10
values[2]	684	1			T2	25		T27	11		T28	2
values[3]	790	1			T36	14		T29	14		T130	4
values[4]	711	1			T11	10		T37	1		T131	1
values[5]	677	1			T7	14		T11	13		T141	27
values[6]	588	1			T2	1		T5	7		T8	15
values[7]	662	1			T11	9		T130	13		T48	25
values[8]	837	1			T2	24		T12	3		T13	6
values[9]	3552	1			T6	20		T12	26		T14	1
minimum	17758	1			T1	120		T4	20		T5	32

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	814	1			T2	25		T3	1		T13	6
values[1]	3070	1			T6	20		T14	1		T83	9
values[2]	788	1			T37	1		T130	4		T48	28
values[3]	679	1			T11	23		T29	14		T134	1
values[4]	672	1			T2	1		T7	14		T141	27
values[5]	496	1			T5	7		T8	15		T11	9
values[6]	811	1			T12	3		T13	6		T130	13
values[7]	653	1			T100	1		T36	10		T59	1
values[8]	1122	1			T2	24		T12	26		T100	1
values[9]	164	1			T132	1		T133	10		T126	13
minimum	17785	1			T1	120		T4	20		T5	32

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

4263

1

T2

24

T5

1

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T2	14		T3	1		T13	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T27	8		T48	9		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T126	1		T140	12		T218	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1720	1			T6	20		T14	1		T83	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T37	1		T48	16		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T130	1		T80	1		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	1		T29	12		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T11	1		T131	1		T217	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T2	1		T7	1		T141	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T134	1		T212	7		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T139	1		T176	1		T179	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	5		T8	15		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	1		T130	1		T42	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T12	3		T48	14		T42	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T100	1		T132	1		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T36	10		T59	1		T138	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T12	13		T100	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T2	12		T37	13		T29	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T132	1		T133	10		T237	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T126	1		T127	13		T181	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17659	1			T1	120		T4	20		T5	32
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T2	11		T13	5		T232	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T27	3		T48	6		T149	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T126	16		T140	11		T136	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1069	1			T83	8		T98	21		T99	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T48	12		T148	3		T140	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T130	3		T80	1		T214	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	9		T29	2		T16	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	12		T140	8		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	13		T141	14		T31	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T149	5		T276	7		T234	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T179	11		T238	8		T152	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T5	2		T11	8		T29	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	5		T130	12		T42	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T48	11		T42	4		T129	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T132	9		T214	4		T280	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T138	13		T214	6		T226	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T12	13		T130	14		T132	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	12		T29	2		T215	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T281	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T126	12		T181	4		T247	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T28	1		T29	2		T59	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T132	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T30	15		T277	1		T87	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T279	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T278	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	1		T13	1		T37	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T215	10		T131	1		T217	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	14		T48	16		T140	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T27	8		T28	2		T36	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T29	12		T134	1		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T36	14		T130	1		T80	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	1		T37	1		T142	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T131	1		T140	10		T15	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	1		T141	13		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	1		T217	4		T128	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T2	1		T152	15		T282	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T5	5		T8	15		T29	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T130	1		T139	1		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	1		T48	14		T42	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	1		T100	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T2	12		T12	3		T59	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	405	1			T12	13		T100	1		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1754	1			T6	20		T14	1		T83	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17645	1			T1	120		T4	20		T5	32
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T30	13		T277	1		T87	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T13	5		T232	5		T224	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T215	11		T149	9		T135	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T2	11		T48	12		T140	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T27	3		T48	6		T233	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T29	2		T126	16		T148	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T130	3		T80	2		T125	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	9		T142	11		T16	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T140	8		T15	1		T129	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	13		T141	14		T31	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	12		T128	11		T149	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T152	11		T282	9		T277	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T5	2		T29	9		T182	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T130	12		T125	7		T163	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	8		T48	11		T42	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	5		T132	9		T42	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	12		T138	13		T214	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T12	13		T130	14		T132	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1086	1			T83	8		T98	21		T99	27
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T29	2		T59	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	12		T3	1		T13	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T27	7		T48	7		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T126	17		T140	12		T218	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1414	1			T6	2		T14	1		T83	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T37	1		T48	13		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T130	4		T80	2		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	10		T29	3		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	13		T131	1		T217	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	1		T7	14		T141	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T134	1		T212	1		T149	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T139	1		T176	1		T179	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	6		T8	1		T11	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T13	6		T130	13		T42	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	1		T48	12		T42	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T100	1		T132	10		T214	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T36	1		T59	1		T138	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	367	1			T12	14		T100	1		T130	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T2	13		T37	1		T29	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T132	1		T133	1		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T126	13		T127	1		T181	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17774	1			T1	120		T4	20		T5	32
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T2	13		T37	9		T232	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T27	4		T48	8		T217	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T140	11		T218	6		T188	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1375	1			T6	18		T34	25		T35	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T48	15		T148	7		T140	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T127	5		T129	9		T233	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T29	11		T16	5		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T217	3		T140	9		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T141	12		T31	1		T163	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T212	6		T137	5		T276	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T165	7		T238	5		T152	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T5	1		T8	14		T29	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T42	7		T163	6		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	2		T48	13		T42	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T280	13		T258	10		T283	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T36	9		T138	8		T218	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T12	12		T148	25		T142	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	11		T37	12		T29	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T133	9		T237	8		T281	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T127	12		T181	6		T284	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T264	2		T250	2		T285	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T132	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T30	17		T277	2		T87	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T279	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T278	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	1		T13	6		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T215	12		T131	1		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T2	12		T48	13		T140	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T27	7		T28	2		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T29	3		T134	1		T126	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T36	1		T130	4		T80	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T11	10		T37	1		T142	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T131	1		T140	9		T15	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	14		T141	15		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	13		T217	1		T128	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T2	1		T152	12		T282	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	6		T8	1		T29	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T130	13		T139	1		T125	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	9		T48	12		T42	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T13	6		T100	1		T132	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T2	13		T12	1		T59	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	384	1			T12	14		T100	1		T130	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1446	1			T6	2		T14	1		T83	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17758	1			T1	120		T4	20		T5	32
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T30	11		T87	7		T286	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T278	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T37	9		T232	14		T224	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T215	9		T217	7		T236	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T2	13		T48	15		T140	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T27	4		T36	12		T48	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T29	11		T148	7		T140	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T36	13		T80	7		T216	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T142	13		T16	5		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T140	9		T15	1		T129	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T141	12		T31	1		T163	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T217	3		T128	9		T129	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T152	14		T282	10		T258	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	1		T8	14		T29	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T163	6		T165	7		T238	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T48	13		T42	10		T129	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T42	7		T15	1		T229	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	11		T12	2		T138	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T12	12		T133	9		T148	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1394	1			T6	18		T34	25		T35	23

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

auto[0]

4263

1

T2

24

T5

1

T6

18