Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27054

1

T1

120

T2

50

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23644

1

T1

120

T4

20

T5

39

auto[ADC_CTRL_FILTER_COND_OUT]

3410

1

T2

50

T3

1

T8

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21009

1

T1

120

T2

50

T4

20

auto[1]

6045

1

T3

1

T5

7

T6

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22998

1

T1

120

T2

27

T3

1

auto[1]

4056

1

T2

23

T5

2

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	5	1			T94	5		-	-		-	-
values[0]	77	1			T141	2		T215	21		T287	31
values[1]	705	1			T28	2		T37	11		T141	27
values[2]	590	1			T100	1		T163	14		T142	7
values[3]	765	1			T12	29		T27	11		T100	1
values[4]	722	1			T36	13		T29	4		T59	1
values[5]	670	1			T7	14		T8	15		T48	25
values[6]	709	1			T2	24		T11	22		T36	10
values[7]	636	1			T5	7		T36	14		T29	19
values[8]	3084	1			T2	25		T3	1		T6	20
values[9]	1333	1			T2	1		T11	10		T13	6
minimum	17758	1			T1	120		T4	20		T5	32

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	917	1			T28	2		T37	1		T141	29
values[1]	766	1			T12	3		T27	11		T37	23
values[2]	685	1			T12	26		T100	2		T36	13
values[3]	708	1			T29	4		T132	10		T42	16
values[4]	748	1			T2	24		T7	14		T8	15
values[5]	604	1			T11	22		T36	10		T29	19
values[6]	2915	1			T5	7		T6	20		T14	1
values[7]	789	1			T2	25		T3	1		T13	6
values[8]	988	1			T2	1		T11	10		T13	6
values[9]	163	1			T132	8		T127	13		T233	23
minimum	17771	1			T1	120		T4	20		T5	32

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

4263

1

T2

24

T5

1

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T141	13		T215	10		T133	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T28	2		T37	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T37	10		T139	1		T127	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	3		T27	8		T37	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	13		T32	2		T176	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T100	2		T36	13		T59	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T132	1		T42	8		T16	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T29	2		T131	1		T213	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T7	1		T48	14		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	12		T8	15		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T36	10		T131	1		T217	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T11	2		T29	10		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1571	1			T5	5		T6	20		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T237	9		T254	4		T233	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T13	1		T215	18		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	14		T3	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	366	1			T11	1		T13	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	1		T29	12		T48	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T272	5		T267	9		T288	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T132	1		T127	13		T233	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17645	1			T1	120		T4	20		T5	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T289	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T141	14		T215	11		T149	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T141	1		T31	1		T126	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T149	10		T228	1		T220	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T27	3		T30	13		T142	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T12	13		T32	4		T229	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T130	17		T48	12		T232	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T132	9		T42	8		T16	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T29	2		T148	3		T140	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	13		T48	11		T125	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T2	12		T125	10		T149	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T135	15		T152	13		T223	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	20		T29	9		T130	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	973	1			T5	2		T83	8		T98	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T254	3		T233	10		T228	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	5		T215	17		T214	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	11		T214	6		T126	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T11	9		T13	5		T42	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T29	2		T48	6		T80	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T272	2		T267	6		T288	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T132	7		T233	10		T269	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T29	2		T59	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T289	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T94	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T215	10		T253	10		T290	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T141	1		T287	15		T246	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T37	10		T141	13		T133	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T28	2		T37	1		T31	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T228	1		T176	2		T220	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T100	1		T163	7		T142	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T12	13		T139	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T12	3		T27	8		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T132	1		T32	2		T33	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T36	13		T29	2		T59	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	1		T48	14		T42	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T8	15		T125	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T36	10		T131	1		T217	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	12		T11	2		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	5		T36	14		T140	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T29	10		T142	14		T237	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1640	1			T6	20		T13	1		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T2	14		T3	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	468	1			T11	1		T13	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T2	1		T29	12		T132	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17645	1			T1	120		T4	20		T5	32
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T94	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T215	11		T253	7		T290	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T141	1		T287	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T141	14		T149	9		T226	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T31	1		T126	16		T148	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T228	1		T220	11		T282	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T163	7		T142	4		T129	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	13		T149	10		T238	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T27	3		T48	12		T30	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T132	9		T32	4		T33	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T29	2		T130	17		T232	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	13		T48	11		T42	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T125	10		T149	5		T129	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T135	15		T188	2		T181	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T2	12		T11	20		T130	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T140	12		T129	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T29	9		T142	11		T254	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T13	5		T83	8		T98	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	11		T126	12		T163	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T11	9		T13	5		T42	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T29	2		T132	7		T48	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T29	2		T59	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T141	15		T215	12		T133	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T28	2		T37	1		T141	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T37	1		T139	1		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	1		T27	7		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	14		T32	6		T176	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T100	2		T36	1		T59	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T132	10		T42	9		T16	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T29	3		T131	1		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T7	14		T48	12		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	13		T8	1		T125	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T36	1		T131	1		T217	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	22		T29	12		T130	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T5	6		T6	2		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T237	1		T254	4		T233	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	6		T215	18		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T2	12		T3	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T11	10		T13	6		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	1		T29	3		T48	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T272	3		T267	7		T288	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T132	8		T127	1		T233	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17758	1			T1	120		T4	20		T5	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T289	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T141	12		T215	9		T133	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T148	10		T163	6		T218	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T37	9		T127	5		T220	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	2		T27	4		T37	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	12		T229	13		T240	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T36	12		T48	15		T232	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T42	7		T16	5		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T29	1		T213	15		T148	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T48	13		T33	7		T237	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	11		T8	14		T129	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T36	9		T217	5		T231	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T29	7		T148	15		T142	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T5	1		T6	18		T34	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T237	8		T254	3		T233	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T215	17		T142	12		T282	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	13		T163	12		T255	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T42	10		T138	8		T217	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T29	11		T48	8		T80	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T272	4		T267	8		T288	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T127	12		T233	12		T258	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T94	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T215	12		T253	8		T290	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T141	2		T287	17		T246	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T37	1		T141	15		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T28	2		T37	1		T31	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T228	2		T176	2		T220	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T100	1		T163	8		T142	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	14		T139	1		T149	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	1		T27	7		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T132	10		T32	6		T33	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T36	1		T29	3		T59	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	14		T48	12		T42	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T8	1		T125	11		T149	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T36	1		T131	1		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	13		T11	22		T130	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	6		T36	1		T140	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T29	12		T142	12		T237	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T6	2		T13	6		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T2	12		T3	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	401	1			T11	10		T13	6		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T2	1		T29	3		T132	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17758	1			T1	120		T4	20		T5	32
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T215	9		T253	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T287	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T37	9		T141	12		T133	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T148	10		T218	6		T234	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T220	8		T263	7		T291	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T163	6		T142	2		T129	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	12		T238	5		T188	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	2		T27	4		T37	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T33	7		T17	1		T229	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T36	12		T29	1		T232	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T48	13		T42	7		T16	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T8	14		T129	14		T263	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T36	9		T217	5		T188	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T2	11		T148	15		T221	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T5	1		T36	13		T140	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T29	7		T142	13		T237	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T6	18		T34	25		T35	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	13		T163	12		T152	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	389	1			T42	10		T138	8		T217	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T29	11		T48	8		T80	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

auto[0]

4263

1

T2

24

T5

1

T6

18