Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27054

1

T1

120

T2

50

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23217

1

T1

120

T2

1

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3837

1

T2

49

T3

1

T5

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21148

1

T1

120

T2

24

T3

1

auto[1]

5906

1

T2

26

T5

7

T6

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22998

1

T1

120

T2

27

T3

1

auto[1]

4056

1

T2

23

T5

2

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T2	1		T149	11		T292	6
values[0]	78	1			T11	13		T59	1		T127	13
values[1]	617	1			T28	2		T36	13		T29	4
values[2]	576	1			T7	14		T100	1		T36	10
values[3]	679	1			T11	9		T12	3		T13	6
values[4]	846	1			T36	14		T29	14		T130	15
values[5]	3203	1			T2	24		T6	20		T8	15
values[6]	704	1			T130	4		T48	15		T42	32
values[7]	725	1			T3	1		T11	10		T12	26
values[8]	708	1			T48	25		T141	27		T133	10
values[9]	1137	1			T2	25		T5	7		T13	6
minimum	17758	1			T1	120		T4	20		T5	32

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	863	1			T11	13		T28	2		T36	13
values[1]	580	1			T7	14		T100	1		T36	10
values[2]	798	1			T12	3		T13	6		T36	14
values[3]	3071	1			T6	20		T11	9		T14	1
values[4]	890	1			T2	24		T8	15		T37	10
values[5]	598	1			T130	4		T132	1		T48	15
values[6]	946	1			T3	1		T11	10		T12	26
values[7]	565	1			T48	25		T133	10		T31	3
values[8]	818	1			T2	26		T5	7		T13	6
values[9]	167	1			T30	1		T163	24		T228	13
minimum	17758	1			T1	120		T4	20		T5	32

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

4263

1

T2

24

T5

1

T6

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T11	1		T59	1		T132	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T28	2		T36	13		T29	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	1		T30	15		T213	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T100	1		T36	10		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T13	1		T36	14		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	3		T29	12		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1640	1			T6	20		T14	1		T83	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T11	1		T130	1		T212	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T8	15		T29	10		T42	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T2	12		T37	10		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T126	1		T15	5		T268	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T130	1		T132	1		T48	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T141	13		T214	1		T217	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T3	1		T11	1		T12	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T133	10		T31	2		T148	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T48	14		T214	1		T217	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	1		T27	8		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T2	14		T5	5		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T30	1		T163	13		T228	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T246	14		T293	1		T294	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17645	1			T1	120		T4	20		T5	32
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	12		T132	7		T215	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T29	2		T141	1		T31	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	13		T30	13		T263	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T132	9		T215	17		T32	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	5		T148	10		T142	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T29	2		T125	10		T149	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	977	1			T83	8		T98	21		T99	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	8		T130	14		T140	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T29	9		T42	4		T138	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	12		T125	7		T233	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T126	12		T15	1		T268	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T130	3		T48	6		T42	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T141	14		T214	6		T226	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T11	9		T12	13		T232	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T31	1		T148	14		T142	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T48	11		T214	11		T221	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T27	3		T130	12		T80	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	11		T5	2		T13	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T163	11		T228	9		T284	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T246	15		T293	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T29	2		T59	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T2	1		T292	6		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T149	1		T295	1		T294	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T11	1		T59	1		T127	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T296	1		T285	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T132	1		T215	10		T148	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T28	2		T36	13		T29	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	1		T213	16		T214	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T100	1		T36	10		T32	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	1		T30	15		T218	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T11	1		T12	3		T215	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T36	14		T48	16		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T29	12		T130	1		T140	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1654	1			T6	20		T8	15		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T2	12		T37	10		T212	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T42	11		T126	1		T271	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T130	1		T48	9		T42	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T214	1		T217	4		T218	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	1		T11	1		T12	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T141	13		T133	10		T31	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T48	14		T232	15		T217	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T27	8		T130	1		T80	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T2	14		T5	5		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17645	1			T1	120		T4	20		T5	32
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T149	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T11	12		T135	9		T181	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T296	8		T285	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T132	7		T215	11		T148	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T29	2		T132	9		T141	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	13		T214	4		T263	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T32	4		T128	3		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	5		T30	13		T254	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	8		T215	17		T125	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T48	12		T148	10		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T29	2		T130	14		T140	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T83	8		T98	21		T99	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T2	12		T125	7		T226	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T42	4		T126	12		T268	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T130	3		T48	6		T42	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T214	6		T15	1		T175	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	9		T12	13		T126	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T141	14		T31	1		T148	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T48	11		T232	5		T140	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T27	3		T130	12		T80	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T2	11		T5	2		T13	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T29	2		T59	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	13		T59	1		T132	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T28	2		T36	1		T29	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	14		T30	17		T213	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T100	1		T36	1		T132	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T13	6		T36	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	1		T29	3		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T6	2		T14	1		T83	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T11	9		T130	15		T212	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T8	1		T29	12		T42	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T2	13		T37	1		T125	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T126	13		T15	5		T268	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T130	4		T132	1		T48	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T141	15		T214	7		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T3	1		T11	10		T12	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T133	1		T31	3		T148	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T48	12		T214	12		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	1		T27	7		T130	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T2	12		T5	6		T13	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T30	1		T163	12		T228	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T246	16		T293	9		T294	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17758	1			T1	120		T4	20		T5	32
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T215	9		T148	7		T163	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T36	12		T29	1		T31	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T30	11		T213	15		T240	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T36	9		T215	17		T217	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T36	13		T148	10		T218	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	2		T29	11		T276	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T6	18		T34	25		T35	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T212	6		T140	11		T33	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T8	14		T29	7		T42	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T2	11		T37	9		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T15	1		T137	5		T238	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T48	8		T42	7		T249	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T141	12		T217	3		T218	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	12		T232	14		T140	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T133	9		T148	15		T142	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T48	13		T217	5		T221	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T27	4		T163	6		T140	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T2	13		T5	1		T37	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T163	12		T228	3		T284	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T246	13		T294	3		T297	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T2	1		T292	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T149	11		T295	1		T294	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T11	13		T59	1		T127	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T296	9		T285	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T132	8		T215	12		T148	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T28	2		T36	1		T29	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	14		T213	1		T214	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T100	1		T36	1		T32	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T13	6		T30	17		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	9		T12	1		T215	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T36	1		T48	13		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T29	3		T130	15		T140	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T6	2		T8	1		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T2	13		T37	1		T212	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T42	5		T126	13		T271	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T130	4		T48	7		T42	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T214	7		T217	1		T218	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	1		T11	10		T12	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T141	15		T133	1		T31	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T48	12		T232	6		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T27	7		T130	13		T80	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T2	12		T5	6		T13	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17758	1			T1	120		T4	20		T5	32
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T292	5		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T294	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T127	12		T181	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T285	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T215	9		T148	7		T298	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T36	12		T29	1		T31	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T213	15		T163	5		T240	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T36	9		T221	2		T165	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T30	11		T218	5		T254	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	2		T215	17		T266	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T36	13		T48	15		T148	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T29	11		T140	11		T33	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T6	18		T8	14		T34	25
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T2	11		T37	9		T212	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T42	10		T165	7		T238	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T48	8		T42	7		T229	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T217	3		T218	6		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	12		T129	14		T16	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T141	12		T133	9		T148	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T48	13		T232	14		T217	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T27	4		T163	18		T140	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T2	13		T5	1		T37	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22791

1

T1

120

T2

26

T3

1

auto[1]

auto[0]

4263

1

T2

24

T5

1

T6

18